EE260: Digital Design, Spring n More Logic Gates n NAND and NOR Gates

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1 EE26: igital esign, Spring 28 -eb-8 EE 26: Introduction to igital esign oolean lgebra: Logic Synthesis and Timing Hazards ao Zheng epartment of Electrical Engineering University of Hawaiʻi at Mānoa Overview n More Logic Gates n NN and NOR Gates n NN and NOR circuits n Two-level Implementations n Multilevel Implementations n Exclusive-OR (OR) Gates n Odd unction n Parity Generation and hecking More Logic Gates n We can construct any combinational circuit with N, OR, and NOT gates UER, NN and NOR n dditional logic gates are used for practical reasons OR and NOR NN Gate OR: not-equal gate NOR: equal gate = Å = Å n Known as a universal gate because N digital circuit can be implemented with NN gates alone. n To prove the above, it suffices to show that N, OR, and NOT can be implemented using NN gates only. hapter 3: Logic Synthesis and Timing Hazards

2 EE26: igital esign, Spring 28 -eb-8 NN Gate Emulation NN ircuits = ( ) = + = = (( ) ) = ( + ) = = = ( ) = + = + = = + n To easily derive a NN implementation of a boolean function: n ind a simplified SOP n SOP is an N-OR circuit n hange N-OR circuit to a NN circuit n Use the alternative symbols below N-OR (SOP) Emulation Using NNs N-OR (SOP) Emulation Using NNs (cont.) a) Original SOP Two-level implementations b) Implementation with NNs Verify: (a) G = W + Z (b) G = ( (W) (Z) ) = (W) + (Z) = W + Z SOP with NN (again!) Two-Level NN Gate Implementation - Example (a) (b) (c) Original SOP ouble inversion and grouping Replacement with NNs N-NOT NOT-OR (,,Z) = Sm(,6). Express in SOP form: = Z + Z 2. Obtain the N-OR implementation for. 3. dd bubbles and inverters to transform N-OR to NN-NN gates. hapter 3: Logic Synthesis and Timing Hazards 2

3 EE26: igital esign, Spring 28 -eb-8 Example (cont.) Two-level implementation with NNs = Z + Z Multilevel NN ircuits Starting from a multilevel circuit:. onvert all N gates to NN gates with N-NOT graphic symbols. 2. onvert all OR gates to NN gates with NOT-OR graphic symbols. 3. heck all the bubbles in the diagram. or every bubble that is not counteracted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance. Example et nother Example! Use NN gates and NOT gates to implement Z=E (+ + )+GH + + E (+ + ) E (+ + )+GH NOR Gate n lso a universal gate because N digital circuit can be implemented with NOR gates alone. n This can be similarly proven as with the NN gate NOR ircuits n To easily derive a NOR implementation of a boolean function: n ind a simplified POS n POS is an OR-N circuit n hange OR-N circuit to a NOR circuit n Use the alternative symbols below hapter 3: Logic Synthesis and Timing Hazards 3

4 EE26: igital esign, Spring 28 -eb-8 Two-Level NOR Gate Implementation - Example (,,Z) = Sm(,6). Express in SOP form:. = Sm(,2,3,4,5,7) = Z + Z + Z + Z + Z + Z 2. = + + Z 2. Take the complement of to get in the POS form: = ( )' = ('+)(+')Z' 3. Obtain the OR-N implementation for. 4. dd bubbles and inverters to transform OR- N implementation to NOR-NOR implementation. Example (cont.) Two-level implementation with NORs = ( )' = ('+)(+')Z' Multilevel NOR ircuits Starting from a multilevel circuit:. onvert all OR gates to NOR gates with OR-NOT graphic symbols. 2. onvert all N gates to NOR gates with NOT-N graphic symbols. 3. heck all the bubbles in the diagram. or every bubble that is not counteracted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance. Exclusive-OR (OR) unction n OR (also Å) : the not-equal function n OR(,) = Å = + n Identities: n Å = n Å = n Å = n Å = n Properties: n Å = Å n ( Å ) Å W = Å ( Å W) OR function implementation OR circuit with 4 NNs n OR(a,b) = ab + a b n Straightforward: 5 gates n 2 inverters, two 2-input Ns, one 2-input OR n 2 inverters & 3 2-input NNs n Nonstraightforward: n 4 NN gates hapter 3: Logic Synthesis and Timing Hazards 4

5 EE26: igital esign, Spring 28 -eb-8 OR circuit with 4 NNs SMRT ESIGN REUE TIVE EVIES On-hip SRM on logic chip RM on memory chip [ rom oss, R.. Implementing pplication- Specific Memory, ISS 996 ] 8 Exclusive-NOR (NOR) unction n NOR: the equality function n NOR(a,b) = ab + a b n Observe that NOR(a,b) = ( OR(a,b) ) n ( a Å b ) = ( a b + ab ) = (a b) (ab ) = (a + b ) (a +b) = ab + a b n a Å b = ( a Å b ) = a Å b n xåy = x y + xy Odd unction n xåyåz = xy z + x yz + x y z +xyz n xåyåzåw = x yzw + xy zw + xyz w + xyzw + x y z w + x yz w + x y zw +xy z w n Observe a pattern here? n n n-input OR function is implied (=) by all the minterms that have an odd # of s n Thus, OR is also know as the odd function Odd unction (cont.) Odd unction (cont.) Minterms are LWS distance two from each other hapter 3: Logic Synthesis and Timing Hazards 5

6 EE26: igital esign, Spring 28 -eb-8 Even unction n How would you implement an even function? The complement of OR à NOR Parity Generation and hecking n Odd and even functions can be used to implement parity checking circuits used for error detection and correction. n Use even parity as example. n Parity generator: the circuit that generates the parity bit before transmitting. n Parity checker: the circuit that checks the parity in the receiver. Even Parity Generation Even Parity hecking How would you implement a parity checker for the previous example? n P(,,Z) must produce a for all the input combinations that contain an odd number of s n Thus, it is a 3-input odd function P = ÅÅZ Use a 4-input OR circuit (odd function) = ÅÅZÅP à indicates an error OR 4-input NOR circuit (even function) = (ÅÅZÅP) à indicates a pass Transmission Gates n The transmission gate is one of the designs for an electronic switch for connecting and disconnecting two points in a circuit: TG (a) = and = (b) = and = (c) (d) TG Transmission Gates (continued) n In many cases, can be regarded as a data input and as an output. and, with complementary values applied, is a control input. n With these definitions, the transmission gate, provides a 3-state output: n =, = ( = or ) n =, = Hi-Z n are needs to be taken when using the TG in design, however, since and as input and output are interchangeable, and signals can pass in both directions. hapter 3: Logic Synthesis and Timing Hazards 6

7 EE26: igital esign, Spring 28 -eb-8 ircuit Example Using TG n Exclusive OR = + n (a) TG TG TG No path Path Path No path Path Path The basis for the function implementation is TG controlled paths to the output (b) TG No path No path More omplex Gates n The remaining complex gates are SOP or POS structures with and without an output inverter. n The names are derived using: n - N n O - OR n I - Inverter n Numbers of inputs on first-level gates or directly to second-level gates More omplex Gates (continued) n Example: OI - N-OR-Invert consists of a single gate with N functions driving an OR function which is inverted. n These gate types are used because: n The number of transistors needed is fewer than required by connecting together primitive gates n Potentially, the circuit delay is smaller, increasing the circuit operating speed n Timing diagrams n Hazards n Static Hazards n ynamic Hazards n Mitigation Timing Hazards oncepts of elays and Timing n or a given gate, the gate delay refers to the time it takes the output signal to respond to in input transition n Why is there a gate delay? n n Gate elays There are actual resistances and capacitances inside digital logic If you apply a unit step voltage signal to an input, the output will not respond immediately, but after a delay proportional to R. Resistance of driver outpu t input Input Output T delay = R. apacitance of load hapter 3: Logic Synthesis and Timing Hazards 7

8 EE26: igital esign, Spring 28 -eb-8 Timing diagrams (waveforms) n Shows time-response of circuits n Like a sideways truth table n Example: = + Timing diagrams n Real gates have real delays n Example: ' =? time width of 3 gate delays n elays cause transient = = + in 2-level logic Timing diagram for = + canonical sum-of-products n Time waveforms for 4 are identical except for glitches 2 minimized sum-of-products 3 canonical product-of-sums minimized product-of-sums 4 Hazards and glitches n glitch: unwanted output n circuit with the potential for a glitch has a hazard. n Glitches occur when different pathways have different delays n auses circuit noise n angerous if logic makes a decision while output is unstable Hazards and glitches n Solutions n esign hazard-free circuits n ifficult when logic is multilevel n Wait until signals are stable hapter 3: Logic Synthesis and Timing Hazards 8

9 EE26: igital esign, Spring 28 -eb-8 Types of hazards n Static -hazard n Output should stay logic n Gate delays cause brief glitch to logic n Static -hazard n Output should stay logic n Gate delays cause brief glitch to logic Static hazards n Often occurs when a literal and its complement momentarily assume the same value n Through different paths with different delays n auses an (ideally) static output to glitch n ynamic hazards n Output should toggle cleanly n Gate delays cause multiple transitions Static hazards Timing diagram for = + multiplexer S S S' S' static- hazard = + in 2-level logic Static hazards canonical product-of-sums 3 hapter 3: Logic Synthesis and Timing Hazards 9

10 EE26: igital esign, Spring 28 -eb-8 Timing diagram for = + = + in 2-level logic canonical sum-of-products ynamic hazards ynamic hazards n Often occurs when a literal assumes multiple values n Through different paths with different delays n auses an output to toggle multiple times ynamic hazards ynamic hazard Eliminating static hazards Eliminating static hazards n Key idea: Glitches happen when a changing input spans separate K-map encirclements n : à n Example: to change can cause a static- glitch ' ' = ' + ' hapter 3: Logic Synthesis and Timing Hazards

11 EE26: igital esign, Spring 28 -eb-8 Eliminating static hazards Eliminating static hazards n Solution: dd redundant K-map encirclements n Ensure that all single-bit changes are covered by same block n irst eliminate static- hazards: Use SOP form n If need to eliminate static- hazards, use POS form n Technique only works for 2-level logic = ' + ' + ' ' ' ' Summary of hazards n We can eliminate static hazards in 2-level logic for single-bit changes n Eliminating static hazards also eliminates dynamic hazards n Hazards are a difficult problem n Multiple-bit changes in 2-level logic are hard n Static hazards in multilevel logic are harder n ynamic hazards in multilevel logic are harder yet hapter 3: Logic Synthesis and Timing Hazards

SYNTHESIS OF COMBINATIONAL CIRCUITS

SYNTHESIS OF COMBINATIONAL CIRCUITS HPTER 6 SYNTHESIS O OMINTIONL IRUITS 6.1 Introduction oolean functions can be expressed in the forms of sum-of-products and productof-sums. These expressions can also be minimized using algebraic manipulations