Digital Logic Design ELCT 201

Transcription

1 Faculty of Information Engineering and Technology Dr. Haitham Omran and Dr. Wassim Alexan Digital Logic Design ELCT 201 Winter 2017 Midterm Exam Second Chance Please tick the box of your major: IET MET MCTR EMS EDPT Please read carefully before proceeding a) The duration of the exam is 2 hours. b) Calculators are permitted for this exam. c) Write your solutions in the space provided. If you need more space, write on the back of sheet containing the problem. d) Attempt as many of the problems as you can within the time limit. The more you solve the higher your score is expected to be. e) This exam booklet contains 15 pages, including this one. f) Two extra sheets have been added at the end of the exam. Please do not write anything below Problem Total Maximum Marks Obtained Marks

2 Problem 1 (10 marks) There are 10 multiple choice questions (MCQs). You are required to solve them all and fill in your answer in the following table. Any answers for these 10 MCQs outside of the table will not be graded! Fill in your answers in the table, by marking a tick ( ) in the right place. MCQ # 1 A B C D ) A tri-state buffer has 3 states: logic 0, logic 1 and a third state that is called high impedance, which A. Behaves like a closed circuit B. Behaves like a buffer C. Behaves like an inverter D. Behaves like an open circuit 2) Which of the following combinational logic circuits can model an electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number? A. A magnitude comparator B. A multiplexer C. A number analyzer 2/15

3 D. A parity checker 3) How many full adders are required to build a 4-bit ripple carry adder? A. 4 B. C. D. 3 4) What does a parity checker circuit do? A. Checks for errors in a communication system B. Routes a single signal into one of many possible routes C. Reduces errors in a communication system D. Checks the bits in a bit stream and applies an inversion process 5) Why are digital circuits often designed and implemented using NAND and NOR gates instead of AND and OR gates? A. Because NAND and NOR gates can withstand higher temperature and pressure B. Because NAND and NOR gates are cheaper, as they have a lower number of transistors than AND and OR gates C. Because NAND and NOR gates are harder to fabricate with electronic components D. Because NAND and NOR gates are more readily available commercially 6) In a 3-variable K-map, how many adjacent squares would result in a term with a single literal? A. 2 B. 4 C. 8 D. 16 7) Which logic gate is missing from the following figure? A. XOR B. INVERTER C. XNOR D. AND 3/15

4 Fig. 1. Some logic gates 8) Which of the following circuits has the longest signal propagation delay? A. A full adder B. A half adder C. A circuit containing four AND gates D. A 4-bit binary ripple carry adder 9) Digital logic circuits in which the logic states of the inputs at any given instant do not solely determine the state of the output are called A. Combinational logic circuits B. Reasonable logic circuits C. Automated logic circuits D. Sequential logic circuits 10) Which of the following is not one of the steps of combinational logic circuit design? A. From the specifications of the circuit, determining the required number of inputs and outputs and assigning a symbol to each B. Deriving the truth table that defines the required relationship between the inputs and the outputs C. Sketching the logic diagram, showing the various logic gates needed for implementation D. From the specifications of the circuit, determining the required number of transistors and assigning a symbol to each NOTE: Remember to fill in your answers to the MCQs in the table provided on page 2. 4/15

5 Problem 2 (15 marks) Consider a digital system that takes as input 4 bits. The output of this system is set to HIGH (logical 1) only when the decimal equivalent of the input bits is one of the terms of the Fibonacci sequence. Note that the first few terms of the Fibonacci sequence are as follows: You are required to: i. Write down the truth table of this system ii. Simplify the Boolean expression of the output iii. Sketch the logic diagram of the circuit, using only NAND gates 5/15

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7 Problem 3 (20 marks) Using decoders and basic logic gates only, design both a parity generation circuit for a 4-bit data (3-bit message with an odd parity bit) to be transmitted by computer, and a receiving circuit in computer, which will generate an error bit,, if the 4-bit data received has an even parity; Otherwise,. You are required to: i. Write down the truth tables for each of the circuits. The first includes the three bits (x,y,z) and the parity bit P, while the second includes the three bits (x,y,z), the parity bit P and the error bit check E ii. Obtain the simplified Boolean expression of P and E, by using a K-map iii. Sketch the logic diagram of the circuits, using decoders and basic logic gates 7/15

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10 Problem 4 (10 marks) Simplify the following expression, using K-maps (without the use of any Boolean simplifications) and implement it using NAND gates only: Where 10/15

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12 Problem 5 (10 marks) a) By analyzing the following logic diagram, write down the Boolean expressions of the outputs S and C. 12/15

13 b) Using a single multiplexer and basic logic gates only, design a circuit that implements the following Boolean expression: You are required to: i. Write down the truth table ii. State the multiplexer size that you are going to use iii. Sketch the logic diagram of the circuit 13/15

14 First scratch sheet 14/15

15 Second scratch sheet 15/15