FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

Transcription

1 HAPTER FUNTION OF OMBINATIONAL LOGI IRUIT OUTLINE HALF-ADDER ANF FULL ADDER IRUIT -BIT PARALLEL BINARY RIPPLE ARRY ADDER -BIT PARALLEL BINARY ARRY LOOK- AHEAD ADDER BD ADDER IRUIT DEODER ENODER MULTIPLEXER DEMULTIPLEXER ODE ONVERTER PARITY GENERATOR & HEKER

2 In the previous chapter, we already look at how combinational circuit operates. Now we will look at some specific function logic circuit.. HALF ADDER AND FULL ADDER IRUIT An adder circuit will add up two -bit binary numbers and produces the SUM and ARRY. The difference between half adder and full adder is that a full adder has a ARRY IN input besides the two -bit binary input. This adder circuit is a component in a computer ALU. Before we start with the design, let s revise on binary arithmetic operation. Binary addition ( carry) ( carry) REMEMBER Binary arithmetic operations are not the same with Boolean expression operation. Half Adder ircuit A half adder circuit will a -bit binary number (lets name it as A ) with - bit binary number ( B ) and will produce -bit SUM and -bit ARRY OUT ( for short) output. So, this circuit will have two input (a and b) O and two output (SUM and o ) Figure. Block Diagram of a half adder. A FA B SUM o It s a good practice to start every design with a block diagram get the whole picture of the system Now, we start by building the truth table. Figure. Truth table for a half adder A (input) B (input) SUM (output) o (output) (low) (low) (low) (low) (low) (high) (high) (low) (high) (low) (high) (low) (high) (high) (low) (high)

3 From the truth table we get the expression for SUM and SUM A B A B A B o below. o A B Figure.3 ircuit for a half adder Drawing the combined two circuit, A B SUM o Figure. ircuit for a half adder (using X-OR) Or A B SUM o For a full adder circuit, it has an extra -bit input in. Therefore, the truth table will have three -bit inputs and two -bit outputs. Figure. Block diagram for a full adder circuit in A FA SUM o B Figure.6 Truth table for a full adder A (input) B (input) in (input) SUM (output) o (output) (low) (low) (low) (low) (low) (low) (low) (high) (high) (low) (low) (high) (low) (high) (low) (low) (high) (high) (low) (high) (high) (low) (low) (high) (low) (high) (low) (high) (low) (high) (high) (high) (low) (low) (high) (high) (high) (high) (high) (high)

4 From the truth table, we get expression SUM and. o SUM A B A (B A B A B A B in in in in Bin ) A (Bin B) in A (B in ) A (B A (B ) in in ) in o A B A B A B A B A B A B in in in in in in A B A B A B in in in A (B A ( A in in in A B in A B( A B B) B) A B in (A B A) A B in (B A) A B A B A B in in in A B in ) in Try to do simplification of o using the k-map and compare the result. Figure.7 Full adder circuit As a result, the circuit will be A B in SUM o Full adder using two half adder. Take a look back at the un-simplified o. Let s do the simplification using different theorem to get a simplified expression in XOR form. o A B A B in in in in A B A B in in A B A B (A B A B) A B (A B) A B in A B in Therefore the circuit will be like this 3

5 Figure.8 Modified full adder circuit A B in SUM o an you spot the two half adder in figure.8? In a block diagram, a full adder build from two half adder are shown in figure.9. Figure.9 Modified full adder circuit A HA A HA SUM B in o. -BIT PARALLEL BINARY RIPPLE ARRY ADDER In short, a -bit parallel binary ripple carry adder is a circuit that will add up a -bit binary number (A, A 3, A and A ) with another -bit binary adder (B, B 3, B and B ) and -bit ARRY IN ( in ) that produce a -bit SUM (, 3, and ) and -bit ARRY OUT ( ) output. Figure. Block diagram of a -bit parallel binary adder S S3 S S -bit binary SUM -bit binary number A A A3 A A -BIT PARALLEL BINARY ADDER B B3 B B -bit binary number B in REMEMBER are in disabled by connecting it to ground (logic ). NEVER let any input floating. This circuit is actually comprises of four -bit adder (with the in of the LSB is grounded/disabled) or with three -bit full adder and one -bit half adder (we don t need the in anyway). The term ripple is to describe the carry that rippled from one full adder to the next one.

6 Figure. Block diagram of a -bit parallel binary adder using four - bit full adder A 3 FA (MSB) B A3 FA B3 A FA B A FA B in S3 S S S Operation of a -bit Parallel Adder Example. If [A] = and [B] = are applied to a -bit parallel adder, what is the resulting [] and? REMEMBER The [ ] bracket is to indicate a register. Therefore, [A] can be more than -bit binary. We will see more of this notation in register and counter hapter 6. Figure. Solution for example. FA (MSB) FA FA FA in 3 = A3+B3+3 = ++ = + (carry) = A+B+ = ++ = + (carry) = A+B+ = ++ = + (carry) = A+B+in = ++ = + (carry) In example., the operation (in decimal) is 5+3=8 (taking as MSB for ). This analysis is for an unsigned binary operation. In a signed binary operation, it is 5 ( 3) (by ignoring ). This is also correct. Example. If [A] = and [B] = are applied to a -bit parallel adder, what is the resulting [] and? 5

7 Figure. Solution for example. FA (MSB) FA FA FA in S3 = A3+B3+3 = ++ = + (carry) S = A+B+ = ++ = + (carry) S = A+B+ = ++ = + (carry) S = A+B+in = ++ = + (carry) In example., the analysis is for an unsigned binary operation is 5 9 (taking as MSB for ). In a signed binary operation, it is 5 ( ) 7 (by ignoring ). This is not correct (supposed to be +9) because there is an overflow occurred. Because this circuit only adds without knowing whether it is a signed or unsigned number, another circuit for detecting overflow occurrence and do the correction are required (we will not cover this overflow circuit in this subject). So, we have an adder. But an ALU still need to do subtraction. We can build a dedicated subtractor for this, or alternatively, we can still use the adder for subtractor. This can be done by changing the addend to its s complement form ( A B A ( B) ). Although a dedicated subtractor circuit may benefit in term of speed, but it will also increase cost. To change a binary number into its s complement form, first we need to complement the entire bit and add. We can complement a binary bit using a NOT gate. It s a simple solution, but we lose the add function of the adder. We need a means to control the operation of the adder to add or sub. This where the XOR gate comes in. Let s do some examination on XOR gate first. 6

8 Figure.3 XOR gate characteristic A B Z When A is, B = Z not inverted When A is, B = Z inverted From figure.3, we can use a XOR gate for inverting the bits, by setting the control bit (A) a high (), or not by setting A to low (). The next part is to add to the complemented binary numbers. Remember the in that are connected to ground? We can use this to add, and also as a control bit to control the XOR. Figure. show the adder/subtractor circuit. Figure. -bit parallel adder/ subtractor o A A3 A A -BIT PARALLEL BINARY ADDER S S3 S S -bit binary SUM -bit binary number A Adder/Subtractor ontrol B B B3 B -bit binary number B The bar on top of the adder label but not on top of subtractor label indicates that: if it add if it sub The 7LS83: -bit Parallel Adder To connect four -bit full-adder to build a -bit parallel adder for an application is a tedious work. The 7LS83 is a -bit parallel adder in form of integrated circuit (I). An I is a specific function combinational logic circuit. The number of the I described its family, technology and operation. 7

9 Figure. I 7LS83: -bit parallel adder pin diagram (left) and logic symbol (right) Σ B A 3 Σ A 5 B 6 7 GND 8 7LS Vc c B3 A3 Σ3 A B Σ (5) (3) () () (6) () (5) () (7) 3 3 o Vcc (6) S A S B 3 () () (3) () (9) (8) Gnd 7LS83: -bit Binary Adder with Fast arry LAB I s I 7LS83: - bit parallel adder with fast carry pin diagram (left) and logic symbol (right) A Σ3 A3 3 B3 Vc c Σ B A LS B Σ GND B A Σ () (8) (3) () () (7) () (6) (3) 3 3 o Vcc (5) S A S B 3 (9) (6) () (5) () () Gnd We can also cascade (connect) two of this I to build an 8-bit parallel adder. The of the lower nibble are connected to the in of the upper nibble. 8

10 Figure. ascading two unit of I 7LS83 to build an 8-bit adder A A A3 A B B B3 B (5) (3) () () (6) () (5) () (7) 3 3 o Vcc (6) A5 (5) (3) A6 A () () A7 () () A8 (3) (6) 3 3 B5 () () B B6 (5) B7 B8 () (9) (7) Gnd 3 3 o Vcc (6) A B Gnd 3 () () (3) () (9) (8) (8).3 -BIT ARRY LOOK-AHEAD ADDER One shortcoming of a ripple carry adder is that every carry generated from each full adder (stage) introduce some delay before the next stage can evaluate its carry to be send to the next stage. This delay is accumulated, and the more number of stages there is, the bigger the delay. A carry look-ahead adder eliminates these ripple carry by anticipating the (for a -bit adder case). Actually, carry can be categorized into two types, generated carry ( ) and propagated carry ( ). p Generated carry ( ): arry generated when A B. So, A B g Propagated carry ( ): arry is propagated when either A or B = and p in =. The in will be propagated to the out. g g Therefore, out g p in Now let s apply this equation to a ripple carry adder. 9

11 Figure.3 stage adder STAGE STAGE 3 STAGE STAGE A A3 A A out FA (MSB) in out3 FA in3 out FA in out FA in B B3 B B g p 3 A A B B g3 p3 A B A B 3 g p A A B B g p A B A B from the equation for stage : out the out for each stage is: g p in out g p in for stage out g p in and in out g p in therefore out for stage 3 out3 g g g3 p p p3 ( g g in3 p p in p ) in and in3 out g p g p p in

12 therefore ) ( in p p g p g p3 g3 out3 in p p p3 g p p3 g p3 g3 for stage in p g out and in p p p3 g p p3 g p3 g3 out3 in therefore ) ( in p p p3 g p p3 g p3 g3 p g out in p p p3 p g p p3 p g p3 p g3 p g Figure. stage carry look ahead adder FA A B in FA A B in FA A B FA A B 3

13 . BD ADDER A -bit parallel adder can be used as a -digit BD adder ( BD digit uses -bit). Keep in mind that there is an illegal BD code ( and onwards). For a BD addition, if the resulting code is larger than decimal 9, a correction process must be done. The corrections are done by adding a decimal 6. So, we need two unit of 7LS83, one for the addition and the other for the correction (adding 6). Besides that, we will also need a circuit to detect whether correction need to be done or not. Detection is done from the sum outputs of the addition I. So we have the, S, S 3, S and S as the input for our detection circuit (we will use notation S instead of because the output of the addition I is not final yet). Let s take a look at every condition that a correction need to be done:. Whenever is HIGH () ( are actually S 5 ) sum more than decimal 5 or. Whenever both is S and S 3 are HIGH () sum more than decimal or 3. Whenever S and S are both HIGH () while S 3 are LOW (). In Boolean expression (let X as output of the correction circuit, if X=, correction is needed): X S S3 S S3 S S (S3 S3 S ) S (S S ) 3 For adding the decimal 6, we will just use the X output from the correction circuit and feed it into the correcting adder input B 3 and B while the other input are grounded.

14 Figure.5 digit BD adder A A A3 A B B B3 B (5) (3) () () (6) () (5) () (7) o Vcc BD Digit BD Digit (6) S (5) Gnd S S S3 S () () (3) () (9) (3) () () (6) () (5) () (7) o Vcc (6) S S Gnd 3 () () (3) () (9) S5 S6 S7 S8 8 (not used) (8) (8) X arry forward to next digit.5 DEODER Decoder is a circuit that will detect a combination of binary code at its input and give out the one corresponding output. That means, there is only one output line that will be active (either HIGH or LOW) for every combination of binary code. For a -bit decoder (four input), there will be 6 possible combination ( n = =6; n=bit). Therefore it will have 6 output lines. Figure.6 Decoder block diagram A A O O A DEODER O An O n INPUT OUTPUT REMEMBER For an decoder, if there is n input, the circuit will have n output 3

15 Basic Binary Decoder Figure.7 show a basic -bit decoder circuit and its truth table. From the truth table, we can see that only one output is active (in this case HIGH) at all time. Figure.7 -bit Binary Decoder A B B A O B A O B A O B A O (MSB) A B O O O O3 INPUT OUTPUT A 3-bit binary decoder has three input lines and eight output line. Figure.8 shows an active-low output decoder. Notice that the NAND gate is used rather than AND to get an active-low output. Figure.8 3-bit Binary Decoder A B B A O (MSB) B O O O O3 INPUT OUTPUT B A O B A O B A O3 B A O B A O5 B A O6 B A O7 A O O5 O6 O7

16 The most common decoder is a -bit decoder. It also known as a -lineto-6-line decoder (because it has four input and 6 output) or a -of-6 decoder (because only one output for any given input combination). Figure.9 Logic symbol for a -line-to- 6-line (-of- 6) decoder BIN/DE The 7LS38: -for-8 Decoder This I is a -for-8 (or 3-line-to-8-line) decoder. It has three input line and eight active low output. For expansion purposes, it also has three EN input ( E, E and E3 ) that must all be active. Figure. I 7LS38: -for-8 decoder pin diagram (left), logic symbol (right) and internal circuitry (bottom). A A A E E E3 O7 GND LS Vcc O O O O3 O O5 O6 A A A E E E3 () () (3) () (5) (6) & (6) Vcc GND (5) () (3) () () () (9) (7) (8) A A A E E E

17 To form a -for-3 decoder, four unit of this I can be cascaded. The EN will be used to select which I will be active (remember that a decoder can only have one active output at one time) from the A3 and A input. We will also need an inverter. Figure. Four I 7LS38 cascaded to form -for-3 decoder A A3 A A A () () (3) () (5) & +5V (6) (5) () (3) () 3 () () 5 (9) 6 (7) 7 () () (3) () (5) (6) & (5) () (3) () () () (9) (7) () () (3) () (5) (6) & (5) () (3) () () () (9) (7) () () (3) () (5) (6) & (5) () (3) () () () (9) (7) The 7H5: -of-6 Decoder This is a -to-6 decoder in form of an I. It has 6 active-low outputs. It also has other input such as S ands. These two input must be both LOW to enable (EN) this I (if not, the output will always be HIGH). Figure. I 7H5: -for-6 decoder pin diagram (left) and logic symbol (right) Y Y Y Y3 Y Y5 Y6 Y7 Y8 Y9 Y GND H Vc c A A A A3 S S Y 5 Y Y 3 Y Y A A A A3 S S (3) () () () (8) (9) 8 & () Vcc GN D () () (3) () 3 (5) (6) 5 (7) 6 (8) 7 (9) 8 () 9 () (3) () (5) 3 (6) (7) 5 () 6

18 The purpose of having the two enable input is for cascading. As an example, two unit of this I can be cascaded to perform as a -for-3 decoder. Figure.3 Two unit of I 7H5 cascaded to form a -for- 3 decoder. A A A A3 A (3) () () () S S 8 & Low order () () (3) () 3 (5) (6) 5 (7) 6 (8) 7 (9) 8 () 9 () (3) () (5) 3 (6) (7) 5 (3) () () () S S 8 & High order () 6 () 7 (3) 8 () 9 (5) (6) (7) (8) 3 (9) () 5 () 6 (3) 7 8 () (5) 9 (6) 3 (7) 3 The 7H: BD-to-Decimal Decoder A BD-to-Decimal has four input lines and ten output lines. Thus, it s called line-to- line decoder or a -for- decoder. The operation is like a 7H5 (-of-6 Decoder), but only has output lines (because BD only has ten symbol). Figure. show the logic symbol of this I. Figure. I 7H : BD-to- Decimal decoder Logic symbol A A A A3 (5) () (3) () 8 (6) Vcc 7H GND () () (3) () (5) (6) (7) (9) () () (8) 7

19 The 7LS7 BD-to-7-Segment Decoder This I can be used to drive a common anode 7-segment display. Besides that, it also has additional capabilities such as: (i) (ii) (iii) LT : Use for lamp test. When connected to LOW, all of the segments are turned on. RBI : Ripple blanking input. Disable the I when LOW. BI / RBO : an be used as either input or output. Used for zero suppression. Zero suppression is to blank out the non essential zero when using several 7-segment display to display a multi digit numbers. There are two type of zero suppression: a. Leading zero suppression (figure.6): for example take number. If we are using 7-segment display (so it can display up to 9999) without leading zero suppression, the display will be (the non-essential zero didn t blank out). In short, used for whole number. b. Trailing zero suppression (figure.7): for example take number.. If we are using 7-segment display (so it can display up to.9999) without trailing zero suppression, the display will be. (the non-essential zero didn t blank out). In short, used for fractional number. Figure.5 I 7H7 : BD-to-7- segment decoder pin diagram (left) and logic symbol (right) BI LT RBO RBI D A GND B LS Vc c f g a b c d e BD INPUTS LT RBI (7) () () (6) (3) (5) 8 (6) Vcc GN D a b c d e f g () (3) () () () (9) (5) () BI RBO (8) 8

20 f f f f f f f f Figure.6 Zero leading configuration for I 7H7 RBI g (7) () () (6) (3) (5) () () BI RBO (3) a () b () c 8 d () (9) e (5) LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT Figure.7 Zero trailing configuration for I 7H7 RBI g (7) () () (6) (3) (5) () () BI RBO (3) a () b () c 8 d () (9) e (5) LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT (7) () () (6) (3) (5) () BI RBO (3) a () b () c () 8 d (9) e (5) () g RBI LT 9

21 .6 ENODER Encoder performs the reverse operation of a decoder. Instead of having a coded input like a decoder, encoder will produce a coded input depending on the input. If for decoder only one output can be active at one time, encoder only allows one active input at a time. Figure.8 Encoder block diagram A A A ENODER O O O A n O n INPUT OUTPUT Decimal-to-BD Encoder Figure.9 Decimal-to- BD encoder circuit (left) and truth table (right). A basic decimal-to-binary encoder required 9 input line (we don t need the input for decimal because all output are LOW when there is no HIGH input) and four output line REMEMBER A (LSB) A A To ensure correct operation, only one input can be active at one time. A3 Decimal BD ODE Digit A 3 A A A

22 The 7H7: Decimal-to-BD Priority Encoder. A normal encoder only can have one active input at a time. This is a problem in a case where other inputs are accidentally active. This where the advantage of the 7H7. It is also called as line-to- line priority encoder. The word priority in the I name is to describe its ability to accept more than one active input at a time, but only the highest input number are encoded. For example, if input and 8 are active, the output (because it is active LOW) will be (8 ). Figure.3 I 7H7 : Decimal-to- BD encoder pin diagram (left), logic symbol (right) and truth table (bottom) D D5 D6 D7 D 8 A A GND LS Vc c N A3 D 3 D D D 9 A () () (3) () () (3) () (5 () (6) Vcc GN D 8 (9) (7) (6) () A A A A3 BD OUTPUT (8) D D D3 D D5 D6 D7 D8 D9 A3 A A A X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

23 The 7LS8: 8-line-to-3-line Encoder This I has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes: (i) (ii) (iii) Enable input, EI (input): must be LOW for the I to function. Enable output, EO (output): LOW when EI=LOW and all input inactive. GS (output): LOW when EI=LOW and any input is active. Figure.3 I 7H8 : Decimal-to- Binary encoder pin diagram (left), logic symbol (right) and truth table (bottom) D D5 D6 D7 EI A A GND LS Vc c EO G S D 3 D D D A (5) () () () (3) () () (3) () EI (6) Vcc GN D EO GS (5) () (9) (7) (6) A A A (8) EI D D D D3 D D5 D6 D7 A A A GS EO X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Similar to other I s, two unit of this I s can be cascaded to form a 6 line-to- line decoder with some external gates.

24 Figure.3 ascading two unit of I 7H8 to form a 6 line-to- line decoder (5) () () () (3) () () (3) () (5) () () () (3) () () (3) () EI EI EO GS EO GS (5) () (9) (7) (6) (5) () (9) (7) (6) A A A A3.7 MULTIPLEXER Multiplexer (or MUX for short) is also called a data selector. We have more than one DATA input that will be selected by using the SELET to be passed through the MUX to the output line (only one output line exists). Figure.33 Multiplexer block diagram I I I I 3 MUX Z A MUX operation is similar to a Drink Vending Machine. We have a selection of drinks that will be dispense in a same compartment. I n- DATA INPUT n SELET OUTPUT 3

25 A Basic Input MUX For a four input MUX, we need -bit select input (this will give us four possible binary combination) to address which input to be selected and then passed through to the output. Figure.33 input multiplexer circuit (left) and truth table (right). I 3 I I Z S S OUTPUT Z = I Z = I Z = I Z = I 3 I S S The 7LS5: 8 line-to- line MUX/ Data selector This I has eight active high input line for data, two outputs (one is inverted), and three active high SELET inputs to address the eight data input. It also has another active low EN input for expanding purposes. Figure.3 I 7LS5 : 8 line-to- line MUX pin diagram (left) and logic symbol (right) I3 I I I Z Z EN GND LS Vcc I I5 I6 I7 S S S () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN (6) Vcc GND S S S () () (9) (5) (6) Z Z (8)

26 Using an inverter and an OR gate, two unit of this I can be cascaded to form a 6 line-to- line MUX. Figure.35 Two unit I 7LS5 cascaded to form a 6 line-to- line MUX DATA INPUT () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN S S S () () (9) (5) (SELET) S S S S3 DATA INPUT () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN S S S () () (9) (5) Z MUX for Logic Function Generation A MUX can also be configured to generate logic function. For a three input logic function (eight possible input combinations), we need an 8 line-to- line MUX. The SELET input will be the logic function input and all the MUX data input will permanently be connected to HIGH () or LOW () depending on the truth table. Figure.36 show how MUX can be used to generate logic function. 5

27 Figure.36: Using MUX to perform logic function S S S INPUT A B OUTPUT Z I (GND) I (V) I (V) I 3 (V) I (GND) I 5 (V) I 6 (GND) I 7 (V) V () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN Vcc S S S () () (9) (5) (6) B A Z Z.8 DEMULTIPLEXER A demultiplexer (DEMUX for short) perform the reverse operation of a MUX. It has one data input and several output lines. Data are channeled to one of the outputs lines depending on the SELET input. Figure.37 Demultiplexer block diagram I DEMUX O O O O 3 A DEMUX operation is like a paper sorter in a Photostat machine. Each tray will has one complete copy of the document. O n- DATA IN n SELET DATA OUTPUT 6

28 The 7ALS38: line-to- 8 line DEMUX We have seen this I in topic.5 (decoder). This I can also perform as a DEMUX. Remember that this I has three inputs (A, A and A) that can be use as SELET and the eight outputs is already similar to a DEMUX. But remember that DEMUX has one more input, that is the DATA IN. What left of the I input pins are the three EN ( E, E and E3). So, we can use either of this input for DATA IN but remember that all the output is inverted. Therefore, it s more practical for using E or E than E3 (because we need an extra inverter). Figure.38 I 7LS38: -for-8 decoder/ demultiplexer (in DEMUX configuration) DATA IN () A () A (3) A E () E (5) E3 (6) 5V & (6) Vcc GN D (5) () (3) () () () (9) (7) (8).9 OMPARATOR omparator circuit, just like its name, will compare two binary numbers. The simplest comparator will just detect equality (non equality) while a more complex circuit can also determine which binary number is larger. For bit equality/ non equality check, we can use XOR (or XNOR) gate. Figure.39: Revision on XOR operation Input is equal, output = Input is not equal, output = So, a -bit binary comparator (to detect equality only) can be build by using four XOR gate and a AND gate. 7

29 Figure.: -bit equality comparator. A3 A A A st Binary number If all the input bit are equal, Z = ; Else, Z= ' Z B3 B B B nd Binary number -bit Magnitude omparator This circuit will compare two -bit binary inputs A (A, A) with another -bit binary number B (B, B) and determine whether it is equal, and if not, which one is greater. So this circuit will have four inputs and three output. Figure.: Block diagram of a magnitude detector. A A B B OMPARATOR M =, if A=B N =, if A>B P =, if A<B *only one output can be active at a time Therefore, the truth table are: Figure.: -bit magnitude detector truth table. A B OUTPUT A A (DE) B B (DE) M N P () () () () () () () (3) () () () () () () () (3) () () () () () () () (3) (3) () (3) () (3) () (3) (3) 8

30 Using three k-map (one for each output), we will get the expression for M, N and P. M (A B) (A B) N A B A B B A A B P A B A B B A A B M N Drawing the circuit give us: Figure.3: -bit magnitude detector circuit A A B B M N P -bit Magnitude omparator ircuit. Just like an I s, unit of -bit magnitude comparator can be cascaded to perform as a -bit magnitude detector (with some external gate). Figure.3: -bit magnitude comparator circuit using two -bit magnitude comparator A3 A B3 B A A M N P M M =, if A=B N =, if A>B P =, if A<B N B P B 9

31 The 7H85:-bit Magnitude omparator. omparator is also available in I form. It has eight input line for the two sets of -bit binary number (A3, A, A, A, B3, B, B and B), and another three inputs for cascading option. Figure. I 7LS85 : -bit Magnitude omparator pin diagram (left) and logic symbol (right). A<B in A=B in A>B in B3 A<B out A=B out A>B out GND H Vc c A3 B A A B A B (5) (3) () () () (3) () () () () (9) A3 A A A A<B in A=B in A>B in B3 B B B (6) Vcc GN D A<B out A=B out A>B out (5) (6) (7) (8) For the I to function, pin 3 needs to be connected to HIGH while pin and connected to LOW. This connection is necessary for a single I operation and also for the lowest-order I in a cascaded comparator. Figure. unit of I 7LS85 cascaded to form an 8-bit Magnitude omparator +5V (5) (3) () () () (3) () () () () (9) Lower-order comparator A3 A A A A<B in A=B in A>B in B3 B B B A<B out A=B out A>B out (5) (6) (7) (5) (3) () () () (3) () () () () (9) Higher-order comparator A7 A6 A5 A A<B in A=B in A>B in B7 B6 B5 B A<B out A=B out A>B out (5) (6) (7) 3

32 . ODE ONVERTER ode converter circuit contains combinational logic gates to convert one code to another. BD-to-Binary onversion This circuit wills covert a two digit BD (from to 99) into binary value. It has eight input (each BD consist of -bit) and seven output (7-bit is sufficient to represent decimal 99). The conversion steps are: (i) Find the binary number for each of the BD digit value (remember that each digit has a different weight). Let examine a two digit BD code. Figure.5 BD tobinary conversion: Step BD NUMBERS BD ODE WEIGHT (in decimal) D 8 7 B A D B A 8 8 BINARY NUMBERS BINARY NUMBERS (ii) Add up all the binary that represent every BD digit. For this purpose, we need two unit of 7LS83 (-bit parallel binary adder) because we have eight inputs. For interconnecting these I, let take a look at the binary number (this time in table form) 3

33 Figure.5 BD tobinary conversion: Step (Truth table) INPUT BD BIT OUTPUT b 6 b 5 b b 3 b b b D B A D B A D D + B + A + D B + A + B A Figure.6 BD tobinary conversion circuit D B A D B A (5) (3) () () (6) () (5) () 3 3 A B S 3 () () (3) () (7) o (9) (5) (3) () () (6) () (5) () 3 3 A B S 3 () () (3) () (7) o b 6 b 5 b b 3 b b b (iii) The result is the BD in binary. 3

34 Binary-to-Gray ode onversion We have discussed about this in chapter. The steps are: Figure.7 Binary togray code conversion circuit (i) (ii) B B B Retain the MSB simple, just connect to gray leftmost bit. Add adjacent binary bit, discard carry use XOR gate. G G G B 3 G 3 B (MSB) G Gray code -to-binary conversion The steps are: Figure.8 Gray code to-binary conversion circuit (i) (ii) G G G Retain the leftmost bit. Add the converted gray bit to the adjacent binary bit, discard carry. B B B G 3 B 3 G B (MSB) 33

35 . PARITY BIT GENERATOR & HEKER Parity bits are determined by the numbers of s in the code (data string) by summing up all the bits (discarding carry). If the result are: the number of s are even the number of s are odd The summing can be done by using XOR gate. Then it can be generated (depending on system used, whether even or odd parity system) and transmitted along with the data. Figure.9 Even parity generator A 6 A 5 A A 3 A A A 6 A 5 A A 3 A A Even parity Even parity generator Transmitted Data Figure.9 Odd parity generator A 6 A 5 A A 3 A A A 6 A 5 A A 3 A A Odd parity Odd parity generator Transmitted Data To check the parity bit with the data (this is at the receiver), calculate back the parity bit (same circuit as parity generator) and then whether the result is the same with the parity bit received (done by using XNOR) 3

36 Figure.9 Even parity checker A 6 A 5 A A 3 A A Even parity A 6 A 5 A A 3 A A Received Data Even parity checker =error Figure.9 Even parity checker A 6 A 5 A A 3 A A Even parity A 6 A 5 A A 3 A A Received Data Odd parity checker =error 35

37 TUTORIAL OBJETIVE UESTION. Which of the following input and output value are incorrect for the -bit parallel binary adder/subtractor circuit in figure above? [A] [B] Adder/Subtractor out [] (a) (b) (c ) (d). In general, a multiplexer has (a) one data input, several data outputs and selection inputs (b) several data input, several data output and selection inputs (c) one data input, one data output and one selection input (d) several data input, one data output and selection inputs 36

38 3. Table 3 is a truth table for a -to- line decoder priority encoder. Which of the inputs and outputs combination is correct? Table 3 Inputs Outputs En A A D D D D3 (a) x x (b) (c) (d). Table is a truth table for a priority encoder. Which of the inputs and outputs combination is incorrect? Table Inputs Outputs D3 D D D A A Y (a) x x (b) (c) x (d) x x x 5. A is a combinational circuit element that selects data from one of many inputs and directs it to a single output. (a) encoder (b) multiplexer (c) decoder (d) demultiplexer 37

39 6. What is the combinational logic circuit in Figure represent? (a) 3-to-8 decoder (b) 3-to-8 encoder (c) BD-to-7 segment decoder (d) 8-to-3 encoder 7. If all the inputs are applied simultaneously to the ripple adder shown in Figure 3, how long does it take before the SUM and become valid? Assume that the delay of each gate (within each adder stage) is t p. (a) t p. (b) t p. (c) 3 t p. (d) 5 t p. 38

40 Figure 8 8. The full-adder in Figure 8 is tested under all input conditions with the input waveforms shown. From your observation of the SUM and OUT waveforms, is it operating properly, and if not, what is the most likely fault? (a) Yes, the output SUM and OUT are correct. (b) No, the input IN is accidentally connected to V. (c) No, the input B is accidentally connected to V. (d) No, the input A is accidentally connected to V. 9 The following data input has been applied to the multiplexer in Figure 9a) : D, D, D and D 3. The data-select inputs to the multiplexer are sequenced as shown by the waveforms in Figure 9(b), determine the output waveform. (a) (b) (c) (d) 39

41 . To expand a bit parallel adder to an 8 bit parallel adder you must (a) use bit adders with no connections (b) use two bit adders and connect to the sum outputs of one to the bit output of the other (c) use eight bit adders with no interconnections (d) use two bit adders with the carry output of one connected to the carry input of the other. If a 7LS85 magnitude comparator has A = and B = on the inputs, the outputs are: (a) A>B =, A<B =, A = B = (b) A>B =, A< B =, A=B= (c) A>B =, A<B =, A=B= (d) A>B=, A< B=, A=B=. A BD to 7 segment decoder has on the inputs. The active output segments are: (a) a,c,f,g (b) b,c,e,f (c) b,c,f,g (d) b,d,e,g 3. Data selectors are basically the same as: (a) decoders (b) multiplexers (c) demultiplexers (d) encoder

42 SUBJETIVE UESTION. The 7LS8 : 8-to-3 encoder This I has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes: i) Enable input, EI (input) : must be LOW for the I to function. ii) Enable output EO (output) : LOW when EI = LOW and all inputs are inactive. iii) GS (output) : LOW when EI = LOW and any input is active. Show how two units of 7LS8 can be used as a 6-to- encoder. Please state the pin number representing the D5 input (i.e. the most significant bit).. Design a circuit that behaves as a 3-to-8 decoder. Use only two types of logic gates, i.e. NOT gates and AND gates. 3. Using a 3:8 decoder in Figure 3, implement the following logic function: F(A,B,) = A B AB Figure 3. Match the names with the circuit diagram in Figure, leave blank if diagram isn t there. (e) RS Latch (f) JK Flip Flop (g) Decoder (h) Gated D Latch : : : : (a) Master-Slave flip flop (b) -bit Multiplexer (c) Full Adder (d) -bit register : : : :

43 B A D F J E d 3 d d d D SET D SET D SET D SET Out LR LR LR LR Load lk In D SET d 3 D SET d D SET d D SET d LR LR LR LR lk I H G Figure 5. A full adder can be implemented in many different ways. One of the method is by combining two half adders. Beginning with the truth table, design the circuit that function as a half adder, with the least number of gates. Then, design a full-adder circuit using the two half-adders.

44 6. The logic diagram, truth table and logic symbol for an eight input multiplexer (75) are given in Figure 6. By using this eight input multiplexer, design a circuit that will perform a 6 bit parallel to serial conversion. Sketch the output waveform if the input to the multiplexer is. Figure 6 7. onsider a -bit parallel adder as shown in Figure 7. It is necessary to build a look ahead carry circuit which generates the carry 3 to be fed to the full-adder of the most significant bit position. Derive 3 in terms of, A, B, A, B, A and B. B 3 B B B A 3 A A A 3 Penambah penuh/ Full Adder Penambah penuh/ Full Adder Penambah penuh/ Full Adder Penambah penuh/ Full Adder S3 S S S Figure 7 3

45 8. Figure 8 shows the logic symbol of the integrated circuit 75: 3 line-to-8 line multiplexer. Show in the given figure how this I can be connected to perform the following logic expression. Label completely and include this sheet in your answer script. Z A B (6) () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN Vcc GND S S S () () (9) (5) (6) Z Z (8) 9. Prove (using Boolean theorem) that the circuit in figure 9 is equivalent to a full-adder. A A HA HA SUM B in Figure 9 o. For the circuit in figure, determine the output if the input are: A A3 A A 3 FA (MSB) FA FA FA in B B3 B B S3 S S S a. [A] = and [B] = b. [A] = and [B] = c. [A] = and [B] = Figure

46 . For the circuit in figure, determine the input [A] if the output and input [B] are: a. [B] = and [Σ] = b. [B] = and [Σ] = c. [B] = and [Σ] =. By using circuit in figure, determine and fill in the empty field in table with the correct answer (all numbers are unsigned) o -bit binary number A A -BIT PARALLEL BINARY ADDER A3 A A Adder/Subtractor ontrol 3 -bit binary SUM Figure B B B3 B -bit binary number B BINARY NUMBER (A) BINARY NUMBER (B) SUM (S) SUB A A3 A A DE B B3 B B DE S S3 S S DE By using circuit in figure, determine and fill in the empty field in table with the correct answer (all numbers are -bit signed). omment on the result. BINARY NUMBER (A) BINARY NUMBER (B) SUM (S) SUB A A3 A A DE B B3 B B DE S S3 S S DE

47 . Draw the complete connection for the two I s (783) in figure to operate as an 8-bit adder. Label all the inputs and outputs completely. Vcc Vcc () (8) (3) () () (7) () (6) (3) 3 3 o A B (5) () (8) (9) (6) 3 () (5) () (3) () () (7) () (6) (3) 3 3 o A B (5) 3 (9) (6) () (5) () Gnd () Gnd () Figure 5 For the circuit you build in figure, determine the output if the input are: a. [A] =and [B] = b. [A] = and [B] = c. [A] = and [B] = 6. Design a -bit carry look-ahead adder. Start by deriving the Boolean equation for out and the draw the complete circuit. What are the advantages and disadvantages of this circuit compared with ripple carry adder? 7. What are the output of the decoder in figure 7 if the inputs are: (6) A A A E E E3 () () (3) () (5) (6) & Vcc GND (5) () (3) () () () (9) (7) a. A=,A=,A=, E =, E = and E3 = b. A=,A=,A=, E =, E = and E3 = c. A=,A=,A=, E =, E = and E3 = d. A=,A=,A=, E =, E = and E3 = (8) Figure 7 8. Show how units of Is in figure 7 can be connected to perform as a 5 line-to-3 line decoder. 6

48 9. What are the differences between a binary to BD decoder with a line-to-6 line decoder?. Explain the trailing zero suppression and leading zero suppression configuration. When these two configurations are used?. What are the advantages of using a priority encoder compared to a normal encoder?. Fill in the truth table for encoder in figure. D 6 Vcc D D D3 D D5 D6 D7 D8 D9 A3 A A A D5 D6 D7 D8 A A LS Figure N A3 D3 D D D9 A X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 3. Explain the characteristic of pin labeled EI, EO and GS in I 78. Shows how two units of these Is can be cascaded to perform as 6 line-to- line encoder.. Show how unit of 7LS5 (MUX) can be cascaded to perform as a 3 line-to- line MUX. 5. Show how 7LS5 (MUX) can be used to implement this logic circuit. Z A B D 6. Explain why in using 738 Is as a DEMUX, Data In is connected to the ATIVE-LOW enabled input instead of the ATIVE-HIGH enable input? 7. Design a -bit magnitude relative detector that takes two -bit binary numbers; x x and y y, and determines whether they are equal and if not, which one is larger. There are three outputs, defined as follows: M= only if the two input numbers are equal N= only if x x is greater than y y P= only if y y is greater than x x Start from truth table, then used Boolean theorem and/or karnaugh map to get the simplified Boolean expression before drawing the circuit. 7

49 8. Show (in detail) how the circuit you design in question 7 can be used as a -bit magnitude relative detector starting from the truth table. 9. Explain the design of BD to binary code converter using your own understanding. Figure (a) show the logic symbol of 7LS38, -to-8 decoder. Waveform A, A, A and E shown in Figure (b) are applied to this decoder. Assume that E and E3 are tied to LOW (). Draw the waveform for outputs O, O 3, O 6 and O 7 A A A A E E E3 () () (3) () (5) (6) & (5) () (3) () 3 () () 5 (9) 6 (7) 7 A A E O O 3 O 6 O 7 3. Given the circuit diagram of Figure 3(a), complete the timing diagram of Figure 3(b) for A, B and. 8

50 3. Show how 7LS5 (MUX) below can be used to perform the following Boolean expression. Y (A B ) (A B ) (A B ) (A B ) 3. A decoder I 7LS38 (3-to-8 decoder) shown in Figure 3(d) can be used to implement combinational logic function. i) Implement GENAP circuit using this I. GENAP circuit has four-bit binary inputs A (A 3 A A A ). It has one output Z that will be HIGH () when A is an even numbers. Show all steps. ii) What are the modifications necessary so that this circuit will produce a HIGH () output when the input is odd numbers? 33. Show how a -bit parallel ripple carry adder (shown below) can be use to add three -bit binary numbers X, Y and Z, and produce - bit output, SUM and ARRY. Label the circuit accordingly. () (8) (3) () () (7) () (6) 3 3 A B S 3 (9) (6) () (5) (3) o () 9

51 3. The 7LS8 is a 8 line-to-3 line encoder. This I has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes: Enable input, EI (input): must be LOW for the I to function. Enable output, EO (output): LOW when EI=LOW and all input inactive. GS (output): LOW when EI=LOW and any input is active. omplete the following truth table for this I. EI D D D D3 D D5 D6 D7 A A A GS EO 35. Show how a 3 line-to-8 line decoder (shown below) can be use to implement the following function. Label the circuit accordingly. Z A B A B B E E E3 () () (3) () (5) (6) & (5) () (3) () 3 () () 5 (9) 6 (7) Show how a 8 line-to- line multiplexer (shown below) can be use to implement the following function. Label the circuit accordingly. Z (A B ) (A B ) (A B ) (A B ) () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN S S S () () (9) (5) (6) Z Z 5

52 37. Figure below shows the logic symbol of a -bit relative magnitude detector. Show how two unit of this circuit can be cascaded along with other logic gates to compare a 3-bit binary numbers X X X and Y Y Y. A A B B OMPARATOR M =, if A=B N =, if A>B P =, if A<B *only one output can be active at a time 38. Figure (a) show the logic symbol of 7LS38, -to-8 decoder. Waveform A, A, A and E3 shown in Figure (b) are applied to this decoder. Assume that E and E are tied to LOW (). Draw the waveform for outputs O, O 3, O 6 and O 7 A A A A E E E3 () () (3) () (5) (6) & (5) () (3) () 3 () () 5 (9) 6 (7) 7 A A E 3 O O 3 O 6 O 7 5

53 39. Figure 3 show the logic symbol of 7LS5, 8-to- line multiplexer. Show how it can be used to generate function Z A B (A ). Label completely. () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN S S S () () (9) (5) (6) Z Z. Show how one () unit of I7LS5 can be use to implement the following function. Z B A D A D 5

54 SUBJET: ELETRIAL ENGINEERING LABORATORY BEE 9 DIGITAL ELETRONIS EXPERIMENT 6: Building a Full-adder Logic ircuit () A A FA FA SUM B in Figure o PRELAB TASK. By using Boolean theorem, show that a full-adder can be implemented by using two half-adder shown in Figure. LAB TASK. onstruct half adder circuit.. By using the two half adder you constructed, build the circuit in Figure on the protoboard. 3. onnect the inputs (A, B and in ) to the data switch and output (SUM and o ) to the LED. Make sure every I is connected to +5V and ground properly.. Build a truth table based on the output of this circuit by using all the possible input combination. EXPERIMENT 7: Building a Full-adder Logic ircuit () A in FA SUM o B Figure 3 PRELAB TASK. Build truth table for a full-adder with input A, B and in, and output SUM and o. This will be the theoretical output.. Obtain the simplest Boolean expression for SUM and o. Draw your circuit. 3. Re-draw your circuit complete with I and pin numbers (refer datasheet for the I pin assignment). 53

55 LAB TASK. onstruct the circuit on the protoboard.. onnect the inputs (A, B and in ) to the data switch and output (SUM and o ) to the LED. Make sure every I is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination and verify that the results are similar with the theoretical full-adder truth table.. Both circuit in experiment 6 and experiment 7 can perform as a full adder. In your opinion, which design is better? Justify your answer. EXPERIMENT 8: Using a 3 line-to-8 line Decoder as a Full Adder (6) +5V A B in () () (3) () (5) (6) SELET Vcc 738 & GND (5) () (3) () () () (9) (7) S out (8) Figure PRELAB TASK. By using any method you prefer, prove that a decoder with connection shown in figure can be used as a full adder. Hint: refer to the decoder datasheet. LAB TASK. onstruct this circuit on the protoboard.. onnect the inputs (A, B, and in ) to the data switch and output (SUM and out ) to the LED. Make sure every I is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination.. Verify that the result correct. 5. In your opinion, what is the advantages of this circuit compared with the full adder circuit you built in experiment? 5

56 EXPERIMENT 9: Using a Multiplexer for Implement Logic Function () (3) () () (5) () (3) () (7) I I I I3 I I5 I6 I7 EN Vcc 75 S S S () () (9) (5) (6) B A Z Figure PRELAB TASK. By using any method you prefer, prove that a multiplexer with connection shown in figure can be used to implement logic function below. Z A B LAB TASK. onstruct this circuit on the protoboard.. onnect the inputs (A, B, and ) to the data switch and output (Z) to the LED. Make sure every I is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination.. Verify that the result correct. 5. What necessary changes must be made if the circuit is now needed to implement the following function? Z A B EXPERIMENT : Building a -digit BD Adder BD number A o -BIT PARALLEL BINARY ADDER arry to next BD digit Illegal ode hecker BD number B orrection ircuit Result in valid BD Figure : Block Diagram of a BD Adder 55

57 PRELAB TASK. In your own words, explain how the circuit operates based on Figure.5 (refer to teaching module).. Figure.5 shows a BD adder circuit using 7LS83. This lab only has 7LS83. Modify this circuit so it can be implemented using 7LS83. Refer to datasheet or teaching module for the pin assignment. LAB TASK. onstruct the circuit on the protoboard. TIPS: you are advised to do this block by block. Start with adder block, and then add the checker and lastly the correction. You are encouraged to check each block output first before proceeding with adding another block.. onnect the inputs to the data switch and output to the LED. Make sure every I is connected to +5V and ground properly. 3. Verify that the circuit is functioning correctly by performing five (5) BD addition operations.. Based on this experiment, what are the disadvantages of using BD code in a digital circuit compared with binary? 56

58 HAPTER 5 LATH & FLIP-FLOP OUTLINE NAND LATH NOR LATH D LATH EDGE TRIGGERED S FLIP-FLOP EDGE TRIGGERED JK FLIP-FLOP EDGE TRIGGERED D FLIP-FLOP FLIP-FLOP HARATERISTI FLIP-FLOP APPLITION 57

59 Up until this chapter, we ve been only discussing about logic circuit without any memory element. Without memory element, the logic circuit cannot remember the previous output state and because of this, the output will change (or re-evaluate) every time input changes. A logic circuit with memory element (temporary), are capable of storing (holding) it previous output level until the opposite input received. A logic gate itself is a non-memory element, but by interconnecting (and feedback) several gate, it can perform as memory circuit. Memory element device are a bistable multivibrator type device because it has two stable states, SET and RESET. Example of this kind of device is latch and flip-flops (FF). The difference between these two is the way they change their output (we will look at this later). 5. NAND LATH A NAND latch is build from two NAND gate interconnected with the other. It has two input, SET(S) and LEAR(), and two output and (the inverted ) Figure 5. NAND latch S REMEMBER LEAR () and RESET (R) can be use interchangeably. Now let s analyze this circuit. There are two inputs, so we have four possible input combinations. Notice that the outputs are feed back into the gate. Therefore we need to assume the initial value of for every possible input combination. That gives us a total of eight possible conditions. ase : S=; =; = Figure 5. NAND latch: ase S S Before After As we can see in figure 5., the output (after) is the same with (before). 58

60 ase : S=; =; = Figure 5.3 NAND latch: ase S S Before After As we can see in figure 5.3, the output (after) is the same with (before). ase 3: S=; =; = Figure 5. NAND latch: ase 3 S S Before After As we can see in figure 5., the output (after) is the same with (before). ase : S=; =; = Figure 5.5 NAND latch: ase S S S Before After As we can see in figure 5.5, the output (after) changes from to. 59

61 ase 5: S=; =; = Figure 5.6 NAND latch: ase 5 S S S Before After As we can see in figure 5.6, the output (after) changes from to. ase 6: S=; =; = Figure 5.7 NAND latch: ase 6 S S Before After As we can see in figure 5.7, the output (after) is the same with (before). ase 7: S=; =; = Figure 5.8 NAND latch: ase 7 S S S Before After As we can see in figure 5.8, the output (after) changes from to but =. This output is not valid because the two outputs supposed to be the invert of each other. 6

62 ase 8: S=; =; = Figure 5.9 NAND latch: ase 8 S S Before After As we can see in figure 5.9, the output (after) is the same but =. This output is not valid because the two outputs supposed to be the invert of each other. As a result, a complete analysis are summarize in table 5. Figure 5. Summarize analysis result of the NAND latch Figure 5. NAND latch truth table Input Before After S invalid invalid : : : : : : To summarize the result, Input S OUTPUT invalid SET LEAR HOLD IGNORE SET LEAR HOLD From truth table in figure 5., it s clear that NAND latch uses active LOW input for S (to SET) and (to clear). Therefore, the input S== should not be used because we are trying to SET and RESET at the same time. The logic symbol for this circuit are shown n figure 5. (notice the bubble at the input to indicates active LOW). 6

63 Figure 5. NAND latch S FF We also have learned in chapter 3 that NAND gate can be represented by a negative-or (OR with bubble at both inputs) and this is shown in figure 5.3. Figure 5.3 NAND latch (alternate form) S Example 5. The waveforms in figure 5. are applied to a NAND latch. Assume that initially =, determine the waveform. Figure 5. Waveform for example 5. S SET HOLD LEAR HOLD SET HOLD LEAR HOLD One of the NAND latch common application is for de-bouncing circuit. In a mechanical switch, it s almost impossible to obtain a clean transition. This phenomenon is known as contact bounce. 6

64 Figure 5.5 Switching bounce (top) and debouncing using NAND latch. +5V +5V Vout +5V V Bouncing Switch to position Switch comes to rest in position S FF Vout +5V V +5V Switch to position 5. NOR LATH Just like a NAND latch, a NOR latch is build from two NOR gate interconnected with the other. It has two inputs, SET(S) and LEAR(), and two output and (the inverted ). Figure 5.6 NOR latch S REMEMBER Note that the output and are at the opposite pin (compared to NAND latch) Now let s analyze this circuit. There are two inputs, so we have four possible input combinations. Notice that the outputs are feed back into the gate. Therefore we need to assume the initial value of for every possible input combination. That gives us a total of eight possible conditions. ase : S=; =; = Figure 5.7 NOR latch: ase S S Before After As we can see in figure 5.7, this input combination is invalid because the output is the same with. ase : S=; =; = 63

65 Figure 5.8 NOR latch: ase S S S Before After As we can see in figure 5.8, this input combination is invalid because the output is the same with. ase 3: S=; =; = Figure 5.9 NOR latch: ase 3 S S S Before After As we can see in figure 5.9, the output changes from to ase : S=; =; = Figure 5. NOR latch: ase S S Before After As we can see in figure 5., the output remains as. ase 5: S=; =; = 6

66 Figure 5. NOR latch: ase 5 S S Before After As we can see in figure 5., the output remains. ase 6: S=; =; = Figure 5. NOR latch: ase 6 S S S Before After As we can see in figure 5., the output changes from to. ase 7: S=; =; = Figure 5.3 NOR latch: ase 7 S S Before After As we can see in figure 5.3, the output remains the same. ase 8: S=; =; = Figure 5. NAND latch: ase 6 S S Before After As we can see in figure 5., the output remains the same. As a result, a complete analysis are summarize in figure

67 Figure 5.5 Summarize analysis result of the NOR latch Figure 5.6 NOR latch truth table Input Before After S : : : : : : invalid invalid To summarize the result, Input S OUTPUT HOLD LEAR SET invalid HOLD SET LEAR IGNORE From truth table in figure 5.6, it s clear that NOR latch uses active HIGH input for S (to SET) and (to clear). Therefore, the input S== should not be used because we are trying to SET and RESET at the same time. The logic symbol for this circuit are shown n figure 5.7. Figure 5.7 NOR latch S FF We also have learned in chapter 3 that NOR gate can be represented by a negative-and (ANDR with bubble at both inputs) and this is shown in figure 5.8. Figure 5.8 NOR latch (alternate form) S Example 5. The waveforms in figure 5.9 are applied to a NOR latch. Assume that 66

68 initially =, determine the waveform. Figure 5.9 Waveform for example 5. S SET HOLD LEAR HOLD SET HOLD LEAR HOLD An example application for a NOR latch is for a door alarm system shown in figure 5.3. The door is connected to a switch that connects the S input to the ground. When the door is open, the connection to ground are open, and the S input are pulled-up to V cc (). Thus, triggering the alarm. Alarm will continue to sound even when the door is closed again, until the reset switch is pressed (assuming the door is already closed). Figure 5.3 NOR latch in an alarm system +5V +5V S Will open when door is open 5.3 D LATH A D latch are also called a transparent latch because its ability to copy the D input to its output. It has two input, D and EN (enable), and two output, and. Figure 5.3 D latch D EN The D latch will copy the input D waveform when the EN input is HIGH 67

69 () and will hold the present value when EN is LOW (). Figure 5.3 D latch truth table Input OUTPUT D EN X Example 5.3 Determine the output of a D latch when waveform D and EN shown in figure 5.33 are applied. (Assume that initially =). Figure 5.33 Waveform for example 5.3 D EN =D (tranparent) HOLD (no change) =D (tranparent) 5. EDGE TRIGGERED S FLIP-FLOP (S FF) The main difference between this and a latch is that the output level can only be change during the transition of the clock input. This transition may either be the positive-going-transition (PGT) or the negative-goingtransition (NGT) but not both. Figure 5.3 The PGT and NGT of clock signal. LOK PGT NGT Therefore a S FF has three input, SET (S), LEAR () and LOK (LK) and two output, and. 68

70 Figure 5.35 S FF internal circuitry, PGT S-FF symbol (bottom left) and NGT S- FF (bottom right) S LK LK S Edge detector circuit S LK The truth table for an S-FF is shown in figure It can be seen that an edge triggered S FF operate just like a NOR latch, but the transition only happens at clock transition. Figure 5.36 S FF (PGT) truth table. INPUT OUTPUT S LK HOLD LEAR SET INVALID Let us examine when the same input waveform in figure 5.9 are applied to an edge triggered S FF. Figure 5.35 S FF (NGT) waveform. S LK SET LEAR HOLD SET HOLD HOLD (NOR LATH) 69

71 Figure 5.36 S FF (PGT) waveform. S LK HOLD HOLD HOLD SET HOLD LEAR (NOR LATH) It can be seen that the output level transition appear to be delayed (because it can only change at clock transition). Method for edge triggering The simplest method of edge triggering is by using a NOT gate and a AND gate. Remember that in practice, all gates will introduce a delay to the output. This principle is used in this edge triggering circuit. Figure 5.37 PGT edge detection circuit (left) and NGT edge detection circuit (right). clock Delayed due to inverter Edge detection circuit (PGT) a b c a b c Spike produced clock Delayed due to inverter Edge detection circuit (NGT) a b c a b c Spike produced 7

72 5.5 EDGE TRIGGERED JK FLIP-FLOP (JK FF) One of the shortcomings of an edge-triggered S FF is the existence invalid input combination. This can be overcome by using an edgetriggered JK FF. Figure 5.38 JK FF internal circuitry, PGT JK-FF symbol (bottom left) and NGT JK- FF (bottom right) LK J Edge detector circuit K J J LK LK K K When inputs of JK FF are both high when it is triggered, it will invert the previous output state (). This condition is called toggle. Figure 5.39 JK FF (PGT) truth table. INPUT OUTPUT S LK HOLD LEAR SET TOGGLE Let us examine when input waveform in figure 5. are applied to an edge triggered JK FF. Figure 5. JK FF (NGT) waveform. J K LK SET LEAR HOLD TOGGLE TOGGLE LEAR 7

73 Figure 5. JK FF (PGT) waveform. J K LK HOLD SET LEAR SET TOGGLE LEAR Asynchronous Preset and lear Input. For any edge-triggered FF, the inputs (besides the clock) are called synchronous input. This is because the output can only change state when a clock transition occurs. Most FF in I form also has a asynchronous input labeled preset (PRE) and clear (LR) that can affect the state of the FF regardless of the clock. These two inputs are both active-low (indicated by bubbles). Low input at PRE will set the FF output to HIGH () and low input at LR will reset the FF output to LOW (). Figure 5. JK FF (with asynchronous input) internal circuitry, PGT JK-FF symbol (bottom left) and NGT JK- FF (bottom right) LK J Edge detector circuit K PRE PRE LR PRE J J LK LK K K LR LR When a asynchronous input are applied, it will immediately affect the state of the output regardless of the clock signal. While a asynchronous input is active, the FF will ignore all the other synchronous inputs until it become un-active again. In other word, asynchronous inputs have higher priority than synchronous input. 7

74 Figure 5.3 JK FF (PGT) with asynchronous inputs waveform. LK J K PRE LR PRE PRE LR HOLD TOGGLE TOGGLE HOLD SET TOGGLE HOLD HOLD SET TOGGLE TOGGLE The 7: Dual J-K Flip-Flop with Preset and lear. Figure 5. Dual J-K Flip- Flop with Preset and lear pin diagram (left) and logic symbol (right) LK K PRE J Vcc LR LR LK () (3) () () (5) Vcc (6) PRE J K LR (5) (6) 5 K () 6 7 GND 8 9 J PRE () (3) () () J K PRE LR (9) (7) (8) Gnd 73

75 5.6 EDGE TRIGGERED D FLIP-FLOP (D FF) An edge triggered D FF only has one input, D (D=data) and clock for edge triggering. When triggered, value of D will be transferred to output (). This is useful for synchronizing especially in storing data (we can control when data are to be stored). Figure 5.5 Edge triggered D-FF (PGT) truth table OUTPUT S LK An edge triggered J-K FF or an edge triggered S FF can be used to perform as D FF as shown in figure 5.5. Figure 5.6 Edge triggered D-FF (PGT) D LK D LK S D LK J K Waveform D and D in figure 5.7 are applied to two different PGT edge triggering D FF. Assuming initially =, sketch and. Figure 5.7 Edge triggered D FF waveform response LK D D From figure 5.7, it can be seen that data that pass through a D FF a resynchronize by the clock input. This is important in data transmission where data pulses are delayed, (or stretch) need to be re-synchronized. The limitation is that the stretch pulse must not exceed one clock pulse. 7

76 5.7 FLIP-FLOP HARATERISTIS Every FF has different characteristic depending on the type and technology. These characteristic are stated in the device datasheet. Propagation delay This is the time interval between the time when input are applied to the time when output changes. It can be categorized into four types:. t PLH : time measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.. t PHL : time measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output. Figure 5.8 Propagation delay: t PLH (left) and t PHL (right) LK 5% of triggering edge LK 5% of triggering edge 5% of the HIGH to LOW transition of 5% of the LOW to HIGH transition of t PLH t PHL 3. t PLH : time measured from the leading edge of the PRESET input to the LOW-to-HIGH transition of the output.. t PHL : time measured from the leading edge of the RESET input to the HIGH-to-LOW transition of the output. Figure 5.9 Propagation delay: t PLH for PRESET (left) and t PHL for RESET (right) PRE 5% of the leading edge t PLH 5% of the LOW to HIGH transition of LR 5% of leading edge t PHL 5% of the HIGH to LOW transition of Pulse Widths Minimum pulse width for the inputs and clock. Typically the clock is specified by the minimum HIGH time and its minimum LOW time. 75

77 Set-up Time (t s ) Minimum time for the input to be at a constant level (ready) before the triggering occurs. Figure 5.5 Set-up time: t S for HIGH input (left) and t S for LOW input (right) D LK 5% of the LOW to HIGH transition of D 5% of triggering edge D LK 5% of the HIGH to LOW transition of D 5% of triggering edge Set-up time (t s ) Set-up time (t s ) Hold Time (t h ) Minimum time needed for an input signal to remain at constant level (hold) after the triggering edge before it can change it states. Figure 5.5 Hold time D 5% of the HIGH to LOW transition of D LK 5% of triggering edge Hold time (t h ) Maximum lock Frequency (f max ) Maximum frequency for the clock to ensure a reliable FF operation. Power Dissipation (P) The power consumption for device. alculated by using the formula below: When building a circuit, P V I make sure the power supply is capable to deliver enough power. For a circuit that uses ten FF with each dissipated mw, the total power needed are.w (mw X ). If each FF operates on +5V (dc), the amount of current needed are ma. 76

78 5.8 FLIP-FLOP APPLIATION We have look at several type of flip-flop. Now we will take a look at its application. A single FF cannot do much, but when several FF are connected together and with some other logic gates, it can be used for many applications. Frequency Divider A frequency divider circuit will divide the clock with for every stage. A JK FF with its J and K input connected to HIGH (so it will always in toggle mode) is required for each stage. Figure 5.5 shows a stage frequency divider. Figure 5.5 A stage frequency divider and waveform (bottom) LK J K J J J K K K A B D LK A B D It can be seen from the waveform for each stage, the frequency are halves. If the clock frequency are Hz: A =/=5Hz B =/=.5Hz =/8=.5Hz D =/6=.65Hz 77

79 Asynchronous ounter A counter function is to count (in binary) from decimal to decimal number N- (where N is the MOD of the counter). Asynchronous don t have a common clock signal and because of output from one FF are feed into another FF, the signal is called rippled. Thus, asynchronous counter are also called ripple counter. Figure 5.53 shows a MOD-6 counter. Figure 5.53 MOD -6 counter and waveform (bottom) LK J J J J K K K K A B D LK A B D (MSB) DE From figure 5.53, it can be seen that a MOD-6 counter counts from ( ) till (5 ). It also consists of JK FF (because counting to (5 ) require at least -bit with all the J and K input connected to HIGH (JK FF always in toggle mode). The rule for determining the minimum number of JK FF required is: MODnumber n (where n number of JK FF) Therefore a MOD-8 will required three JK FF while a MOD-3 will required five JK FF. We will look more on counter in the next chapter. 78

80 ONE-SHOT A one-shot device (a.k.a. monostable multivibrator) has only one stable state. It will always be in it stable state and when triggered, move to its unstable state and remains for a determine time before returning to its stable state. The time its stays in the unstable state determine the pulse width. Figure 5.5 Basic One- Shot Device Trigger +5V A basic one-shot device consists of logic gates and inverter (shown in figure 5.5). This device stable state is =LOW (). When triggered:. Output of NOR will become LOW (). Output of INVERTER will become HIGH (), =HIGH () 3. Because = HIGH (), output of NOR will stay LOW (), although triggering has stop.. apacitor will be charge until certain level before the INVERTER will interpret it as HIGH () and the output becomes LOW (), = LOW () and NOR output become HIGH (). It will stay low until another triggering occurs. The time for the device to stays in its unstable state are determine by the capacitor and resistor value (R time constant). 79

81 SUBJET: EXPERIMENT : ELETRIAL ENGINEERING LABORATORY BEE 9 DIGITAL ELETRONIS NAND LATH PRELAB TASK LAB TASK. Draw a NAND latch circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit.. onstruct the circuit on the protoboard.. onnect the inputs (SET and RESET) to the data switch and two outputs to the LED. Make sure every I is connected to +5V and ground properly. 3. Verify that the latch operates correctly.. Write a short comment on the illegal input condition. EXPERIMENT : NOR LATH PRELAB TASK LAB TASK. Draw a NOR latch circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit.. onstruct circuit on the protoboard.. onnect the inputs (SET and RESET) to the data switch and two outputs to the LED. Make sure every I is connected to +5V and ground properly. 3. Verify that the latch is operating correctly.. Write a short comment on the illegal input condition. EXPERIMENT 3: D LATH PRELAB TASK LAB TASK. Draw a D latch circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit 3.. onstruct circuit 3 on the protoboard.. onnect the inputs (D and EN) to the data switch and two outputs to the LED. Make sure every I is connected to +5V and ground properly. 3. Verify that the latch is operating correctly.. omment on what happen during the transparent states. 8

82 EXPERIMENT : EDGE TRIGGERED S FLIP FLOP PRELAB TASK LAB TASK. Draw a S Flip-flop circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit.. onstruct circuit on the protoboard.. onnect the inputs (S and ) to the data switch and LK input to pulse generator and two outputs to the LED. Make sure every I is connected to +5V and ground properly. 3. Verify that the circuit is functioning correctly.. Write a short discussion on the difference in term of output transition of this circuit compared to NOR latch. EXPERIMENT 5: EDGE TRIGGERED JK FLIP FLOP PRELAB TASK. Study the operation of I7LS76 (refer to datasheet).. In your own words, write a short explanation about the asynchronous input of this I (the PRE and LR input). LAB TASK. onstruct the circuit on the protoboard.. onnect the inputs (J, K, PRE and LR ) to the data switch, and LK input to pulse generator and two outputs to the LED. 3. Make sure every I is connected to +5V and ground properly.. Write a short discussion on the advantages of using JK flip-flop compared with S flip-flop. EXPERIMENT 6: D LATH PRELAB TASK LAB TASK. Show (in drawings) how a JK flip-flop can be modified to operate as D flip-flop.. Re-draw this circuit complete with I and pin numbers (refer datasheet for the I pin assignment).. onnect the inputs, D the data switch, and LK input to pulse generator and two outputs to the LED.. Make sure every I is connected to +5V and ground properly. 3. Verify that the I s is functioning correctly.. Write a short discussion on the difference between D latch and D flip-flop. 8

83 HAPTER 6 OUNTER AND REGISTER OUTLINE ASYNHRONOUS OUNTER SYNHRONOUS OUNTER STATE MAHINE SERIAL IN / SERIAL OUT SHIFT REGISTER SERIAL IN / PARALLEL OUT SHIFT REGISTER PARALLEL IN / SERIAL OUT SHIFT REGISTER PARALLEL IN / PARALLEL OUT SHIFT REGISTER 8

84 In chapter 5, we have discussed about the basic of counter. In this chapter, we will go into the detail of counter, the types and I available. 6. ASYNHRONOUS OUNTER In the previous chapter, the counters we ve been discussing are only in block diagram level. Now we are going to design and build a counter using an I. Design and Implementation of MOD-8 ounter using 7 For a MOD-8 counter, three JK FF are required. The block diagram and expected waveform are shown in figure 6. Figure 6. MOD-8 ounter J J J REMEMBER LK K K K J=K= for toggle operation A B LK A B (MSB) DE Therefore, the implementation using 7 will require two unit of this I (because we need three JK FF while 7 only contain JK FF). 83

85 Figure 6. Implementing a MOD-8 counter using 7 LK () (3) () () (5) () () (3) PRE J K LR PRE J (5) A (6) (9) B () (3) () () (5) () () (3) PRE J K LR PRE J (5) (6) (9) REMEMBER J=K= for toggle operation PRE=LR= for synchronous operation () () K LR (7) () K LR (7) Implementation of MOD-6 ounter using 7 Figure 6.3 MOD -6 counter LK () (3) () () (5) () () (3) PRE J K LR PRE J (5) A (6) (9) B () (3) () () (5) () () (3) PRE J K LR PRE J (5) D (6) (9) REMEMBER J=K= for toggle operation PRE=LR= for synchronous operation () () K LR (7) () () K LR (7) Implementation of MOD- ounter Up till now, we ve only discussing about counter with MOD number n (e.g. MOD-8, MOD 6). To build a counter with MOD number other than n, other logic gates are needed for resetting the counter to. Let s take a MOD- counter as an example. Step : Determining amount of JK FF needed. For a MOD- counter, we need unit of JK FF (because =, that means -bit). Step : Determining the reset logic A JK FF counter is in essence a MOD-6 counter. To make it into a MOD- counter, it needs to be reset, after it reaches (9 ). In other words, when the output is ( ), it will immediately 8

86 reset/clear all the JK FF by sending a low signal to the LR input. This is done by using a NAND gate with the input connected to D and B (because mean that D and B are equal to HIGH while and A are equal to LOW). Step 3: Drawing the block diagram Figure 6. Block diagram of a MOD- counter LK J K PRE PRE PRE J J J K K K PRE LR LR LR LR LK A B D A B D (MSB) DE Glitch Glitch Step : ircuit implementation Although output ( ) appeared (suppose to be until (9 )), this output only last for a fraction of a second before it will reset the counter and are hardly noticeable. It will only appear as a glitch rather than a pulse. () () LK (3) () () (5) PRE J K LR (5) A (6) (3) () () (5) PRE J K LR (5) D (6) () () () (3) PRE J (9) B () (3) PRE J (9) () () K LR (7) () () K LR (7) 85

87 The 7LS93: Decade ounter,-bit Binary ounter It can be seen that it s quite tedious to use 7 I for counter implementation. As a better option, we have -bit binary counter I (7LS93). This decade counter is divided into two part, divide by eight and divide by two. It is triggered by using NGT edge of clock pulse. Figure 5.58 I 7LS93: Decade ounter,-bit Binary ounter pin diagram (left), logic symbol (right) and internal circuitry (bottom). N N N N GND LS Vcc MR MR P P 3 Vcc () () P () P () MR (3) & MR (8) Gnd (8) () (5) (9) J PRE PRE PRE PRE J J J P K K K K LR LR LR LR P MR MR 3 Note that the output of is not hardwired to the clock input of the next JK FF. Therefore it needs to be connected externally. The purpose is to add flexibility for this I. The MR (master reset) is used for counter with MOD number not equal to n (will reset all the JK FF when both are input are HIGH). Figure 6.5 MOD- counter using 7LS93 LK () () () (3) P P MR & MR (8) () (5) (9) D (MSB) B A A MOD- counter is also known as decade counter 86

88 Figure 6.6 MOD- counter using 7LS93 LK () P () P () MR (3) & MR (8) () (5) (9) D(MSB) B A REMEMBER Because there only two MR s, an external AND gate are used because ( ). Figure 6.7 MOD-6 counter using 7LS93 LK N () () () (3) P P MR & MR (8) () (5) (9) D (MSB) B A NOT USED REMEMBER Because MOD-6 only requires 3 JK FF (3-bit), the st JK FF is not connected. So we have look at few types of counter. But the entire counter we ve seen so far is a count-up type. For a count-down type counter, the connection is shown below. Figure 6.8 MOD-8 Down ounter (right) and waveform (below). LK J K A J B J Notice how the clock connection K K differs from a count-up counter. LK A B (MSB) DE Figure 6.9 MOD-6 Down counter J A J B J J D LK K K K K 87

89 6. SYNHRONOUS OUNTER The problem with asynchronous counter is that because the signal are rippled from one FF to another, the delay for each FF are accumulated (remember the case of a ripple carry adder). This problem can be overcome by using synchronous counter (a.k.a. parallel counter). Unlike asynchronous counter, synchronous counter has a common clock signal. Thus, all the changes at the output happen at the same time for the entire FF. Figure 6. MOD-6 counter counting steps Therefore, we cannot set both J and K to HIGH (like an asynchronous counter) but we need to control which FF will toggle at which specific time. To do this lets examine the counting steps. OUNT D B A (LSB) (MSB) From the table, it can be seen that:. A (LSB) will toggle at every triggering edge. Thus J=K=. B will toggle at every triggering edge when A =. Thus J=K= A 3. will toggle at every triggering edge when both A and B are HIGH (). Thus, J3 K3 A B. D (MSB) will toggle at every triggering edge when both A and B and are HIGH (). Thus, J K A B 88

90 Because of the AND operation, it s obvious that these counter requires extra circuitry and the final circuit are shown in figure 6.. Figure 6. MOD-6 synchronous counter J J J 3 J K K K 3 K LK A B D For a synchronous counter with MOD number not equal with n, we will use the LR input to reset the counter (same as the asynchronous counter). Figure 6. MOD- (decade) synchronous counter J K J K J 3 K 3 J K LR LR LR LR LK A B D Presetable Synchronous ounter A pressetable counter allows user to preset (load) the start of the counting sequence. There are two type of preset, asynchronous and synchronous. This operation (preset) is also referred a parallel loading. Figure 6.3 shows a -bit presettable asynchronous counter. 89

91 Figure 6.3 -bit Presetable Synchronous ounter P P P P3 J PRE PRE PRE PRE J J 3 J K K K 3 K LR LR LR LR LK PE (Parallel load) A B D From figure 5.66, a presetable synchronous counter has a -bit parallel data input (P to P3). Notice that these inputs are connected to a NAND gate. This NAND gate acts like an enable or disable gate. Inputs from parallel data input are enabled only when the other input (PE) is LOW and these input value will be stored in the counter (each JK FF will stored bit). Because of these JK FF uses asynchronous PRE and LR, the synchronous input (LK) are ignored until PE goes back to HIGH. Only then the counting will start. The 7LS63: Synchronous -bit ounter A part from being a synchronous counter, this I also allows parallel enable feature. This feature enables the I to be loads with value to start the counting (load). Thus, it is called a presetable (because can be preset) synchronous counter. Note that this I triggers on PGT. Figure 6. 7LS63 : Synchronous -bit ounter with Parallel Load SR P P P P P3 E P GND LS Vcc T 3 ET 8 9 PE (9) (3) () (5) (6) () PE P P P P3 P (7) E P () ET () SR Vcc (6) 3 T () () (3) () (5) (8) Gnd 9

92 Synchronous Down/Up ounter In previous chapter (asynchronous counter), we saw that an up counter can be modified to a down counter by changing the clock input of the next FF to the inverted output. To design an up/down counter (which we can choose by a control line), we will use an AND gate to function as an enable/disable gate. Figure 6.5 shows a 3-bit up/down synchronous counter. It will count down when control is HIGH () (gate and will be enabled) and up when control is LOW () (gate and 3 will be enabled). Figure 6.5 MOD-8 synchronous up/down counter J A J K 3 B J A K B K UP/ DOWN LK The 7LS9: Presetable -bit Up/Down Synchronous ounter This I offers two mode of operation, count up or count down depending on the U/D input. If U/D is HIGH (), it will count down and if U/D is LOW (), it will count up. E (count enable) must also be low to enable this I. Just like 7LS63, this I also offer parallel load feature for presetting this counter. Figure 6.6 7LS9: Presetable -bit Up/Down Synchronous ounter pin diagram (left) and logic symbol (right) P E U/D 3 GND LS Vcc P P R T PL P 8 9 P3 Vcc (6) () PL 3 (5) P () P () P (9) P3 () P (5) U/D T () E (3) R (7) (6) () (3) (5) (8) Gnd 9

93 5.3 STATE MAHINE State machine can be view as a synchronous counter with irregular sequence unlike a normal counter. State machine are also called a sequential circuit. In general, a state machine can be divided into two type: Moore machine: the next state (output) depends only on the present internal state. Mealy machine: the next state (output) depends on the present internal state and input at that time. Designing a state machine follows steps below (you may skip certain steps depending on the task):. State diagram: Diagram that shows all the transition of states when clock are triggered. Amount of FF needed are also determine depending on the bit.. Next state table: Table that listed all the present state along with its next state. 3. Excitation table: Listed all the J and K connection for all FF for the transition in next state table to occur. This is done by following the JK FF transition table. Figure 6.7 JK FF transition table Output Transition FF Inputs n n+ J K X X X X. K-map: To determine the simplified logic expression for all the J and K input. 5. ircuit implementation: Draw the complete circuit. 9

94 Moore Machine Task : Design a 3-bit Gray code up counter. Step : State diagram Figure 6.8 State diagram of a count up Gray code counter You may want to do some revision on Gray code first before going into this section. Because this is a 3-bit state machine, three JK FF are required. Note that JK FF is the MSB. Figure 6.9 MOD-8 synchronous up/down counter J A A J B B J FF A FF B FF K A A K B B K Step : Next state table Present State Next State B A B A It is advisable to arrange the table based on the present state in incremental binary counting order. 93

95 Step 3: Excitation table Present State Next State FF FF B FF A B A B A J K J B K B J A K A X X X X X X X X X X X X X X X X X X X X X X X X Step : K-map (We need 6 K-map, two for each JK FF). FF J input K input A B x x B A B A B A x x x x J K B B A A x x FF B J input K input A B B A x x x x A x x A J K B B A A x x 9

96 FF A J input K input A B x x x x B B B A x x x x B B J A K A B B Step 5: ircuit implementation Figure 6. Gray code up counter J A A J B B J FF A FF B FF K A A K B B K LK Task : Design a 3-bit Moore state machine with state diagram shown in figure 6.. Figure 6. State diagram for task 95

97 Step : Next state table Present State Next State B A B A Step 3: Excitation table PRESENT STATE NEXT STATE FF FF B FF A B A B A J K J B K B J A K A X X X X X X X X X X X X X X X X X X X X X X X X Step : K-map (We need 6 K-map, two for each JK FF). FF J input K input A B B A x x B A B x x x x J K B B A A x x A 96

98 FF B J input K input A B B A x x x x A A x x K JB A B A x x FF A J input K input A B x x x x B B B B A x x x x J A K A B B Step 5: ircuit implementation Figure 6. Gray code up counter J A A J B B J FF A FF B FF K A A K B B K LK 97

99 Mealy Machine Because of a Mealy machine output(s) also depend on the present input(s); the input will be treated just like another state variable. Task: Design an up/down Gray code counter. If input Y is LOW (), it will count down, and if Y is HIGH (), it will count up. Figure 6. State diagram for task 3 Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Step : Next State Table PRESENT STATE NEXT STATE (Y=) NEXT STATE (Y=) B A B A B A 98

100 Step : K-map FF J input A Y B K input A Y B x x x x x x x x x x x x x x x x x J A ( B Y) K A ( B Y) FF B J input A Y B K input A Y B x x x x x x x x x x x x x x x x J K B A A ( ( Y) Y) FF A J input A Y B K input A Y B x x x x x x x x x x x x x x x J A K A B Y B Y 99

101 Figure 6. ircuit For task 3 Y A A B J FF K J B B FF B K B B J A A FF A K A A 5. SERIAL IN / SERIAL OUT SHIFT REGISTER (SISO) This register takes in serial data; shift it, the output data in serial format. The shift operation may be a shift right, left or both (depending on the design). Figure 6.3 Basic Data Movement of a Shift Right SISO (above) and Shift Left SISO (below) Data in Data out Data out Data in A register in a microcomputer has capabilities to do both type of shifting. A basic -bit SISO register (right shift) comprises of four PGT edgetriggered D FF. Data from input will move from input of the FF to the input of the next one at every PGT. Therefore, it will take four clock pulses for the data from DATA IN to get to the DATA OUT. Figure 6. A -bit Shift Right SISO DATA IN A B D D D D DATA OUT LK

102 Let s examine the operation of the circuit in figure 6.. A -bit data ( ) are inserted serially (shift in/loading) in the DATA IN beginning with the rightmost bit (LSB). Figure 6.5 shows what happen to the inserted data after each clock pulse. Figure 6.5 Basic SISO operation (shift in) DATA IN D D D D FF A FF B FF FF D DATA OUT Initial condition, all FF output are cleared. LK DATA IN D D D D FF A FF B FF FF D DATA OUT After the st clock pulse, the LSB at the input D of FF A will be transferred to the of FF A LK DATA IN LK DATA IN D D D D FF A FF B FF FF D D D D D FF A FF B FF FF D DATA OUT DATA OUT After the nd clock pulse, the next bit at the input D of FF A will be transferred to the of FF A and the LSB at that already at the input of FF B will be transferred to of FF B After the 3 rd clock pulse, the next bit at the input D of FF A will be transferred to the of FF A and the other bit are shifted to the next FF LK DATA IN D D D D FF A FF B FF FF D DATA OUT After the th clock pulse, all the data has been loaded into this SISO register. Data can be stored until another clock pulse received (or the power is off) LK To get back the data stored, data are shifted out serially. This is explained in figure 6.6. Figure 6.6 Basic SISO operation (shift out) DATA IN LK DATA IN LK D D D D FF A FF B FF FF D D D D D FF A FF B FF FF D DATA OUT DATA OUT To shift the data out, new data must be inserted to push out the existing data. In this case, data will be inserted. This data is chosen because it will also clear the SISO register. After the 5 th clock pulse the st are transferred to of FF A and by that, all the bit in the other FF are shifted to the next FF.

103 DATA IN LK DATA IN D D D D FF A FF B FF FF D D D D D FF A FF B FF FF D DATA OUT DATA OUT After the 6 th clock pulse the nd are transferred to of FF A and by that, all the bit in the other FF are shifted to the next FF. After the 7 th clock pulse all the data bit in the SISO register has been outputted serially. LK DATA IN D D D D DATA OUT FF A FF B FF FF D After the 8 th clock pulse the register has been clear (reset). LK An 8-bit SISO register can be represented by a logic symbol shown in figure 6.7. Data in LK SRG REMEMBER SRG 8 stands for Shift Register with 8-bit capacity 5.5 SERIAL IN / PARALLEL OUT SHIFT REGISTER (SIPO) This register takes in serial data; shift it, and when done, output the data in parallel. Figure 6.7 Basic Data Movement of a SIPO Data in Data out Figure 6.8 A -bit Shift Right SIPO DATA IN D D D D LK A B D DATA OUT Let s examine the operation of the circuit in figure 6.9. A -bit data ( ) are inserted serially (shift in/loading) in the DATA IN beginning with the rightmost bit (LSB). Figure 6.5 shows what happen to the inserted data after each clock pulse.

104 Figure 6.9 Basic SIPO operation DATA IN D D D D FF A FF B FF FF D Initial condition, all FF output are cleared. LK DATA IN DATA OUT D D D D FF A FF B FF FF D After the st clock pulse, the LSB at the input D of FF A will be transferred to the of FF A LK DATA IN LK DATA OUT D D D D FF A FF B FF FF D After the nd clock pulse, the next bit at the input D of FF A will be transferred to the of FF A and the LSB at that already at the input of FF B will be transferred to of FF B DATA IN LK DATA OUT D D D D FF A FF B FF FF D After the 3 rd clock pulse, the next bit at the input D of FF A will be transferred to the of FF A and the other bit are shifted to the next FF DATA IN LK DATA OUT D D D D FF A FF B FF FF D DATA OUT After the th clock pulse, all the data has been loaded into this SIPO register. Data can be stored until another clock pulse received (or the power is off) and can be retrieved simultaneously (in parallel). An 8-bit SIPO register can be represented by a logic symbol shown in figure 6.3. Figure 6.3 Logic symbol for an 8-bit SIPO Data in LK SRG

105 The 7LS6: 8-bit Serial in / Parallel out Shift Register This I has two data input, A and B. Data is entered serially through either A or B with the other function as enable/disable control or tied to Vcc if unused. It also has asynchronous active low master reset (MR). Figure. The 7LS6: 8-bit Serial in / Parallel out Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom). A B 3 GND A B LS Vcc MR P A B P MR () () (8) (9) () Vcc GND (7) (3) () (5) (6) () () () (3) Examining from the internal circuitry: (i) If the leftmost bit is entered st, which of the output is the MSB after the 8 th clock pulse? (ii) How to use this I as SISO? D D D D D D D D P MR LR LR LR LR LR LR LR LR PARALLEL IN / SERIAL OUT SHIFT REGISTER (PISO) Parallel in enables data to be entered simultaneously rather than one bit at a time directly into its respective stage (FF). Data are outputted bit by bit (serially). Figure. Basic Data Movement of -bit PISO (left) and logic symbol (right) Data in Data out SHIFT / LOAD LK Data in D D D SRG D 3 Data out A PISO has a control input (SHIFT/LOAD) to set the operation mode of this circuit. When this input is LOW (), this register is in LOAD mode, meaning that all the DATA IN will enter their respective FF at the next triggering edge; and when it is HIGH (), this register is in SHIFT mode, meaning that all the bits is shifted to the next FF at every triggering

106 Figure. -bit Parallel in/ Serial out internal circuitry. edge. SHIFT/LOAD DATA IN D D D D D D D D 3 LK Referring to figure., when the control input (SHIFT/LOAD) is: LOW (): AND gate, 3, 5 and 7 will be enabled allowing DATA IN bit to enter their respective FF at the next triggering edge while AND, and 6 are disabled, stopping all the shifting. HIGH (): AND gate, and 6 will be enabled allowing data to be shifted to the next FF at the next triggering edge while AND, 3, 5 and 7 are disabled. The 7LS65: 8-bit Parallel In/ Serial Out Shift Register The 7LS65 uses SHIFT/LOAD input to determine its operation. If its LOW (), it will load value D to D 7 into the register and if it is HIGH (), the register will shift its content (while parallel input is disabled). This I also allows serial data input through DS (only when SHIFT/LOAD input is HIGH ()). locking is accomplished through a -input OR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH (if not, it will assume the level change as clock). 5

107 Figure.3 The 7LS65: 8-bit PISO Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom). SHIFT / LOAD LK D D5 D6 D7 7 GND SHIFT/ LOAD 7LS D Vcc LK INH D3 D D D DS 7 () SHIFT / LOAD () DS (8) LK (9) LK INH (3) D () D (5) D (6) D3 () D () D5 () D6 (3) D7 7 7 (9) (7) D D D 3 D D 5 D 6 D 7 Examining from the internal circuitry: (i) How to use this I as a SISO? DS D D D D D D D D 7 LR LR LR LR LR LR LR LR LK LK INH 5.7 PARALLEL IN / PARALLEL OUT SHIFT REGISTER (PIPO) A parallel in/ parallel out shift register takes all the DATA IN bit simultaneously and after triggering edge, the data are available for retrieval at the output line. Figure. Basic Data Movement of -bit PIPO (left) and logic symbol (right) and internal circuitry (bottom) Data in Data out DATA IN D D D D3 D D D D LK D Data in D D SRG Data out D 3 3 LK 3 DATA OUT 6

108 The 7H95: -bit Parallel Shift Register This shift register features parallel inputs, parallel outputs, JK inputs, SHIFT/LOAD control input, and a asynchronous LEAR. This shift register can operate in two modes: PARALLEL LOAD; SHIFT from A towards D. Parallel loading is accomplished by applying the four bits of data, and setting the SHIFT/LOAD control input to LOW (). The data is loaded into the respective FF and available at the outputs after the positive transition of the clock input (triggering edge). During parallel loading, serial data flow is disabled. Serial shifting occurs synchronously when the SHIFT/LOAD control input is HIGH (). Serial data for this mode is entered at the J-K inputs. Figure.3 The 7LS95: -bit Parallel Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom). LR J K D D D D3 GND SHIFT/ LOAD H Vc c 3 3 LK SHIFT / LOAD (9) SHIFT / LOAD J K LK LR () (8) (9) () () (5) (6) (7) D D D D3 (5) () (3) () 3 () 3 Examining from the internal circuitry: (i) How to use the J K input for serial DATA IN J K D D D D 3 LR LK 3 3 7

109 TUTORIAL. What is the difference between a LATH and a FLIP-FLOP? (a) Latch is a level sensitive device while flip-flop is an edge sensitive device. (c) Latches take less gates (also less power) to implement than flip-flops. (b) Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches. (d) all above. A bistable multivibrator is (a) an electronic circuit (c) capable of serving as one bit of memory (b) has two stable states (d) all of above 3. Which of the following circuit realized a D flip-flop? (a) (b) (c) (d) 3. For a gated D latch, the output always equals the D input (a) before the enable pulse (c) immediately after the enable pulse (b) during the enable pulse (d) answers (b) and (c) 8

110 . A JK flip-flop is presently in the SET state and must remain SET on the next clock pulse. What is the input J and K? (a) J must be and K must be. (b) J must be and K must be. (c) J must be and K must be (d) Answer (b) and (c) 5. When will the second flip-flop update its output Z? (a) When the input Y is changed. (c) When the clock value changes from low to high. (b) When the clock value changes from high to low. (d) Never. 6. Asynchronous counter are known as (a) ripple counters (c) decade counters (b) multiple clock counters (d) modulus counter 7. For a finite state machine with 3 states, the number of storage elements (flip-flops) needed to implement the sequential machine circuit is (a) 3 (b) 5 (c) 5 (d) 8. In a clocked sequential circuit, the finite state machine can make a transition from one state to another state: (a) only once per clock cycle (c) at any time (b) only when it is in the initial state (d) depends on the combinational logic 9

111 9. Which of the following shows the connection for mod-6 counter using a decade counter? (a) (b) (c) (d). The waveforms in Figure 6 are applied to the inputs A & B of a flip-flop. Based on the waveform of output, determine the type of flip-flop. (a) S flip-flop with PGT (c) S flip-flop with NGT (b) JK flip-flop with PGT (d) JK flip-flop with NGT. Which of the following is NOT a characteristic of the latches?

112 (a) Temporarily stored the data. (c) The outputs respond to the present inputs. (b) The operations are synchronous. (d) The latches are bistable devices.. For a positive edge-triggered JK flip-flop with preset and clear inputs in figure above, determine the output at clock pulse 6, 7 & 8. (a) (b) (c) (d) 3. A feature that distinguishes the JK flip-flop from the S flip-flop is the (a) toggle condition (c) preset input (b) clear input (d) type of clock. A JK flip-flop with J = and K = has a 5 khz clock input. The output is (a) constantly low (c) a khz square wave (b) a 5 khz square wave (d) a.5 khz square wave 5. Asynchronous counters are also known as ripple counter. How many JK flip-flops are needed to build MOD 3 counters?

113 (a) (b) 6 (c) 5 (d) 7 6. Indicate the type of the counter in Figure 3. What would be the values of, and when PL is low if P, P and P are, and respectively? (a) Ripple counter, (c) Ripple counter, (b) Presettable synchronous counter, (d) Presettable synchronous counter, 7. Which of the following is NOT the characteristic of Moore state machine? (a) Output signals can have asynchronous changes (c) Output signals are all synchronous. (b) Moore output is a function only of the current flip-flop. (d) Next states of Moore machine depend solely on the present states. 8. A -bit ripple counter has a 56 khz clock signal applied. Determine the frequency at the MSB output and the MOD number of this counter.

114 (a) 5 Hz, (b) 5 Hz, (c) Hz, (d) Hz, 9. The invalid state for a S latch occurs when (a) S=, = (b) S=, = (c) S=, = (d) S=, =. Like the latch, flip-flop belongs to a logic circuit known as (a) monostable multivibrator (b) bistable multivibrator (c) astable multivibrator (d) one-shots. The purpose of having the clock input to a flip-flop is to (a) clear the state (b) always cause the output to change states (c) set the flip-flop (d) cause the output to assume a state dependent on the controlling (S,JK,D) inputs. For an edge triggered D flip-flop, (a) state changes can only occur at the clock pulse edge (c) the output follows the input at each clock pulse (b) (d) the state the flip-flop goes to depends on the D input all of the above 3. A JK flip-flop is in toggle mode when (a) J=, K= (b) J=, K= (c) J=, K= (d) J=, K=. An asynchronous counter differs from a synchronous counter in (a) the method of clocking (b) the type of flip-flop used 3

115 (c) the number of states sequence (d) the modulus value 5. A 3 bit binary counter has a maximum modulus of (a) 3 (b) 6 (c) 8 (d) 6 6. A BD counter is also known as (a) decade counter (c) a truncated modulus counter (b) full modulus counter (d) both (a) and (c) 7. omplete the following table of flip-flop excitation values required to produce the indicated flip-flop state changes, where X indicates the present state and Y is the desired next state of the flip-flop. Present state Next State J-K Flip flop S Flip flop D Flip flop X Y J K S D 8. Given the JK flip flop as shown in the Figure 8 below. omplete the timing diagram of Figure 8 by determining the output waveform of. Figure 8 9. The circuit of Figure 9contains a D latch, a positive edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. omplete the timing diagram of Figure 9 by drawing the waveforms of the signals y, y and y 3.

116 Figure 9 3 (a) Draw the state transition diagram for a three bit counter that has the following counting sequence:,,,,6,7,3,5,, repeats. (b) What is the MOD number of the counter? (c) If the counter is initially at, what count will it hold after 3673 pulses? 3. A clock generator system's input frequency is 36 khz. The system is required to generate two frequencies 9 khz and 3 khz at its outputs. Propose an arrangement for frequency division by using counters. 3. Design a state machine based on state diagram given in Figure 3 below by using Moore machine. Assume state,3,,6 as don t care. Implement the circuit by using JK flip-flop. Figure Given the circuit diagram of Figure 33, complete the timing diagram of Figure 33 for A, B and. 5

117 Figure Analyse the circuit diagram of Figure 3(a) and complete the timing diagram of Figure 3(b). Do not show the propagation delays. Draw the truth table of this circuit. (a) Input Before After A B (b) 35. Design and realise a 3-bit counter that counts in the following sequence:,,,,,,,,,, 6

118 Use JK flip-flops in this design. 36. omplete the timing diagram for this circuit. The initial states of D flip-flops and input waveforms are shown in Figure 36. Figure Table 37 is a state table for a circuit operation. Assume you make use of J-K flip flop in the design. X is the external input and Z is the output of the circuit. Draw the logic diagram for the sequential circuit Present state Next State Output Z AB X= X= X= X= 38. Explain one () advantage and one () disadvantages of a synchronous counter compared with an asynchronous counter using suitable example or figure. 7

119 39. Figure below shows the block diagram of a digital clock. Show the connection for counter A, B and using I 7LS93.. Design an asynchronous counter that will count in a sequence of 6, 5,, 3,, and repeat. Use only J-K flip-flop that has two active low control inputs PRE and LR. Explain the operation of your design briefly.. Figure below show the logic symbol of 7LS93, -bit binary counter. Show how it can be used to generate a KHz clock from the 6KHz clock source. Label completely. lock () P (8) 6KHz () P () () (3) MR MR & (5) (9). Eight sensors each feed eight bits of information to a circuit which processes the information. It is decided that instead of using 6 signal lines, the data will be multiplexed onto eight data lines with three address lines used to indicate the sensor using the data lines. In fact, the sensors will be continually cycled through in order. (i) (ii) (iii) A three-bit counter is required to cycle through the values for the address lines. Design it using JK flip-flop. You may assume the availability of a clock signal. An 8: multiplexer has eight data inputs, three control inputs and an output. The value of the control inputs determines the data input which is selected as the output. Design an 8: multiplexer. Show how these components could be used to build the required system. 8

120 3. (a) A -bit shift register constructed from edge-triggered D-type flip flops is shown in Figure 6(a). If, on successive rising edges of the clock signal LK, the input takes on the values,,,,,,,, what are the contents of the shift register after each edge of the clock? You may assume that the register contains all zeroes initially. (3 marks) (b) (c) The shift register in 6(a) is require to detect bit pattern from the serial data feed into the input pin. Design and illustrate how a combinational logic circuit can be added to achieve this. This combinational logic circuit will produce an output HIGH () when the pattern is detected. (7 marks) Figure 6(c) shows a state transition diagram for an infinite state machine with control input, Y. Design the circuit using JK flip-flop. (5 marks). The circuit of Figure 3(a) contains a D latch, a positive edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. omplete the timing diagram of Figure 3(b) by drawing the waveforms of the signals y, y and y 3. 9

121 5. Given the circuit diagram below, complete the timing diagram for A, B and. Assume that A, B and are at high level initially. 6. Design a circuit that will generate TWO () frequencies, khz and 3 khz at its outputs when a clock signal applied to the circuit is operating at 8 khz. Use JK flip-flops in your design.

122 7. Determine and draw the state transition diagram for the Moore machine below. J A A J B B J FF A FF B FF K A A K B B K LK

123 SUBJET: EXPERIMENT 7: ELETRIAL ENGINEERING LABORATORY BEE 9 DIGITAL ELETRONIS Full Modulus MOD-6 Asynchronous ounter PRELAB TASK. Show (in drawings) how a four JK flip-flop can operate as a MOD-6 counter.. Re-draw this circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit. LAB TASK. onstruct circuit on the protoboard.. onnect all the outputs to LED and verify that the counter is functioning correctly. 3. Write a brief comparison about the advantages and disadvantages between an asynchronous counter and a synchronous counter.. Modify this circuit to implement a MOD- counter 5. Write a brief discussion about the difference between a full modulus counter and a truncated counter. EXPERIMENT 8: PRELAB TASK Building a 3-bit Moore machine. Figure shows the state diagram of a 3-bit Moore machine. Build the next state table for this counter.. Build the excitation table. 3. Using k-map, get simplified expression for the circuit.. Draw the circuit using 3 J-K flip-flops. 5. Re-draw this circuit complete with I and pin numbers (refer datasheet for the I pin assignment). Name this circuit as circuit. LAB TASK. Build circuit on the protoboard.. Make sure every I is connected to +5V and ground properly. 3. Verify that the counter is functioning correctly.. What are the difference between state machines and counter?

124 HAPTER 7 DIGITAL SYSTEM INTERFAING OUTLINE DIGITAL-TO-ANALOG (DA) ONVERSION DA IRUITARY DA PERFORMANE DA ONVERSION ERROR REONSTRUTION FILTER ANALOG-TO-DIGITAL (AD) ONVERSION SAMPLE AND HOLD 3

125 In chapter, we have discussed about the overcoming the limitation of digital system by using AD (analog-to-digital converter) and DA (digital-to-analog converter). This chapter will discuss the detail about interfacing a digital system with analog world. 7. DIGITAL-TO-ANALOG ONVERSION (DA) We will start by discussing about DA first. This is because DA is simpler than AD process and AD circuit also contains DA circuit. Remember that a digital signal comprises of binary bits, while analog signal can either be voltage or current. Depending on the value (or combination) of the digital input, the corresponding predetermine analog signal will be outputted. Binary-Weighted-Input DA One method of DA is by using resistor with different value for each bit. The LSB has the largest value resister (lowest current) while the MSB has the smallest value resistor (largest current) because each binary bit has different weight. The typical circuit is shown in figure 7.. If there is voltage at the input (input HIGH), there will be current across the resistor and this current value varies between each input because of the different resistor value. Because there is practically no current at the inverting input of the opamp (virtual ground), all the input current are summed together and the drop across R f is equal to the output voltage. Figure 7. Typical Binary- Weighted- Input DA ircuit D D D 8 R R R I I I - + Rf V =I f R f D 3 R I 3 The disadvantage of this type of DA is the input level must be the same and the amount of resistor needed in a higher bit input DA. If there is 8-bit input, the resistor must be in the range of R to 55R, making this type of AD very difficult to mass-produce. Lets us examine circuit in figure 7.. We are going to feed binary input () to (7) and calculate the corresponding output.

126 Figure 7. Example value of a Binary- Weighted- Input DA ircuit D D D D 3 kω kω 5 kω 5 kω I I I I kω V =I f R f For a +5 input (typical value for digital circuit) the current at each inputs are: 5V I.5mA kω 5V I.5mA kω I I 3 5V 5kΩ 5V 5kΩ.mA.mA Therefore, kω.5ma.5v V out(d) kω.5ma.5v V out(d) V out(d) V out(d3) kω.ma V kω.ma V Figure 7.3 shows the output voltage for each of the input combination. Figure 7.3 Binary- Weighted- Input DA ircuit Output INPUT OUTPUT D 3 D D D V V Input (binary) 5

127 Notice that in the graph in figure 7.3, the analog output is not pure analog signal (it look more like a step). In fact, a DA output cannot produce a pure analog signal (which varies continuously with time). DA Resolution Resolution determines the accuracy of a DA and it can be expressed as the step size or the number of step. The different between each step in the graph in figure 7.3 is the step size. It is defined as the smallest change that can occur in the analog output corresponding to the input. So, for DA in figure 7.3, the step size is.5 V. The smaller the step size, the more analog the output will be (because of the step is smaller). So, the smaller the step size, the better DA it is. REMEMBER Don t get confuse with resolution in digital imaging. The resolution in image is often referred to the amount of pixel in a specific size image. Thus, the higher resolution is, the better the picture quality. Resolution (step size) is calculate with the formula below resolution (step size) K A n fs where A fs = analog full-scale output n = the number of bits From the formula, it can be seen that to decrease resolution, the full-scale analog output must be kept small and the number of bits is high. But achieving high resolution is not easy and maybe costly. Not easy because the A fs is depended on the application the DA are used in and costly when the bits is higher (more gates). Although higher resolution is better, it may not always necessary to have it. Let s take a D motor speed controller as an example; a small increase in current may not be enough to vary the motor speed. Thus, using a small resolution DA will be a waste. Resolution may also be expressed in percentage using the formula below. 6

128 Step size % resolution (step size) % A fs Resolution can also be referred to the number of discrete steps in the output, which is dependent on the number of bits for the input. For example a -bit DA has 5 steps (each step is one part of fifteen. This can also be expressed in percentage as 6.67% or the number of bits converted. Input Weight Each of the bits in the binary input has different amount of contribution to the output (weight). Taking DA in figure 7.3 for example, the weight for D 3 is -V, D is -V, D is -.5V and D is -.5V. The MSB (D 3 ) has the most weight while LSB (D ) has the least. The weight of the LSB is also the DA resolution 7. DA IRUITARY We are going to take a look at several DA circuit. The first one is the Binary-weighted-input DA which we already seen in figure 7.. This DA consist of a resistor network to give every input a different weight and then been connected to a summing op-amp. One of the problems for this type of DA is that V out is dependent on the digital input voltage. In the previous example, the weights of each bit are calculated by assuming the input is 5V, which is the ideal case. To overcome this, additional circuits are needed to provide a precise input voltage. Binary-Weighted-Input DA ircuit With Reference Supply Figure 7. shows an improved version of Binary-weighted-input DA. It has a reference supply to keep the input voltage of the DA to 5V. Each digital input control an electronic controlled switch (can also be relay) to connect or disconnect the DA input to the reference supply. If the digital input is HIGH (), the switch will closed and the DA input for that bit will be pulled to 5V (reference supply) 7

129 Figure 7.3 Binary- Weighted- Input DA ircuit With Reference Supply D D Reference Supply 8 R I R I - + Rf V =I f R f D R I D 3 R I 3 The R/R Ladder DA Another problem with Binary-Weighted-Input DA is that the value or R (resistor) can be very large. Let say we have an 8-bit DA. The resistor value will be between R and 8R and the tolerance must be low to give an accurate result. This problem can be overcome by using R/R Ladder DA. It only uses two resistor value, R and R. In this circuit, the MSB is D 3. Figure 7.3 The R/R Ladder DA D D D D 3 R R R3 R R5 R R7 R Rf = R R R R R R6 R R8 R - + V out Now let see this DA in action. We will do an analysis for several input condition. ase : D 3 =,D =,D =,D = Figure 7. The R/R Ladder DA with input 5V D= - R R R5 R7 R R R R + R R R3 R R5 R R7 R Rf = R V out 8

130 the equivalent circuit will be: Figure 7.5 The R/R Ladder DA with input D= (equivalent circuit) RE R 5V R7 R Rf = R - + V out therefore: V out IR f 5V R 5V R ase : D 3 =,D =,D =,D = Figure 7.6 The R/R Ladder DA with input 5V D= - R R R5 R7 R R R R + R R R3 R R5 R R7 R Rf = R V out the equivalent circuit will be: Figure 7.7 The R/R Ladder DA with input D= (equivalent circuit) RE R 5V R5 R R8 R R7 R Rf = R - + V out V TH.5V RTH R R8 R R7 R Rf = R - + V out therefore: V out IR f.5v R.5V R 9

131 ase 3: D 3 =,D =,D =,D = Figure 7.8 The R/R Ladder DA with input 5V D= - R R R5 R7 R R R R + R R R3 R R5 R R7 R Rf = R V out the equivalent circuit will be: Figure 7.9 The R/R Ladder DA with input D= (equivalent circuit) R3 R RE R 5V R6 R R5 R R8 R R7 R Rf = R - + V out V TH.5V RTH R R8 R R7 R Rf = R - + V out therefore: V out IR f.5v R.5V R ase : D 3 =,D =,D =,D = Figure 7. The R/R Ladder DA with input 5V D= - R R R5 R7 R R R R + R R R3 R R5 R R7 R Rf = R V out the equivalent circuit will be: 3

132 Figure 7. The R/R Ladder DA with input D= (equivalent circuit) R R R R 5V R R R3 R R6 R R5 R R8 R R7 R Rf = R - + V out V TH.65V RTH R R8 R R7 R Rf = R - + V out therefore: V out IR f.65v R.65V R 7.3 DA PERFORMANE Performance of DA are determine by the following characteristic: Resolution: (see previous subtopics) Accuracy: the comparison of the actual DA output with the expected output. Linearity: a linear error is a deviation from the ideal straight-line output of a DA. Monotonicity: a DA is monotonic if it does not take any reverse steps when it is sequenced over its entire range of input bits. Settling time: normally defined as the time a DA takes to settle within ± ½ LSB of its final value when input code changes. 3

133 7. DA ONVERSION ERROR Several type of errors can arise in a DA are shown below. Figure 7. DA with nonmonotonicity error Analog Output Ideal Nonmonotonicity output Binary Input Figure 7.3 DA with non-linearity error Analog Output Ideal Non-linearity output Binary Input 3

134 Figure 7. DA with non-linearity error Analog Output High gain Ideal Low gain Binary Input Figure 7.5 DA with offset error Analog Output Ideal Offset Binary Input 33

135 7.5 REONSTRUTION FILTER To get a more analog output, the staircase like DA output are usually feed into a reconstruction filter (a.k.a. post filter) to smoothen the output. This is done by removing the higher frequency content of the signal by using a low-pass filter. Figure 7,6 below shows the signal at the input of this filter at the resulting output. Figure 7.6 Reconstruction filter input (left) and output (right). Analog Input Analog Output t t 7.6 ANALOG -TO- DIGITAL ONVERSION (AD) Now let s take a look an analog-to-digital converter (AD). As we know, AD takes an analog input signal and converts it into a digital signal (bit). It also has a DA as its main component. Figure 7.7 Basic 8-bit Digital Ramp AD block diagram Analog Input V A + - omparator lock V A DA ounter Reset Start D7.D Binary (digital output) 3

136 This is how the AD in figure 7.7 works. (i) (ii) (iii) A pulse (Start) is given to signal the start of the conversion process. When the start signal is HIGH (), the AND gate is disabled and no clock signal are feed into the counter. This HIGH () start pulse also reset the counter to. When the start pulse goes to LOW (), the AND gate are enabled thus allowing clock signal to go into the counter; as long as the output of the comparator is HIGH (). Output of the comparator will be HIGH when V A > V A. ounter will start to count (one count), and the outputs are feed into a DA which generate the analog value (V A ) of the current counter binary output. The comparator then compares V A with V A. If V A > V A, the AND gate will still be enabled, thus step (ii) and (iii) are repeated. (iv) When V A V A, output f the comparator will become LOW (), thus disabling the AND gate. As a result, the counter will stop counting (because there is no clock), and the current counter binary output is the digital value of the analog input. Because of the conversion will not always stop at V A = V A (can also stop when V A < V A, we can say that the binary digital output is an approximation of the analog input. Because the counter in this AD need to count until V A V A before the digital output can be obtain, this type of AD is slow, especially if the number of output bit increased and the time to finish vary depending on the analog input. Flash AD Flash AD, as the name implies, is a faster DA than successiveapproximation AD. In flash AD, multiple comparators are used, thus conversion are done simultaneously. When the input the input voltage exceeds the reference voltage of the comparator, output HIGH () will be generated. Each comparator reference voltage is different because of the voltage-divider resistor network. For an N-bit AD, the comparator needed is N - (less because we don t need conversion for V input. The high number of comparator for a high number of bits outputs is the main disadvantage of this AD. Outputs of these comparators are then connected to a priority encoder (see chapter ) to generate the binary digital value. Figure 7.8 below shows a 3-bit flash AD. 35

137 Figure 7.8 Basic 3-bit Flash AD. Analog Input +V REF omparator Priority Encoder D D D Digital Output SAMPLE AND HOLD Before AD conversion can be done, the analog value must hold still until the conversion is done, which is impossible because analog signal is a signal that varies over time. Therefore, to get a still signal, the analog signal is sampled and then hold until the conversion complete. Sampling is a process of taking a sufficient number of discrete values at points on the waveform. These discrete values are used to define the waveform shape. Figure 7.9 below shows an original analog signal that are being sampled by sampling pulse A and sampling pulse B (figure 7.). Figure 7. shows the resulting sampled signal. 36

138 Figure 7.9 Original Analog Signal Analog Input Analog Input Figure 7. Sampling Pulse Sampling Pulse (A) Sampling Pulse (B) Figure 7. Sampled Signal Sampled Signal Sampled Output As we can see from figure 7., a lower frequency of sampling pulse resulting in a less accurate discrete representation of the original signal. The proper frequency for sampling must be determined using Nyquist theorem. Nyquist Theorem: f sample f a (max) where f a(max) is the highest analog frequency. 37

139 HAPTER 8 INTEGRATED LOGI IRUIT FAMILY OUTLINE INTEGRATED IRUIT (I) BASI I HARATERISTI AND PARAMETER MOSFETs TRANSISTOR-TRANSISTOR LOGI (TTL) PROGRAMMABLE LOGI DEVIE (PLD) 38

140 Figure 8. utaway view of an I In this chapter, we will discuss the details of integrated circuit (or I). There are two type of I, the fixed function (which function has already been set by the manufacturer) and the programmable one. We will focus on the fixed function I and take a brief look at the programmable I at the end of this chapter. 8. INTEGRATED IRUIT (I) BASI The term integrated circuit (I) is a small chip made of silicon that contains the entire electronic circuit. This small chip are put inside a packaging and connected to the package pin for I/O connection. Figure 8. PGA Packaging Packaging The most common I packaging is the Dual-inline-package (DIP) such as in figure 8.. This packaging is for through hole-mounted circuit board or PB. For more complex I (more pins), Pin Grid Array (PDA) packaging are used. The disadvantage of this type of packaging is the space it used, and not suitable for multi layer circuit board. Surface mount technology (SMT) overcome this limitation by offering smaller size package and the pin can directly be soldered on the surface. Thus, allowing multi layer circuit board. 39

141 Figure 8.3 SOI (small outline I), a type of SMT Figures below show the various type of SMT package and a short explanation. Figure 8.3 PL Package I (above) PL socket (below) A Plastic Leaded hip arrier (PL) is a four-sided J -leaded plastic integrated circuit package with pin spacing of.5" (.7 mm). Lead counts range from to 8. PL PL sockets may in turn be surface mounted, or use thru-hole technology. The motivation for a surface-mount PL socket would be when working with devices that cannot withstand the heat involved during the reflow process, or to allow for component replacement without reworking. Figure 8. L Package I A leadless chip carrier (L) is a type of packaging for integrated circuits which has no "leads", but instead rounded pins through the edges of the ceramic package. Figure 8.5 SSOP Package I Figure 8.6 TSSOP Package I Shrink small-outline package (SSOP). A microchip package for surface-mount technology with "gull wing" leads protruding from the two long sides and a lead spacing of.5 inches. A TSSOP (Thin-Shrink Small Outline Package) is a four-sided, rectangular, thin body size surface mount component. A Type I TSSOP has leads protruding from the width portion of the package. A Type II TSSOP has the leads protruding from the length portion of the package. A TSSOP's lead count can range from 8 to 56.

142 Figure 8.7 P-LGA775 Package I (above) and socket (below) The land grid array (LGA) is a physical interface for microprocessors of the Intel Pentium and AMD Opteron families. Unlike the pin grid array (PGA) interface found on most AMD and Intel processors, there are no pins on the chip; in place of the pins are pads of bare gold-plated copper that touch pins on the motherboard. LGA processor sockets include Socket F (also called Socket 7) from AMD and the Prescott core Pentium and Xeon chip systems with the new model number system from Intel. I lassification I can be classified into several groups. The most common classification are by type and transistor count. By type: o Integrated circuits can be classified into analog, digital and mixed signal (both analog and digital on the same chip). o Digital integrated circuits can contain anything from a few thousand to millions of logic gates, flip-flops, multiplexers, and other circuits in a few square millimeters. The small size of these circuits allows high speed, low power dissipation, and reduced manufacturing cost compared with board-level integration. These digital Is, typically microprocessors, DSPs, and micro controllers work using binary mathematics to process "one" and "zero" signals. o Analog Is, such as sensors, power management circuits, and operational amplifiers, work by processing continuous signals. They perform functions like amplification, active filtering, demodulation, mixing, etc. Analog Is ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch. o Is can also combine analog and digital circuits on a single chip to create functions such as A/D converters and D/A converters. Such circuits offer smaller size and lower cost, but must carefully account for signal interference

143 By transistor count: o The first integrated circuits contained only a few transistors. alled "Small-Scale Integration" (SSI), they used circuits containing transistors numbering in the tens. SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missile and Apollo program needed lightweight digital computers for their inertially-guided flight computers; the Apollo guidance computer led and motivated the integrated-circuit technology, while the Minuteman missile forced it into massproduction. These programs purchased almost all of the available integrated circuits from 96 through 963, and almost alone provided the demand that funded the production improvements to get the production costs from $/circuit (in 96 dollars) to merely $5/circuit (in 963 dollars). They began to appear in consumer products at the turn of the decade, a typical application being FM inter-carrier sound processing in television receivers. o The next step in the development of integrated circuits, taken in the late 96s, introduced devices which contained hundreds of transistors on each chip, called "Medium-Scale Integration" (MSI). They were attractive economically because while they cost little more to produce than SSI devices, they allowed more complex systems to be produced using smaller circuit boards, less assembly work (because of fewer separate components), and a number of other advantages. o Further development, driven by the same economic factors, led to "Large-Scale Integration" (LSI) in the mid 97s, with tens of thousands of transistors per chip. Integrated circuits such as Kbit RAM, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 97s, had fewer than transistors. True LSI circuits, approaching transistors, began to be produced around 97, for computer main memories and second-generation microprocessors. o The final step in the development process, starting in the 98s and continuing on, was "Very Large-Scale Integration" (VLSI), with hundreds of thousands of transistors, and beyond (well past several million in the latest stages). For the first time it became possible to fabricate a PU on a single integrated circuit, to create a microprocessor. In 986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips produced in 99 contained more than three million transistors. This step was largely made possible by the codification of "design rules" for the MOS technology used in VLSI chips, which made production of working devices much more of a systematic endeavor.

144 o To reflect further growth of the complexity, the term ULSI that stands for "Ultra-Large Scale Integration" was proposed for chips of complexity more than million of transistors. However, there is no qualitative leap between VLSI and ULSI, hence normally in technical texts the "VLSI" term covers ULSI as well, and "ULSI" is reserved only for cases when it is necessary to emphasize the chip complexity, e.g. in marketing. The most extreme integration technique is wafer-scale integration (WSI), which uses whole uncut wafers containing entire computers (processors as well as memory). Attempts to take this step commercially in the 98s (e.g. by Gene Amdahl) failed, mostly because of defectfree manufacturability problems, and it does not now seem to be a high priority for the industry. The WSI technique failed commercially, but advances in semiconductor manufacturing allowed for another attack on I complexity, known as System-on-hip (SO) design. In this approach, components traditionally manufactured as separate chips to be wired together on a printed circuit board are designed to occupy a single chip that contains memory, microprocessor(s), peripheral interfaces, Input/Output logic control, data converters, and other components, together composing the whole electronic system. Technology I can be made by using either MOSFET (metal-oxide-semiconductorfield-effect-transistor) or bipolar junction transistor. I using MOSFET is MOS (complimentary MOS) while I using bipolar transistor is TTL (transistor-transistor-logic). ombination of both technologies is BiMOS. 8. I HARATERISTI AND PARAMETER D Supply Voltage The nominal D supply voltage for a TTL device is 5V while MOS device has several different supply voltages (5V, 3.3V,.5V and.v) depending on the categories. This supply voltage are distributed internally to all element within the I. 3

145 Logic Level There are four logic level in I specifications: V IL(max) : Low-level Input Voltage. The maximum input value (in volt) that the I will interpret as LOW (). Value higher than this will not be accepted as LOW () V IH(min) : High-level Input Voltage The minimum input value (in volt) that the I will interpret as HIGH (). Value lower than this will not be accepted as HIGH () V OL(max) : Low-level Output Voltage The maximum voltage level at the I output when in LOW () state under defined load condition. V OH(min) : High-level Output Voltage The minimum voltage level at the I output when in HIGH () state under defined load condition. Figure 8.8 Typical parameter for a 5V MOS I 5V 3.3V HIGH () V IH V IH(min) 5V.V HIGH () V OH V OH(min) Undefined Undefined.5V V IL(max) V LOW () V IL.33V V LOW () V OL V OL(max) Figure 8.9 Typical parameter for a 3.3V MOS I 3.3V V HIGH () Undefined V IH V IH(min) 3.3V.V HIGH () Undefined V OH V OH(min).8V V LOW () V IL(max) V IL.V V LOW () V OL V OL(max)

146 Figure 8. Typical parameter for a 5V TTL I 5V HIGH () V IH 5V HIGH () V OH V V IH(min).V V OH(min) Undefined Undefined.8V V LOW () V IL V IL(max).V V LOW () V OL V OL(max) Noise Immunity Noise is unwanted signal that practically exist in all electrical devices and can prevent circuit from operating properly. Noise can be generated internally or be pick-up externally. An I must be able tolerate certain amount of noise. Referring to figure 8., an input voltage for HIGH () logic level may fluctuate between V and 5V, and still be interpreted as HIGH (). But, once its drop below V (the V IH(min) ), it will goes into the undefined range, and the output is unpredictable. Noise Margin ircuit noise immunity are called noise margin, and measured in volt. There are two parameter for noise immunity: High-level noise margin (V NH ) = V OH(min) -V IH(min) Low-level noise margin (V NL ) = V IL(min) -V OL(min) Power Dissipation Logic gate will drawn current from the D supply voltage. There are two type of current: I H : current drawn when the gate output is HIGH () I L : current drawn when the gate output is LOW () 5

147 Therefore, the power dissipation for a gate with HIGH () output is: P D V I H When the gate is pulsed, with 5% duty cycle, the output will be 5% in HIGH () states and 5% in LOW () states. Therefore, the average supply current is: I I H I L and the average power dissipation is: P D(ave) V I Propagation Delay When signal passed through a gate, time delay will occurs. There are two types of time delay, t PHL and t PLH. (refer to chapter 5 in subtopic Flipflop characteristic). Speed Power Product As the name implies, it is the product of power and time. This parameter are used when both speed and power are critical aspect in selecting types of I for a design. The lower the speed power product value is better. Loading and Fan-Out When the output of a logic gates is connected to the input of one or more gates, a load will be created. The limit of how many gates can be connected is called the fan-out. MOS Loading: MOS are constructed from MOSFET that used a predominantly capacitive load to the driving gate (figure 8.). The more load gate are connected to the driving gate, the total capacitance will increase (because s effectively appear as parallel) thus reducing the maximum frequency the gate can operate (f max ) 6

148 Figure 8. apacitive loading of MOS gate + 5V HIGH I HARGE LOW I DISHARGE harging Discharging TTL Loading: A TTL driving gate source current to load gate input in HIGH () state and sinks current from the load gate in LOW () state. Figure 8. urrent sourcing and sinking of TTL gate + 5V HIGH I IH LOW I IL + 5V urrent Sourcing urrent Sinking As more load added, the total source current will increase, and the internal voltage drop of the driving gate will also increase. This will decrease the output voltage. If the output voltage drop below the V OH(min), the noise margin are reduce, thus compromising the circuit operation. Increasing load will also increase the power dissipation in the driving gate. The maximum number of load is called a unit load. As more load added, the total sinking current will increase, and the internal voltage drop of the driving gate will also increase. This will increase the V OL and if it exceeds the V OL(max), the noise margin are reduce, thus compromising the circuit operation. 7

149 8.3 MOSFETs The metal-oxide-semiconductor field-effect transistor (MOSFET), is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material and is accordingly called an NMOSFET or a PMOSFET (also commonly nmosfet, pmosfet, NMOS FET, PMOS FET, nmos FET, pmos FET). A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back into the same direction as the channel. Sometimes a broken line is used for enhancement mode and a solid one for depletion mode, but the awkwardness of drawing broken lines means this distinction is often ignored. Another line is drawn parallel to the channel for the gate. The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in. If the bulk is connected to the source (as is generally the case with discrete devices) it is angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in I design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS. omparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols: Figure 8.3 NMOS and PMOS symbol 8

150 n-hannel MOSFET transistors With no voltage between the gate terminal and the substrate, there are two junctions between the two n regions and the p region. This acts like two oppositely connected diodes, and no current can flow between the source and the drain. Application of a positive voltage between the gate terminal and the substrate creates an electric field that drives Holes out of the region under the gate, creating a channel of n-type material that connects the source and drain terminals. urrent is due to electron movement Tap analogy Sub-threshold, linear, and saturation regions of operation Standard notation that you will encounter includes supply voltage V DD, gate-to-source voltage V GS, drain-to-source voltage V DS, and threshold voltage V T Figure 8. NMOS structure and operation p-hannel MOSFET transistors The p and n regions are reversed from the n-hannel device. Application of a voltage on the gate terminal that is negative relative to the substrate creates a p channel beneath The gate and charge flow is due to hole movement. Figure 8.5 PMOS structure 9