COMPUTER ARCHITECTURE AND ORGANIZATION

Transcription

1 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING COMPUTER ARCHITECTURE AND ORGANIZATION (CSE18R174) LAB MANUAL Name of the Student:..... Register No Class Year/Sem/Class :. :. :... 1

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3 DEPARTMENT OF.. BONAFIDE CERTIFICATE Bonafide record of the work done by.... of.. in Computer Architecture and Organization (CSE17R174) during even/odd semester in academic year Staff in-charge Head of the Department Submitted to the Practical Examination held at KARE on Register Number INTERNA EXAMINER EXTERNAL EXAMINER 3

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5 INDEX Sl.no Experiment name Page Date of Experiment Study of peripherals, components of a 1. Computer System Date of submission Marks Sign Binary Addition Binary Multiplication Booth s Multiplication algorithm Restoring Division Non Restoring Division Algorithm Study of Logisim Tool. Realization of the basic logic and universal gates Design of half-adder circuit using basic gates. Design of full-adder circuit using basic gates. Ripple Carry adder Assignment Topics: 1. Carry look ahead adder 2. Design of a 4-bit parallel Binary adder circuit 3. Design of ALU 5

6 Name of the Subject : Computer Architecture and Organization/CSE17R252 Category : Integrated Course Objectives: The Objective is to expose the students to the various key aspects of Computer Organization & Architecture by enabling them to perform the experiments with support of a design and simulation in Logisim. Pre-requisites: 1. Basic knowledge regarding digital logic design & memory organization 2. Awareness regarding any simulation tool 3. Awareness regarding any programming language like C 4. Disciplined learning with positive attitude. Experiments Based: In this phase, the student needs to work out and execute the list of programs/experiments as decided by the instructor. These lists of programs/experiments must cover all the basics required to implement any project in the concerned course. This course will be undertaken through internal and external evaluation. *As part of Integrated Course, the work done should be assessed in each of the laboratory assessment to identify the capability of the student Hands on experience &Practical knowledge gained in the Lab as well as External Lab. Rubrics for Lab Experiments: Rubrics Poor Fair Good Excellent Implementation and Technical competence Production preparation handled ineffectively and are There is sufficient evidence of application of knowledge, skills and practical experience to ensure that artwork was mostly produced correctly. There is good evidence of application of knowledge, skills in the generation of files and practical experience to ensure that the work was produced efficiently to a good standard. There is excellent evidence of application of knowledge, skills and practical experience to ensure that the work was produced efficiently to a consistently high standard. Lab Performance Lab performance is not sufficient to pass since 80% of assignments were not completed (or unacceptable) Lab performance is fair with most assessments at the Adequate and Substandard levels. Lab performance is good with most assessments at the adequate level (with no more than 2 substandard) or above. Lab performance is excellent with the majority of assessments rated as proficient. Report quality Report is well organized and cohesive and contains no mechanical errors. Presentation seems polished. Report is well organized and cohesive but contains some spelling or grammatical errors Report is somewhat organized with some spelling or grammatical errors No attention to detail evident. 6

7 Experiment No: 1 Study of peripherals, components of a Computer System Aim: To Study of peripherals, components of a Computer System Question (1): What are the four basic functions that is performed by the computer? Question (2): Choose the correct answer? (a) The task of performing arithmetic and logical operation is performed by. (i) ALU (ii) Editor (iii) storage (iv) output (b) The ALU and CPU are jointly known as (i) RAM (ii) ROM (iii) CPU (iv) none of the above (c) The process of producing results from the data for getting useful information is called? Question (3): (i) Output (ii) input (iii) processing (iv) storage (a): List four input devices? (b): List four input devices?

8 Question (5): What is CPU and how does it work? Explain briefly? Question (6): What are the four basic functions performed by the computer? Question (2): Differentiate between the following: (a) RAM and ROM (b) DRAM and SRAM 8

9 Question (3): a. Distinguish between bit and byte? b. Define volatile and non-volatile memory? Question (4): Write True or False? (a) There are two kinds of computer memory: primary and secondary. (b) The computer can understand decimal system also. (c) The storage of program and data in the RAM is permanent. (d) PROM is secondary memory. (e) The memories which do not lose their content on failure of power Supplies are known as non-volatile memories True/False True/False True/False True/False True/False Result: Thus the study of peripherals, components of a computer was studied successfully. 9

10 Experiment No 2: Binary Addition Aim: To write C program for sum of two binary numbers Alogrithm: Program: 10

11 Result: Thus the Program for Binary addition was executed Successfully. 11

12 Experiment No: 3: Binary Multiplication Aim: To write a C program for multiplication of two binary numbers Algorithm: Program: 12

13 Result: Thus the Program for Binary multiplication was executed Successfully. 13

14 Experiment No: 4 Booth Multiplication AIM: Write a C program to implement Booth s algorithm for multiplication. THEORY: Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in notation.the Booth's algorithm serves two purposes: Fast multiplication (when there are consecutive 0's or 1's in the multiplier). And Signed multiplication. Booth's algorithm is a powerful direct algorithm to perform signed-number multiplication. The algorithm is based on the fact that any binary number can be represented by the sum and difference of other binary numbers. Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Booth's algorithm examines adjacent pairs of bits of the N-bit multiplier Y in signed two's complement representation, including an implicit bit below the least significant bit, y-1 = 0. For each bit yi, for I running from 0 to N-1, the bits yi and yi-1 are considered. Where these two bits are equal, the product accumulator P is left unchanged. Where yi = 0 and yi-1 = 1, the multiplicand times 2i is added top; and where yi = 1 and yi-1 = 0, the multiplicand times 2i is subtracted from P. The final value of P is the signed product. The representation of the multiplicand and product are not specified; typically, these are both also in two's complement representation, like the multiplier, but any number system that supports addition and subtraction will work as well. As stated here, the order of the steps is not determined. Typically, it proceeds from LSB to MSB, starting at i = 0; the multiplication by 2 i is then typically replaced by incremental shifting of the P accumulator to the right between steps; low bits can be shifted out, and subsequent additions and subtractions can then be done just on the highest N bits of P. There are many variations and optimizations on these details. The algorithm is often described as converting strings of 1's in the multiplier to a high-order +1 and a low-order 1 at the ends of the string. When a string runs through the MSB, there is no high- order +1, and the net effect is interpretation as a negative of the appropriate value. ALGORITHM: 14

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16 //Program for Booth's algorithm 16

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21 Result: Thus the program for Booth s multiplication is executed successfully. 21

22 Experiment No:5 Restoring Division Algorithm. AIM: Write a program to implement Restoring Division Algorithm. THEORY: Restoring division Restoring division operates on fixed-point fractional numbers and depends on the following assumptions: The following division methods are all based on the form Q = A/ M where ALGORITHM: Q = Quotient A = Numerator (dividend) M = Denominator (divisor). 22

23 //PROGRAM TO IMPLEMENT RESTORING DIVISION ALGORITHM 23

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29 Result: Thus the program for restoring division was successfully executed. 29

30 Experiment No:6 Non-Restoring Division Algorithm AIM: Write a C/C++ program for Non-Restoring Division Algorithm. THEORY: NON RESTORING DIVISION: In each cycle content of register A is first shifted and then divisor is added or subtracted with the content of register a depending upon the sign of A. In this there is no need of restoring, but if the remainder is negative then there is need of restoring the remainder. This is the faster algorithm of division. ALGORITHM: 30

31 //PROGRAM TO IMPLEMENT NON RESTORING DIVISION ALGORITHM 31

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37 Result: Thus the program for restoring division was successfully executed. 37

38 Experiment No: 7 Study of Logisim Tool Aim: To Study the Logisim Tool Introduction: Logisim allows you to design and simulate digital circuits. It is intended as an educational tool, to help you learn how circuits work. To practice using Logisim, let's build a XOR circuit - that is, a circuit that takes two inputs (which we'll call x and y) and outputs 0 if the inputs are the same and 1 if they are different. The following truth table illustrates. We might design such a circuit on paper. But just because it's on paper doesn't mean it's right. To verify our work, we'll draw it in Logisim and test it. Step 1: Adding gates Building a circuit is easiest by inserting the gates first as a sort of skeleton for connecting wires into the circuit later. The first thing we're going to do is to add the two AND gates. Click on the AND tool in the toolbar (, the next-to-last tool listed). Then click in the editing area where you want the AND gates to go. Be sure to leave plenty of room for stuff on the left. Notice the five dots on the left side of the AND gate. These are spots where wires can be attached. It happens that we'll just use two of them for our XOR circuit; but for other circuits, you may find that having more than two wires going to an AND gate is useful. 38

39 Now add the other gates. First click on the OR tool ( ( ) and put those two gates into the canvas. ); then click where you want it. And select the NOT tool I left a little space between the NOT gates and the AND gates; if you want to, though, you can put them up against each other and save yourself the effort of drawing a wire in later. Now we want to add the two inputs x and y into the diagram. Select the input pin ( ), and place the pins down. You should also place an output pin ( ) next to the OR gate's output. (Again, though I'm leaving a bit of space between the OR gate and the output pin, you might choose to place them right next to each other.) If you decide you don't like where you placed something, then you can right-click (or control-click) anything in the canvas to view a pop-up menu. Choose Delete. You can also rearrange things using the select tool ( ). Step 2: Adding wires After you have all the components blocked out on the canvas, you're ready to start adding wires. Select the wiring tool ( ). Then start dragging from one position to another in the canvas area, and a wire will start to appear between the two points. The wiring tool is pretty intelligent. Whenever a wire ends at another wire, Logisim automatically connects them. You can also "extend" or "shorten" a wire by dragging one of its endpoints using the wiring tool. Wires in Logisim must be horizontal or vertical. To connect the upper input to the NOT gate and the AND gate, then, I added three different wires. Logisim automatically connects wires to the gates and to each other. This includes automatically drawing the circle at a T intersection as above, indicating that the wires are connected. 39

40 As you draw wires, you may see some blue or gray wires. Blue in Logisim indicates that the value at that point is ``unknown'', and gray indicates that the wire is not connected to anything. This is not a big deal temporarily. But by the time you finish your circuit, none of your wires should be blue or gray. (The unconnected legs of the OR gate will still be blue: That's fine.) If you do have a blue or a gray wire after you think everything ought to be connected, then something is going wrong. It's important that you connect wires to the right places. Logisim draws little dots on the components to indicate where wires ought to connect. As you proceed, you'll see the dots turn from blue to light or dark green. Once you have all the wires connected, all of the wires you inserted will themselves be light or dark green. Step 3: Adding text Adding text to the circuit isn't necessary to make it work; then some labels help to communicate the purpose of the different pieces of your circuit. Select the text tool ( ). You can click on an input pin and start typing to give it a label. (It's better to click directly on the input pin than to click where you want the text to go, because then the label will move with the pin.) You can do the same for the output pin. Or you could just click any old place and start typing to put a label anywhere else. Step 4: Testing your circuit Our final step is to test our circuit to ensure that it really does what we intended. Logisim is already simulating the circuit. Let's look again at where we were. 40

41 Note that the input pins both contain 0s; and so does the output pin. This already tells us that the circuit already computes a 0 when both inputs are 0. Now to try another combination of inputs. Select the poke tool ( ) and start poking the inputs by clicking on them. Each time you poke an input, its value will toggle. For example, we might first poke the bottom input. When you change the input value, Logisim will show you what values travel down the wires by drawing them light green to indicate a 1 value or dark green (almost black) to indicate a 0 value. You can also see that the output value has changed to 1. So far, we have tested the first two rows of our truth table, and the outputs (0 and 1) match the desired outputs. By poking the switches through different combinations, we can verify the other two rows. If they all match, then we're done: The circuit works. Result: Thus the study of Logisim tool was studied successfully. 41

42 Experiment No:8 Realization of Logic Gates Aim: To realize the logic gates using Logisim tool. Introduction: A Logic Gate is assigned as an elementary building block of digital circuits. Logic gate is considered as a device which has the ability to produce one output level with the combinations of input levels. There are seven basic types of logic gates: By combining them in different ways, you will be able to implement all types of digital components. There are seven basic types of logic gates: AND GATE OR GATE NOT GATE NAND GATE NOR GATE EXCLUSIVE-OR GATE (X-OR) GATE EXCLUSIVE-NOR (X-NOR) GATE AND GATE An AND gate requires two or more inputs and produce only one output. The AND gate produces an output of logic 1 state when each of the inputs are at logic 1 state and also produces an output of logic 0 state even if any of its inputs are at logic 0 state. The symbol for AND operation is., or we use no symbol for representing. If the inputs are of X and Y, then the output can be expressed as Z=XY. OR GATE Similar to AND gate, an OR gate may also have two or more inputs but produce only one output. The OR gate produces an output of logic 1 state even if any of its inputs is in logic 1 state and also produces an output of logic 0 state if any of its inputs is in logic 0 state. The symbol for OR operation is +. If the inputs are of X and Y, then the output can be represented as Z=X+Y. An OR gate may also be defined as a device whose output is 1, even if one of its input is 1. OR gate is also called as any or all gate. 42

43 NOT GATE The NOT gate is also called as an inverter, simply because it changes the input to its opposite. The NOT gate is having only one input and one corresponding output. It is a device whose output is always the compliment of the given input. That means, the NOT gate produces an output of logic 1 state when the input is of logic 0 state and also produce the output of logic 0 state when the input is of logic 1 state. NAND GATE The NAND and NOR gates are the universal gates. Each of this gates can realize the logic circuits single handedly. The NAND and NOR are also called as universal building blocks. Both NAND and NOR has the ability to perform three basic logic functions such as AND,OR and NOT. NAND gate is a combination of an AND gate and a NOT gate. The expression for the NAND gate is whole bar. The output of the NAND gate is at logic 0 level only when each of the inputs assumes a logic 1 level. The truth table of two-input NAND gate is given below: NOR GATE NOR means NOT OR. That means, NOR gate is a combination of an OR gate and a NOT gate. The output is logic 1 level, only when each of its inputs assumes a logic 0 level. For any other combination of inputs, the output is a logic 0 level. The truth table of two-input NOR gate is given below: 43

44 EXCLUSIVE-OR GATE (X-OR) GATE An X-OR gate is a two input, one output logic circuit. X-OR gate assumes logic 1 state when any of its two inputs assumes a logic 1 state. When both the inputs assume the logic 0 state or when both the inputs assume the logic 1 state, the output assumes a logic 0 state. The output of the X-OR gate will be the sum of the modulo sum of its inputs. X-OR gate is also termed as anti-coincidence gate or inequality detector. An X-OR gate can also be used as inverter by connecting one of the two input terminals to logic1 and also by inputting the sequence to be inverted to the other terminal. EXCLUSIVE-NOR (X-NOR) GATE An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is also a two input, one output concept. The output of the X-NOR gate will be logic 1 state when both the inputs assume a 0 state or when both the inputs assume a 1 state. The output of the X-NOR gate will be logic 0 state when one of the inputs assume a 0 state and the other a 1 state. It is also named as coincidence gate, because its output will be 1 only when the inputs coincide. X-NOR gate can also be used as inverter by connecting one of the two input terminals to logic 0 and also by inputting the sequence to be inverted to the other terminal. 44

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47 Result: This the study of logic gates was successfully executed using logisim tool. 47

48 Experiment No:9 Design of Half-adder circuit Aim: To study and design half adder circuit THEORY: There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and the outputs are named as Sum (S) and Carry (C). The Sum is X-OR of the input A and B. Carry is AND of the input A and B. With the help of half adder, one can design a circuit that is capable of performing simple addition with the help of logic gates. Let us first take a look at the addition of single bits = = = = 10 These are the least possible single bit combinations. But the result for =10. This problem can be solved with the help of an EX OR gate. The sum results can be re-written as a 2-bit output. Thus the above combination can be written as = = = = 10 Here the output 1 of 10 becomes the carry-out. SUM is the normal output and the CARRY is the carry-out. From the truth table of the half adder we can see that the SUM (S) output is the result of the Exclusive-OR gate and the Carry-out (Cout) is the result of the AND gate. Then the Boolean expression for a half adder is as follows. For the SUM bit: SUM = A XOR B = A B For the CARRY bit: CARRY = A AND B = A.B The main disadvantage of this circuit is that it can only add two inputs and if there is any carry it is neglected. Thus, the process is incomplete. To overcome this difficulty Full Adder is designed. 48

49 Half Adder Circuit Result: Thus the study of Half adder circuit was completed successfully. 49

50 Experiment No: 10 Design of Full-adder circuit Aim: To study the Full Adder Circuit The full adder is a little more difficult to implement than a half adder. The main difference between a half adder and a full adder is that the full adder has three inputs and two outputs. The two inputs are A and B, and the third input is a carry input C IN. The output carry is designated as C OUT, and the normal output is designated as S. The output S is an EX OR between the input A and the half adder SUM output B. The COUT will be true only if any of the two inputs out of the three are HIGH or at logic 1. Then the Boolean expression for a full adder is as follows. For the SUM (S) bit: SUM = (A XOR B) XOR Cin = (A B) Cin For the CARRY-OUT (Cout) bit: CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A B) The addition of the four-bit number is shown below. 50

51 With the help of this type of symbol, one can add two bits together, taking a carry from the next lower order of magnitude and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add two 8 bit numbers, 8 full address is needed that can be formed by cascading two of the 4-bit blocks. Result: Thus the study of Half adder circuit was completed successfully. 51

52 Experiment No:11 Design of Ripple -adder circuit Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a C in, which is the C out of the previous adder. This kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder. The block diagram of 4-bit Ripple Carry Adder is shown here below - The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry propagation) + 3(for sum) = 65 gate delays. 52

53 Result: Thus the Ripple Carry adder circuit was designed and executed successfully. 53

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