Abstract. 1. Introduction. Department of Electronics and Communication Engineering Coimbatore Institute of Engineering and Technology

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1 IMPLEMENTATION OF BOOTH MULTIPLIER AND MODIFIED BOOTH MULTIPLIER Sakthivel.B 1, K. Maheshwari 2, J. Manojprabakar 3, S.Nandhini 4, A.Saravanapriya 5 1 Assistant Professor, 2,3,4,5 Student Members Department of Electronics and Communication Engineering Coimbatore Institute of Engineering and Technology Abstract This paper describes implement of 8-bit Modified Booth Multiplier and this Implementation is compared with 4-bit Booth Multiplier. Modified Booth s algorithm employs both addition and subtraction and also treats positive and negative operands uniformly. No special actions are required for negative numbers. In this Paper, we investigate the method of implementing the parallel MAC with the smallest possible delay. Parallel MAC is frequently used in digital signal processing and video/graphics applications. A new architecture of multiplier and accumulator(mac) for high speed arithmetic by combining multiplication with accumulation. Modified Booth multiplication algorithm is designed using high speed adder. High speed adder is used to speed up the operation of multiplication. 1. Introduction Multipliers are key components of many high performance systems such as FIR filters, Microprocessor, Digital signal processors, etc. Signed multiplication is a careful process. With unsigned multiplication there is no need to take the sign of the number into consideration. However in signed multiplication the same process cannot be applied because the signed number is in a 2 s compliment form which would yield an incorrect result if multiplied in a similar fashion to unsigned multiplication. That s where Booth s algorithm comes in. Booth s algorithm preserves the sign of the result. Booth algorithm is also used for high speed multiplication as high speed digital multipliers find application in many digital signal processing. Digital multipliers are also utilized in other digital signal processors, such as radar and sonar. In many applications, processing of analog signals in digital form in real time would not be practical without high speed digital multipliers. Other applications include fast fourier transform processors and high speed floating point arithmetic logic units. Booth multiplier reduces number of iteration step to perform multiplication as compare to conventional steps. Booth algorithm scans the multiplier operand and skips chains of this algorithm can reduce the number of additions required to produce the result compared to conventional All Rights Reserved 45

2 algorithm., where each bit of the multiplier is multiplied with the multiplicand and the partial 2.Booth Multiplier Booth s Multiplication Algorithm is a Multiplication algorithm that multiplies two signed binary numbers in two s complement notation. The algorithm was invented by Andrew Donald Booth in 1950 while doing research on crystallography at Birkbeck college in Bloomsbury, London. Booth used desk calculators that were faster at shifting than adding and created the algorithm to increase their speed. Booth s algorithm is of interest in the study of computer architecture. Booth Algorithm Booth s algorithm examines adjacent pairs of bits of the N-bits multiplier Y in signed two s complement representation, including in implicit bit below the least significant bit,y - 1=0.For each bit yi, for i running from 0 to N- products are aligned and added together 1,the bits yi and yi-1 are considered. Where these two bits are equal, the product accumulator P is left unchanged. Where yi=0 and yi-1=1, the multiplicand times 2 i is added to P; and where yi=1 and yi-1=0, the multiplicand times 2 i is subtracted from P. The final value of P is the signed product. The representation of multiplicand and product are not specified; typically, these are both also in two s complement representation, like the multiplier, but any number system that support addition and subtraction will work as well. As stated here, the order of the steps is not determined. Typically, it proceeds from LSB to MSB, starting at i= 0; the multiplicand by 2 i is then typically replaced by incremental shifting of the P accumulator to the right between steps; low bits can be shifted out, and subsequent additions and subractions can then be done just on the highest N bits of P [1]. There are many variations and optimizations on these details. The algorithm is often describes as converting strings 1s in the multiplier to a highorder +1 and a low-order -1 at the ends of the string. When a string runs through the MSB, there is no high-order +1, and the net effect is interpretation as a negative of the appropriate All Rights Reserved 46

3 Booth s algorithm can be implemented by repeatedly adding (with ordinary unsigned binary addition) one of the predetermined values A and S to a product P, then performing a rightward arithmetic shift on A. Let m and r be the multiplicand and multiplier, respectively; and x and y represent the number of bits in m and r. III.P: Fill the most significant x bits with zeros. To the right of this, append the value of r. Fill the least significant (rightmost) bit with a zero. 2.Determine the two least significant (rightmost) bits of P. I.If they are 01, find the value of P+A. Ignore any overflow. II.If they are 10,find the values P+S. Ignore any overflow. III.If they are 00, do nothing. Use P directly in the next step. IV.If they are 11,do nothing. Use P directly in the next step. 3.Arithmatically shift the value obtained in the 2 nd step by a single place to the right. Let now equal this new value. 1.Determine the values of A and S, and the initial value of P. All of these numbers should have a length equal to (x+y+1). I.A:Fill the most significant(leftmost) bits with the values of m. Fill the remaining (y+1). Bits with zero. II.S: Fill the most significant bits with the values of(-m) in two s complement notation. Fill the remaining (y+1) bits with zero. 4.Repeat steps 2 and 3 until they have been done y times. 5.Drop the least significant (rightmost) bit from P. This product of m and r. Example Find 3*(-4), with m=3 and r=-4, and x=4 and y=4: 1.m= 0011,-m =1101,r= A= S= All Rights Reserved 47

4 4. P= Perform the loop four time: (i). P= The last two bits are 00. P= Arithmatic right shift. (ii). P= The last two bits are 00. P= Arithmatic right shift. (iii). P= The last two bits are 10. P= (P=P+S). P= (Arithmatic right shift) (iv). P= The last two bits are 11. P= ( Arithmatic right shift) (v). The product is , which is Modified Booth Algorithm Booth multiplication algorithm consists of three major steps as shown in structure of Booth algorithm figure that includes generation of partial product called as recoding, reducing the partial product in two rows, and addition that gives final product. modified Booth algorithm & for multiplication, we must know about each block of Booth algorithm for multiplication process. + (or ) - 1,+ (or) -2,or 0,to obtain the same results.radix-4 Booth encoder performs the process of encoding the multiplicand based on multiplier bits. It will compare 3 bits at a time with overlapping technique. Grouping starts from the LSB, and the first block only uses two bits of the multiplier and assumes a zero for the third bit. Radix-4 Booth algorithm is given below: 1. Extend the sign bit 1 position if necessary to ensure that n is even. 2. Append a 0 to the right of the LSB of the multiplier. 3. According to the value of each vector, each partial product will0,+y,y,+2y,-2y. Example 13*(-6) 13=01101=> =0110 => (-6)=1010=> It is possible to reduce the number partial products by half, by using the technique of radix-4 Booth recoding. The basic idea is that, instead of shifting and adding for every column of multiplier term and multiplying by 1 or 0, we only take every second column, and multiply All Rights Reserved 48

5 Bit position i+1 I i Operation 0*M 1*M 1*M 2*M -2*M -1*M Comment A Q Q_1 SC=n/2-2*M Arithmatic Right Shift times *M Arithmatic Right Shift 2 times *M Arithmatic *M right shift 2 times 0 1 All Rights Reserved 49

6 5.Exprimental Work After analysing the two Booth Multipliers, and compare their characteristics in terms of multiplication speed, no of computation required no of hardware, we come on finding that 4-bit Booth Multipliers is better than 4-bit Booth Multipliers. By implementing both 4-bit and 4- bit multiplier we analysis that 4-bit multiplier computation speed is higher then Radix-2. We have done the coding of both multiplier separately in VHDL and simulate it to get the accurate waveforms as output each multiplier. Also get the device utilization summary, Where we get the exact no of input,output, no of slices requirement etc. for the multiplier. In radix- 4design simulation result is same as Radix-2 scheme. Only difference between these two schemes is synthesis report. 4-bit Booth Multipliers and 4-bit modified Booth multipliers are implemented here; the complete process of theimplementation is giving higher speed of operation. The Speed and circuit complexity is compared,8-bit Booth multiplier is giving higher speed as compared to 4-bit Booth Multiplier and Circuit complexity is also less as compared to it. References: [1]. Hsin- Lei Lin, Robert C. Chang, Ming- Tsai Chan (2004), Design Of A Novel Radix- 4 Booth Multiplier, IEEE Asia Pacific Conference On Circuits And Systems, Vol.2, pp [2]. H.Lee, A High speed Booth Multiplier, ICCs,(2002). [3]. M.Sheplie (2004), High performance array multiplier, IEEE transactions on very large scale integration systems, vol. 12,no. 3, pp [4]. Robert C. Ghest, Saratoga; Hua- Thye Chua, Cupetino; John M. Brikner,Santa Clara, (1979) High Speed Combinatorial digital multiplier, United States Patent, US A 6.SimulationResults [5]. Vincent P. Heuring, Harry.F. Jordon (2003), Computer Systems Design and Architecture, Perason Education, All Rights Reserved 50

7 [6]. Y.N. Ching (2005), Low-power high speed multipliers, IEEE Transactions on Computers, vol. 54,no. 3, pp , International Journal of Recent Trends in Engineering & Research All Rights Reserved 51

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