Digital Fundamentals

Transcription

1 Digital Fundamentals Tenth Edition Floyd Chapter 6 组合逻辑电路函数 Floyd, Digital Fundamentals, th ed 29 Pearson Education, Upper 28 Pearson Saddle River, Education NJ All Rights Reserved

2 Summary Half-Adder 半加器 Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). The inputs and outputs can be summarized on a truth table. Inputs Outputs A B C out S The logic symbol and equivalent circuit are: A B S S C out A B S C out = AB + A B = A B C out =AB Floyd, Digital Fundamentals, th ed

3 Summary n-bit Addition? The addition of two n-bit binary numbers generates a n-bit sum and a carry out. Example: let n = 4 C out C 3 C 2 C C A 3 A 2 A A + B 3 B 2 B B S 3 S 2 S S + Floyd, Digital Fundamentals, th ed

4 Summary Full-Adder By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. C out = AB + A BC in + AB C in = AB + (A B)C in = AB C in + A B C in + A BC in +ABC in Inputs Outputs A B C in C out S = A B C in BC in A BC in A Floyd, Digital Fundamentals, th ed

5 Summary Full-Adder C out = AB + (A B)C in = A B C in A full-adder can be constructed from two half adders as shown: A B A B C in S S C out A B S Observe C out S C out Sum Inputs Outputs A B C in C A B C in S S C out out S C out Symbol Floyd, Digital Fundamentals, th ed

6 Summary Full-Adder A S S A S S Sum For the given inputs, determine the intermediate and final outputs of the full adder. B C out B C out The first half-adder has inputs of and ; therefore the Sum = and the Carry out =. The second half-adder has inputs of and ; therefore the Sum = and the Carry out =. The OR gate has inputs of and, therefore the final carry out =. C out Floyd, Digital Fundamentals, th ed

7 Summary Full-Adder Notice that the result from the previous example can be read directly on the truth table for a full adder. Inputs Outputs A B C in C out S A B S S C out S A S B C out Sum C out Floyd, Digital Fundamentals, th ed

8 Summary n-bit Combinational Adders Perform parallel multi-bit addition Parallel Adders ( 并行加法器,also called Ripple Carry Adder, 串行加法器 ) Simple design Time consuming. Carry Look ahead Adder ( 先行进位加法器 ) More complex than Parallel Adders Reduces circuit delay Floyd, Digital Fundamentals, th ed

9 Parallel Adders 并行加法器 Summary Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. A 4 B 4 A 3 B 3 A 2 B 2 A B C A B C in A B C in A B C in A B C in C out S C out S C out S C out S C 4 C 3 S 4 C S 3 C 2 S 2 S The output carry (C 4 ) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process. Floyd, Digital Fundamentals, th ed

10 Summary 6.3 Carry Look ahead Adder( 先行进位加法器 ) One method of speeding up the addition process by eliminating this ripple carry delay is called lookahead carry addition. Consider:C i+ = A i B i + (A i B i ) C i Carry generation( 进位产生 ): Let G i = A i B i =,if G i =,then C i+ = Carry propagation( 进位传递 ): Let P i = A i B i,if P i =,then C i+ =C i Floyd, Digital Fundamentals, th ed

11 Summary Carry Look ahead Adder( 先行进位加法器 ) HA HA PARTIAL FULL ADDER(PFA) Can this connection eliminate the ripple carry delay Floyd, Digital Fundamentals, th ed

12 Summary A 4-bit Carry Look ahead Adder C i+ = G i + P i C i Base on this ayalysis: C = G +P C C 2 = G +P C = G +P (G +P C ) = G +P G +P P C C 3 = G 2 + P 2 C 2 = G 2 +P 2 G +P 2 P G +P 2 P P C C 4 = G 3 +P 3 G 2 +P 3 P 2 G +P 3 P 2 P G + P 3 P 2 P P C Carry generation( 进位产生 ) Carry propagation( 进位传递 ) Now the ripple problem is solved. Floyd, Digital Fundamentals, th ed

13 A 4-bit Carry Look ahead Adder C i :2 gate delays. C 4 G 3 P 3 C 3 G 2 P 2 C 2 G P C G P C Floyd, Digital Fundamentals, th ed

14 A 4-bit Carry Look ahead Adder Logic diagram for a 4-stage look-ahead carry adder Floyd, Digital Fundamentals, th ed

15 Summary A 4-bit Adders The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C ) and a Carry out (labeled C 4 ). Binary number A Binary number B Input carry S C C 4 4-bit sum Output carry The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 7 ns. Floyd, Digital Fundamentals, th ed

16 An application: a voting system Floyd, Digital Fundamentals, th ed

17 An application: Cascading four 74LS283 four-bit adders to form 6bit adder Floyd, Digital Fundamentals, th ed

18 An application:subtractor Using 2 s complement to realize subtraction Input data Difference Borrow Why c-in always be. Floyd, Digital Fundamentals, th ed

19 An application:an adder/subtractor circuit. A /S is the mode control. How does it work? When the A /S mode control input is a the EX-OR gates do not invert, so the input data are added unchanged. The carry-in bit is forced to logic. 4-bit Adder 4-bit Adder 9-bit Result Floyd, Digital Fundamentals, th ed

20 An application:a BCD to Excess-3 code converter BCD Input Excess-3 output Floyd, Digital Fundamentals, th ed

21 An application:bcd Adder BCD Decimal Adder: Requires 8 inputs (4 bits per decimal number) 5 outputs indicate the decimal sum and the carry Remember BCD addition rules: Add to the sum if it is greater than to correct the carry bit e.g.:let A=,B= The BCD sum of A+B is () + + Floyd, Digital Fundamentals, th ed

22 BCD Inputs 4-bit Adder From lower order BCD digits. To higher order BCD digits. 4-bit Adder BCD Result Floyd, Digital Fundamentals, th ed

23 Summary 6.4 Comparators The function of a comparator is to compare the magnitudes of two binary numbers to determine the relationship between them. Single bit comparator A EQ B = A B + AB A > B = AB A< B = A B A B A=B A>B A<B How about Two-bit comparator? Floyd, Digital Fundamentals, th ed

24 In order to compare binary numbers containing two bits each, an additional exclusive- NOR gate is necessary. The two least significant bits (LSBs) of the two numbers are compared by gate G, and the two most significant bits (MSBs) are compared by gate G2, as shown in Figure 6 9. If the two numbers are equal, their corresponding bits are the same, and the output of each exclusive-nor gate is a. If the corresponding sets of bits are not equal, a occurs on that exclusive-nor gate output. Figure 6.2 Logic diagram for equality comparison of two 2-bit numbers Floyd, Digital Fundamentals, th ed

25 EXAMPLE 6 5 Apply each of the following sets of binary numbers to the comparator inputs in Figure 6 2, and determine the output by following the logic levels through the circuit. (a) and (b) and Figure 6.2 InfoNote In a computer, the cache is a very fast intermediate memory between the central processing unit (CPU) and the slower main memory. The CPU requests data by sending out its address (unique location) in memory. Part of this address is called a tag. The tag address comparator compares the tag from the CPU with the tag from the cache directory. If the two agree, the addressed data is already in the cache and is retrieved very quickly. If the tags disagree, the data must be retrieved from the main memory at a much slower rate. Floyd, Digital Fundamentals, th ed

26 Summary Comparators IC comparators provide outputs to indicate which of the numbers is larger or if they are equal. The bits are numbered starting at, rather than as in the case of adders. Cascading inputs are provided to expand the comparator to larger numbers. A A A 2 A 3 Cascading inputs B B B 2 B 3 COMP A 3 A > B A > B A = B A = B A < B A < B A 3 Outputs The IC shown is the 4-bit 74LS85. Floyd, Digital Fundamentals, th ed

27 Summary Comparators IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input. LSBs MSBs +5. V A A A 2 A 3 B B B 2 B 3 COMP A 3 A > B A > B A = B A = B A < B A < B A 3 A 4 A 5 A 6 A 7 B 4 B 5 B 6 B 7 COMP A 3 A > B A > B A = B A = B A < B A < B A 3 Outputs Floyd, Digital Fundamentals, th ed

28 6.5 Decoders ( 译码器 ) Summary A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence of the binary code are shown. The first has an active HIGH output; the second has an active LOW output. A A X A A X A 2 A 2 A 3 A 3 Active HIGH decoder for Active LOW decoder for Floyd, Digital Fundamentals, th ed

29 Summary Decoders Assume the output of the decoder shown is a logic. What are the inputs to the decoder? A = A = A 2 = A 3 = Floyd, Digital Fundamentals, th ed

30 Decoders Floyd, Digital Fundamentals, th ed

31 Decoders Summary IC decoders have multiple outputs to decode any combination of inputs. For example the binary-to-decimal decoder shown here has 6 outputs one for each combination of binary inputs. For the input shown, what is the output? 4-bit binary input A A A 2 A 3 Bin/Dec Decimal outputs Floyd, Digital Fundamentals, th ed

32 Decoders Summary A specific integrated circuit decoder is the 74HC54 (shown as a 4-to-6 decoder). It includes two active LOW chip select lines which must be at the active level to enable the outputs. These lines can be used to expand the decoder to larger inputs. A A A 2 A 3 CS CS & X/Y EN HC54 Floyd, Digital Fundamentals, th ed

33 Decoders Summary A 5-bit decoder using 74HC54s Floyd, Digital Fundamentals, th ed

34 Decoders* Summary The 74LS38 is a 3-to-8 decoder with three chip select inputs (two active LOW, one active HIGH). In this Multisim circuit, the word generator (XWG) is set up as an up counter. The logic analyzer (XLA) compares the input and outputs of the decoder. Inputs are blue, outputs are red. Floyd, Digital Fundamentals, th ed

35 Summary Decoders* How will the waveforms change if the word generator is configured as a down counter instead of an up counter? Inputs are blue, outputs are red. Floyd, Digital Fundamentals, th ed

36 Decoders* Summary The chip select inputs can be used to expand a decoder. In this circuit, two 74LS38s are configured as a 6 line decoder. Notice how the MSB is connected to one active LOW and one active HIGH chip select. The next slide shows the logic analyzer output Floyd, Digital Fundamentals, th ed

37 Summary Decoders* Is the word generator set as an up counter or a down counter? (The least significant decoder output at the top). It is an up counter. Floyd, Digital Fundamentals, th ed

38 Decoders Summary BCD-to-decimal decoders accept a binary coded decimal input and activate one of ten possible decimal digit indications. A A A 2 A 3 Assume the inputs to the 74HC42 decoder are the sequence,,, and. Describe the output. (5) (4) (3) (2) BCD/DEC 74HC () (2) (3) (4) (5) (6) (7) (9) () () All lines are HIGH except for one active output, which is LOW. The active outputs are 5, 6, 3, and 2 in that order. Floyd, Digital Fundamentals, th ed

39 BCD Decoder/Driver Summary Another useful decoder is the 74LS47. This is a BCD-toseven segment display with active LOW outputs. V CC (6) The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BCD inputs LT RBI (7) () (2) (6) (3) (5) BCD/7-seg LT RBI BI/RBO a b c d e f g (4) (3) (2) () () (9) (5) (4) BI/RBO Outputs to seven segment device 74LS47 (8) GND Floyd, Digital Fundamentals, th ed

40 BCD Decoder/Driver Summary Here the 7447A is an connected to an LED seven segment display. Notice the current limiting resistors, required to prevent overdriving the LED display. BCD input. kw +5. V 74LS47 6 BCD/7-seg V CC LT BI/RBO RBI A B C D GND R's = 33 W 3 a 3 4 b c 6 d 8 2 e 9 7 f g 4 8 a b c d e f g +5. V MAN72 3, 9, 4 Floyd, Digital Fundamentals, th ed

41 BCD Decoder/Driver Summary The 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBI input of the next decoder. RBI LT RBI LT RBI LT RBI LT LS47 74LS47 74LS47 74LS47 g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO Blanked Blanked Depending on the display type, current limiting resistors may be required. Floyd, Digital Fundamentals, th ed

42 BCD Decoder/Driver Summary Trailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBI input is connected to the BI/RBO output of the following decoder. RBI LT RBI LT RBI LT RBI LT LS47 74LS47 74LS47 74LS47 g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO Decimal point Blanked Blanked Floyd, Digital Fundamentals, th ed

43 Implementing Boolean functions using decoders use 74HC54 to implement F(A, B, C, D) = Sm(,2,5,7) & & Floyd, Digital Fundamentals, th ed

44 6.6 Encoders( 编码器 ) Summary An encoder accepts an active logic level on one of its inputs and converts it to a coded output, such as BCD or binary. The decimal to BCD is an encoder with an input for each of the ten decimal digits and four outputs that represent the BCD code for the active digit. The basic logic diagram is shown. There is no zero input because the outputs are all LOW when the input is zero A A A 2 A 3 Floyd, Digital Fundamentals, th ed

45 Summary Encoders Show how the decimal-to-bcd encoder converts the decimal number 3 into a BCD. The top two OR gates have ones as indicated with the red lines. Thus the output is. 2 3 A A A 2 9 A 3 Floyd, Digital Fundamentals, th ed

46 Summary Encoders The 74HC47 is an example of an IC encoder. It is has ten active-low inputs and converts the active input to an V active-low BCD output. CC This device is offers additional flexibility in that it is a priority encoder( 优先编码器 ). This means that if more than one input is active, the one with the highest order decimal digit will be active. Decimal input () (2) (3) () (2) (3) (4) (5) () (6) HPRI/BCD (9) (7) (6) (4) BCD output 74HC47 (8) GND Floyd, Digital Fundamentals, th ed

47 Encoders V CC R 7 R 8 R 9 Summary Keyboard encoder HPRI/BCD 4 R 4 R 5 R BCD complement of key press R R 2 R 3 74HC R The zero line is not needed by the encoder, but may be used by other circuits to detect a key press. Floyd, Digital Fundamentals, th ed

48 Priority Encoders( 优先编码器 ). e.g. The truth table of a 4-2 priority encoders. input output D 3 D 2 D D A A V X X X X X X X X Floyd, Digital Fundamentals, th ed

49 Priority Encoders( 优先编码器 ). Floyd, Digital Fundamentals, th ed

50 Summary 6.7 Code converters( 代码转换器 ) There are various code converters that change one code to another. Two examples are the four bit binary-to-gray converter and the Gray-to-binary converter. Show the conversion of binary to Gray and back. LSB LSB MSB MSB Binary-to-Gray Gray-to-Binary Floyd, Digital Fundamentals, th ed

51 Multiplexers( 数字多路器 ) Summary A multiplexer (MUX) selects one data line from two or more input lines and routes data from the selected line to the output. The particular data line that is selected is determined by the select inputs. For a 2 n -to- multiplexer, there are 2 n data input lines and n selection lines whose bit combination determines which input is selected. 4- Multiplexer needs 2 selection lines. 8- Multiplexer needs 2 selection lines. Floyd, Digital Fundamentals, th ed

52 Multiplexers( 数字多路器 ) Summary Floyd, Digital Fundamentals, th ed

53 Summary 4- Multiplexer(4- 多路器 ) S S Y D D D 2 D 3 Y=S S D +S S D +S S D 2 +S S D 3 = m i D i Floyd, Digital Fundamentals, th ed

54 Multiplexers( 数字多路器 ) Summary Two select lines are shown here to choose any of the four data inputs. Which data line is selected if S S =? D 2 Data select Data inputs S S D D D 2 D MUX Data output Floyd, Digital Fundamentals, th ed

55 Multiplexer Expansions( 多路器扩展 ) Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words? Combine MUX blocks in parallel with common select and enable signals Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution). Floyd, Digital Fundamentals, th ed

56 Example: Quad 2-to- MUX Uses four 2-to- MUXs with common select (S) and enable (E). Select line chooses between A i s and B i s. The selected fourwire digital signal is sent to the Y i s Enable line turns MUX on and off (E= is on). Floyd, Digital Fundamentals, th ed

57 Multiplexer Expansions( 多路器扩展 ) A 6-input multiplexer Floyd, Digital Fundamentals, th ed

58 A 7-Segment Display Multiplexer Figure 6 52 shows a simplified method of multiplexing BCD numbers to a 7-segment display The basic operation is as follows. Two BCD digits (A3A2AA and B3B2BB) are applied to the multiplexer inputs. A square wave is applied to the data-select line, and when it is LOW, the A bits (A3A2AA) are passed through to the inputs of the 74HC47 BCD-to-7- segment decoder. The LOW on the data-select also puts a LOW on the A input of the 74HC39 2-line-to-4- line decoder, thus activating its output and enabling the A-digit display by effectively connecting its common terminal to ground. The A digit is now on and the B digit is off. When the data-select line goes HIGH, the B bits (B3B2BB) are passed through to the inputs of the BCD-to-7-segment decoder. Also, the 74HC39 decoder s output is activated, thus enabling the B- digit display. The B digit is now on and the A digit is off. The cycle repeats at the frequency of the data-select square wave. This frequency must be high enough to prevent visual flicker as the digit displays are multiplexed. Floyd, Digital Fundamentals, th ed Figure 6.52 Simplified 7-segment display multiplexing logic.

59 Implementing Boolean functions with Multiplexers E.g. Using an 8-to- multiplexer to realize the Boolean function F=f(x,y,z)= (,2,4,5,7) Y= C B A D + C B AD + C BA D 2 +C BAD 3 + CB A D 4 + CB AD 5 + CBA D 6 + CBAD 7 i=2 n - = m i D i i= F=f(x,y,z)= (,2,4,5,7) =x y z+x yz +xy z +xy z+xyz C=x,B=y,A=z D =D 3 =D 6 = D = D 2 = D 4 = D 5 = D 7 = Floyd, Digital Fundamentals, th ed

60 Summary 6.9 Demultiplexers( 多路分配器 ) A demultiplexer (DEMUX) performs the opposite function from a MUX. It switches data from one input line to two or more data lines depending on the select inputs. The 74LS38(3-8 译码器 ) was introduced previously as a decoder but can also serve as a DEMUX. When connected as a DEMUX, data is applied to one of the enable inputs, and routed to the selected output line depending on the select variables. Note that the outputs are active-low as illustrated in the following example Data select lines Enable inputs A A A DEMUX 2 G G G 2A 2B 74LS38 Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Data outputs Floyd, Digital Fundamentals, th ed

61 Demultiplexers Summary Determine the outputs, given the inputs shown. The output logic is opposite to the input because of the active-low convention. (Red shows the selected line). Data select lines Enable inputs A A A DEMUX 2 G G G 2A 2B 74LS38 Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Data outputs A A A 2 G G 2A LOW G 2B LOW Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Floyd, Digital Fundamentals, th ed

62 Summary Parity Generators/Checkers( 奇偶发生器 / 校验器 ) Parity is an error detection method that uses an extra bit appended to a group of bits to force them to be either odd or even. In even parity, the total number of ones is even; in odd parity the total number of ones is odd. The ASCII letter S is. Show the parity bit for the letter S with odd and even parity. S with odd parity = S with even parity = Floyd, Digital Fundamentals, th ed

63 Summary Parity Generators/Checkers The 74LS28 can be used to generate a parity bit or to check an incoming data stream for even or odd parity. Checker: The 74LS28 can test codes with up to 9 bits. The even output will normally be HIGH if the data lines have even parity; otherwise it will be LOW. Likewise, the odd output will normally be HIGH if the data lines have odd parity; otherwise it will be LOW. Generator: To generate even parity, the parity bit is taken from the odd parity output. To generate odd parity, the output is taken from the even parity output. Data inputs (8) (9) () () (2) (3) () (2) (4) A B C D E F G H I 74LS28 (5) (6) S Even S Odd Floyd, Digital Fundamentals, th ed

64 Selected Key Terms Full-adder Cascading Ripple carry Look-ahead carry A digital circuit that adds two bits and an input carry bit to produce a sum and an output carry. Connecting two or more similar devices in a manner that expands the capability of one device. A method of binary addition in which the output carry from each adder becomes the input carry of the next higher order adder. A method of binary addition whereby carries from the preceding adder stages are anticipated, thus eliminating carry propagation delays. Floyd, Digital Fundamentals, th ed

65 Selected Key Terms Decoder Encoder A digital circuit that converts coded information into a familiar or noncoded form. A digital circuit that converts information into a coded form. Priority encoder Multiplexer (MUX) Demultiplexer (DEMUX) Floyd, Digital Fundamentals, th ed An encoder in which only the highest value input digit is encoded and any other active input is ignored. A circuit that switches digital data from several input lines onto a single output line in a specified time sequence. A circuit that switches digital data from one input line onto a several output lines in a specified time sequence.

66 Homework 判断题 自测题 :( 自愿完成 ) 节 : 节 : 节 : 节 : Floyd, Digital Fundamentals, th ed

67 C. For the full-adder shown, assume the input bits are as shown with A =, B =, C in =. The Sum and C out will be a. Sum = C out = b. Sum = C out = A S S A S S Sum c. Sum = C out = B C out B C out d. Sum = C out = C out Floyd, Digital Fundamentals, th ed 28 Pearson Education

68 C 2. The output will be LOW if a. A < B b. A > B c. both a and b are correct d. A = B A B A 2 B 2 A 3 B 3 A 4 B 4 Output Floyd, Digital Fundamentals, th ed 28 Pearson Education

69 3. If you expand two 4-bit comparators to accept two 8-bit numbers, the output of the least significant comparator is a. equal to the final output b. connected to the cascading inputs of the most significant comparator c. connected to the output of the most significant comparator d. not used B Floyd, Digital Fundamentals, th ed 28 Pearson Education

70 C 4. Assume you want to decode the binary number with an active-low decoder. The missing gate should be a. an AND gate b. an OR gate A A? X c. a NAND gate A 2 d. a NOR gate A 3 Floyd, Digital Fundamentals, th ed 28 Pearson Education

71 A 5. Assume you want to decode the binary number with an active-high decoder. The missing gate should be a. an AND gate b. an OR gate A A? X c. a NAND gate A 2 d. a NOR gate A 3 Floyd, Digital Fundamentals, th ed 28 Pearson Education

72 D 6. The 7438 is a 3-to-8 decoder. Together, two of these ICs can be used to form one 4-to-6 decoder. To do this, connect a. one decoder to the LSBs of the input; the other decoder to the MSBs of the input b. all chip select lines to ground c. all chip select lines to their active levels d. one chip select line on each decoder to the input MSB Floyd, Digital Fundamentals, th ed 28 Pearson Education

73 A 7. The decimal-to-binary encoder shown does not have a zero input. This is because a. when zero is the input, all lines should be LOW b. zero is not important c. zero will produce illegal logic levels d. another encoder is used for zero A A A 2 A 3 Floyd, Digital Fundamentals, th ed 28 Pearson Education

74 D 8. If the data select lines of the MUX are S S =, the output will be a. LOW b. HIGH Data select S S MUX c. equal to D d. equal to D 3 Data inputs D D D 2 D Data output Floyd, Digital Fundamentals, th ed 28 Pearson Education

75 B 9. The 7438 decoder can also be used as a. an encoder b. a DEMUX c. a MUX d. none of the above Floyd, Digital Fundamentals, th ed 28 Pearson Education

76 B. The 74LS28 can generate even or odd parity. It can also be used as a. an adder b. a parity tester c. a MUX d. an encoder Floyd, Digital Fundamentals, th ed 28 Pearson Education

77 Answers:. c 6. d 2. c 7. a 3. b 8. d 4. c 9. b 5. a. b Floyd, Digital Fundamentals, th ed