Chapter 3 Combinational Logic Design
|
|
- Stephany Antonia Richards
- 5 years ago
- Views:
Transcription
1 Logic and Computer Design Fundamentals Chapter 3 Combinational Logic Design Part 2 Combinational Logic
2 Overview Part -Implementation Technology and Logic Design Design Concepts Fundamental concepts of design Design Procedure The major design steps: specification, formulation, optimization, technology mapping, and verification Technology Mapping From AND, OR, and NOT to other gate types Verification Does the designed circuit meet the specifications? Chapter 3-p2 IT32 2
3 Overview Part 2 Combinational Logic Functions and functional blocks Rudimentary logic functions Decoding Encoding Selecting Chapter 3-p2 IT32 3
4 Functions and Functional Blocks The functions considered are those found to be very useful in design. Corresponding to each of the functions is a combinational circuit implementation called a functional block. In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. Today, they are often simply parts within a VLSI circuits. Chapter 3-p2 IT32 4
5 Rudimentary Logic Functions Value fixing, transferring, inverting and enabling are the most elementary of combinational logic functions. Can be used on the inputs to functional blocks to implement other than the block s intended function Chapter 3-p2 IT32 5
6 Value fixing, transferring, and inverting functions Functions of a single variable X X F = F = X F = X F = V CC V DD F = F = X (c) F = X F = F = X F = X (a) (b) (d) Chapter 3-p2 IT32 6
7 Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be, or Hi-Z (as for three-state buffers). a) When disabled, output b) When disabled, output X EN (a) F EN X F Chapter 3-p2 IT32 7 (b)
8 Decoders Convert binary information from n input lines to (max. of) 2 n output lines. Known as n-to-m-line decoder, or simply n:m or nxm decoder (m <= 2 n ). A n-to- 2 n decoder uses its n-bit input to determine which of 2 n outputs will be uniquely activated. Generate 2 n (or fewer) minterms of n input variables. Chapter 3-p2 IT32 8
9 Decoders Example: if codes,,, are used to identify four light bulbs, we may use a 2-bit decoder: 2-bit code X Y 2x4 Dec F F F 2 F 3 Bulb Bulb Bulb 2 Bulb 3 This is a 2x4 decoder which selects an output line based on the 2-bit code supplied. Truth table: X Y F F F 2 F 3 Chapter 3-p2 IT32 9
10 Decoders From truth table, circuit for 2x4 decoder is: X Y F F F 2 F 3 Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) F = X'Y' F = X'Y F 2 = XY' F 3 = XY X Y Chapter 3-p2 IT32
11 Decoder Examples -to-2-line Decoder Chapter 3-p2 IT32
12 Decoder Examples 2-to-4-Line Decoder Note that the 2-4-line made up of 2 -to-2- line decoders and 4 AND gates. Chapter 3-p2 IT32 2
13 Decoders Design a 3x8 decoder. x y z F F F 2 F 3 F 4 F 5 F 6 F 7 F = x'y'z' F = x'y'z F 2 = x'yz' F 3 = x'yz F 4 = xy'z' F 5 = xy'z F 6 = xyz' F 7 = xyz x y z Chapter 3-p2 IT32 3
14 Decoders In general, for an n-bit code, a decoder could select up to 2 n lines: n-bit code n to 2 n : decoder : up to 2 n output lines Chapter 3-p2 IT32 4
15 Decoder with Enable In general, attach m-enabling circuits to the outputs See truth table below for function Note use of X s to denote both and Combination containing two X s represent four binary combinations Alternatively, can be viewed as distributing value of signal EN to EN of 4 outputs In this case, called a demultiplexer A A D EN A A D D D 2 D 3 D X X D 2 D 3 (a) (b) Chapter 3-p2 IT32 5
16 Decoder with Enable Design a 3x8 decoder. E x y z F F F 2 F 3 F 4 F 5 F 6 F 7 x x x F = x'y'z' F = x'y'z F 2 = x'yz' F 3 = x'yz F 4 = xy'z' F 5 = xy'z Enabel (E) F 6 = xyz' F 7 = xyz x y z Chapter 3-p2 IT32 6
17 Decoder Expansion Another way to design a decoder is to break it into smaller pieces. Notice some patterns in the table below: When S2 =, outputs Q-Q3are generated as in a 2-to-4 decoder. When S2 =, outputs Q4-Q7are generated as in a 2-to-4 decoder. Chapter 3-p2 IT32 7
18 Decoder Expansion Here s a 3-to-8 decoder built from two smaller 2-to-4 decoders. When S2=, the bottom 2-to-4 decoder is enabled and generates a for one of outputs Q, Q, Q2or Q3. When S2=, the top 2-to-4 decoder is enabled instead, and a will be output for either Q4, Q5, Q6or Q7. Chapter 3-p2 IT32 8
19 Decoder Expansion Activity Chapter 3-p2 IT32 9
20 Encoding Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n m 2 n such that each valid code word produces a unique output code Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is to a binary code corresponding to the position in which the appears. Chapter 3-p2 IT32 2
21 Octal-to-Binary Encoder A = D + D3 + D5 + D7 A= D2 + D3 + D6 + D7 A2= D4 + D5 + D6 + D7 Chapter 3-p2 IT32 2
22 Octal-to-Binary Encoder Chapter 3-p2 IT32 22
23 Selecting Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic Chapter 3-p2 IT32 23
24 Multiplexers A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has n control inputs (S n -, S ) called selection inputs, 2 n information inputs (I 2 n -, I ), and one output Y A multiplexer can be designed to have m information inputs with m < 2 n as well as n selection inputs Chapter 3-p2 IT32 24
25 2-to--Line Multiplexer Since 2 = 2, n = The single selection variable S has two values: S = selects input I S = selects input I Truth Table The equation: Y = S I + SI Chapter 3-p2 IT32 25
26 2-to--Line Multiplexer The equation: Y = SI + SI The circuit: Decoder Enabling Circuits Note the regions of the multiplexer circuit shown: S -to-2-line Decoder 2 Enabling circuits 2-input OR gate I I Y Chapter 3-p2 IT32 26
27 2-to--Line Multiplexer (continued) To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 2 AND- OR circuit: -to-2-line decoder 2 2 AND-OR In general, for an 2 n -to--line multiplexer: n-to-2 n -line decoder 2 n 2 AND-OR Chapter 3-p2 IT32 27
28 Example: 4-to--line Multiplexer 2-to-2 2 -line decoder AND-OR Condensed Truth Table Chapter 3-p2 IT32 28
29 Multiplexer Width Expansion Some IC packages have a few multiplexers in each package. The selection and enable inputs are common to all multiplexers within the package. Select vectors of bits instead of bits Chapter 3-p2 IT32 29
30 Multiplexer Width Expansion A A A2 A3 Y Y Y2 Y3 S (select) E (enable) B B B2 B3 E S Output Y X all s select A select B Quadruple 2: multiplexer Chapter 3-p2 IT32 3
31 Three-State Implementation Chapter 3-p2 IT32 3
32 Larger Multiplexers Larger multiplexers can be constructed from smaller ones. An 8-to- multiplexer can be constructed from smaller multiplexers like this (note placement of selector lines): I I I2 I3 I4 I5 I6 I7 4: MUX S S 4: MUX 2: MUX S2 Y S 2 S S Y I I I 2 I 3 I 4 I 5 I 6 I 7 S S Chapter 3-p2 IT32 32
33 Summary Decoder: For each possible input condition, one and only one output signal will be at logic n-to-2 n decoder is simply a minterm generator, with output corresponding to exactly one minterm. Encoders: Assign a unique output code (a binary number) for each input signal applied to the device Opposite of the decoder Chapter 3-p2 IT32 33
34 Summary Demultiplexer: Connects a single input line to one of n output lines, the specific output being determined by a selection code Multiplexers: Connects a single output line to one of n input lines, the specific input being determined by a selection code. Chapter 3-p2 IT32 34
Encoders. Lecture 23 5
-A decoder with enable input can function as a demultiplexer a circuit that receives information from a single line and directs it to one of 2 n possible output lines. The selection of a specific output
More informationDigital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders
Indian Institute of Technology Jodhpur, Year 28 29 Digital Logic and Design (Course Code: EE222) Lecture 4: Combinational Contd.. Decoders/Encoders Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationUnit 3. Logic Design
EE 2: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Unit 3 Chapter Combinational 3 Combinational Logic Logic Design - Introduction to Analysis & Design
More informationDigital Electronics 8. Multiplexer & Demultiplexer
1 Module -8 Multiplexers and Demultiplexers 1 Introduction 2 Principles of Multiplexing and Demultiplexing 3 Multiplexer 3.1 Types of multiplexer 3.2 A 2 to 1 multiplexer 3.3 A 4 to 1 multiplexer 3.4 Multiplex
More informationDepartment of Electrical and Electronics Engineering Logic Circuits Laboratory EXPERIMENT-5 COMBINATIONAL LOGIC CIRCUITS
5.1 Preliminary Study Simulate experiment using an available tool and prepare the preliminary report. 5.2 Aim of the Experiment Implementation and examination of MULTIPLEXER and DEMULTIPLEXER circuits
More informationCombinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations
Combinational Logic Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations Copyright (c) 2012 Sean Key Combinational Logic Design
More informationSolutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature
ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id
More informationICS 151 Final. (Last Name) (First Name)
ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id
More informationUNIT III. Designing Combinatorial Circuits. Adders
UNIT III Designing Combinatorial Circuits The design of a combinational circuit starts from the verbal outline of the problem and ends with a logic circuit diagram or a set of Boolean functions from which
More informationMSI Design Examples. Designing a circuit that adds three 4-bit numbers
MSI Design Examples In this lesson, you will see some design examples using MSI devices. These examples are: Designing a circuit that adds three 4-bit numbers. Design of a 4-to-16 Decoder using five 2-to-4
More information(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification
More informationCOMBINATIONAL CIRCUIT
Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits
More informationCombinational Circuits: Multiplexers, Decoders, Programmable Logic Devices
Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Lecture 5 Doru Todinca Textbook This chapter is based on the book [RothKinney]: Charles H. Roth, Larry L. Kinney, Fundamentals
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitII 2. SKILLS ADDRESSED: Learning I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More informationCombinational Circuits DC-IV (Part I) Notes
Combinational Circuits DC-IV (Part I) Notes Digital Circuits have been classified as: (a) Combinational Circuits: In these circuits output at any instant of time depends on inputs present at that instant
More informationProject Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus.
Project Part 1 A Circuit Description and Diagrams: The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus. Shown below is a jpeg screenshot
More informationCombinational logic. ! Regular logic: multiplexers, decoders, LUTs and FPGAs. ! Switches, basic logic and truth tables, logic functions
Combinational logic! Switches, basic logic and truth tables, logic functions! Algebraic expressions to gates! Mapping to different gates! Discrete logic gate components (used in labs and 2)! Canonical
More informationCombinational Logic Circuits. Combinational Logic
Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The
More informationData output signals May or may not be same a input signals
Combinational Logic Part 2 We ve been looking at simple combinational logic elements Gates, buffers, and drivers Now ready to go on to larger blocks MSI - Medium Scale Integration or Integrate Circuits
More informationCS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page
More informationTABLE 3-2 Truth Table for Code Converter Example
997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z 2 3 4 5 6 7 8 9 Truth
More information16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)
16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Aim: To design multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Components required: Digital IC Trainer kit,
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More informationCHW 261: Logic Design
CHW 6: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Copyright 6 by Pearson Education, Inc. Upper Saddle
More informationLogic Families. Describes Process used to implement devices Input and output structure of the device. Four general categories.
Logic Families Characterizing Digital ICs Digital ICs characterized several ways Circuit Complexity Gives measure of number of transistors or gates Within single package Four general categories SSI - Small
More informationLogic Circuit Design
Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple
More informationECE COMBINATIONAL BUILDING BLOCKS - INVEST 14 DATA TRANSFER
C 24 - COMBINATIONAL BUILDING BLOCKS - INVST 4 DATA TRANSFR FALL 23 A.P. FLZR To do "well" on this investigation you must not only get the right answers but must also do neat, complete and concise writeups
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More informationEXPERIMENT NO 1 TRUTH TABLE (1)
EPERIMENT NO AIM: To verify the Demorgan s theorems. APPARATUS REQUIRED: THEORY: Digital logic trainer and Patch cords. The digital signals are discrete in nature and can only assume one of the two values
More information4:Combinational logic circuits. 3 July
4:Combinational logic circuits 3 July 2014 1 overview What is combinational logic circuit? Examples of combinational logic circuits Binary-adder Binary-subtractor Binary-multiplier Decoders Multiplexers
More informationDigital Electronics. Functions of Combinational Logic
Digital Electronics Functions of Combinational Logic Half-dder Basic rules of binary addition are performed by a half adder, which has two binary inputs ( and B) and two binary outputs (Carry out and Sum).
More informationLOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.
LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,
More informationClassification of Digital Circuits
Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational
More information7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers
7. Unit 7 Fundamental Digital Building Blocks: Decoders & Multiplexers CHECKER / DECODER 7.2 7.3 Gates Gates can have more than 2 inputs but the functions stay the same AND = output = if ALL inputs are
More information2 Building Blocks. There is often the need to compare two binary values.
2 Building Blocks 2.1 Comparators There is often the need to compare two binary values. This is done using a comparator. A comparator determines whether binary values A and B are: 1. A = B 2. A < B 3.
More informationCSCI "Decoders & Demultiplexers"
CSCI 2150 -- "Decoders & Demultiplexers" Reading: Digital Fundamentals section 6.8 The Need for Decoders Digital signals are often used to enable something. For example, we've spoken in class of the basic
More informationCOMPUTER TECHNOLOGY 2015/2016 Exercises. Unit 7
COMPUTER TECHNOLOGY 05/06 Exercises. Unit 7 Test. Identify the function of the figure below: A F ABC+ ABC B F ABC+ AB+ ABC C Neither A nor B are true ) About the circuit of the figure below, tick the true
More informationEE19D Digital Electronics. Lecture 1: General Introduction
EE19D Digital Electronics Lecture 1: General Introduction 1 What are we going to discuss? Some Definitions Digital and Analog Quantities Binary Digits, Logic Levels and Digital Waveforms Introduction to
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More informationLaboratory Manual CS (P) Digital Systems Lab
Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification
More informationUNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS
UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS STRUCTURE 2. Objectives 2. Introduction 2.2 Simplification of Boolean Expressions 2.2. Sum of Products 2.2.2 Product of Sums 2.2.3 Canonical
More informationCS302 - Digital Logic Design Glossary By
CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering
More informationSatish Chandra, Assistant Professor, P P N College, Kanpur 1
8/7/4 LOGIC GTES CE NPN Transistor Circuit COMINTIONL LOGIC Satish Chandra ssistant Professor Department of Physics P PN College, Kanpur www.satish4.weebly.com circuit with an output signal that is logical
More informationDigital Logic Design ELCT 201
Faculty of Information Engineering and Technology Dr. Haitham Omran and Dr. Wassim Alexan Digital Logic Design ELCT 201 Winter 2017 Midterm Exam Second Chance Please tick the box of your major: IET MET
More informationTiming and Power Optimization Using Mixed- Dynamic-Static CMOS
Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2013 Timing and Power Optimization Using Mixed- Dynamic-Static CMOS Hao Xue Wright State University Follow
More informationDO NOT COPY DO NOT COPY
456 Chapter 5 Combinational Logic Design Practices The first PAL devices were invented at Monolithic Memories, Inc. (MMI) in 978 by John Birkner and H. T. Chua. The inventors earned U.S. patent number
More informationDigital Electronic Concepts
Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course
More informationModule 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits
1 Module-4 Design and Analysis of Combinational Circuits 4.1 Motivation: This topic develops the fundamental understanding and design of adder, substractor, code converter multiplexer, demultiplexer etc
More informationBEE 2233 Digital Electronics. Chapter 1: Introduction
BEE 2233 Digital Electronics Chapter 1: Introduction Learning Outcomes Understand the basic concept of digital and analog quantities. Differentiate the digital and analog systems. Compare the advantages
More informationLogic and Computer Design Fundamentals. Chapter 6 Selected Design Topics. Part 1 The Design Space
Logic and Computer Design Fundamentals Chapter 6 Selected Design Topics Part 1 The Design Space Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview
More informationDepartment of Electronics and Communication Engineering
Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of
More information(a) (b) (c) (d) (e) (a) (b) (c) (d) (e)
Exercises 97 Exercises Exercise 2. Write a oolean equation in sum-of-products canonical form for each of the truth tables in Figure 2.8. (d) (e) C C C D Figure 2.8 Truth tables for Exercises 2. and 2.3
More information2-BIT MAGNITUDE COMPARATOR DESIGN USING DIFFERENT LOGIC STYLES
2-BIT MAGNITUDE COMPARATOR DESIGN USING DIFFERENT LOGIC STYLES 1 Shruthi B, Assistant professor, GSSSIETW, Mysuru 2 Ashwini K R Assistant professor, GSSSIETW, Mysuru ABSTRACT: 2-bit magnitude comparator
More informationUnit 1 Foundations in Electronics - Lesson 1.1 Introduction to Electronics Standards Essential Question Enduring Understandings
Course: DIGITAL ELECTRONICS- PROJECT LEAD THE WAY (DE-PLTW) Year: 2017-2018 Teacher: Mr. Christopher Reynolds/ Mr. Kenneth Rice Unit 1 Foundations in Electronics - Lesson 1.1 Introduction to Electronics
More informationJEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer
JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean
More information7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers
7. Unit 7 Fundamental Digital Building Blocks: Decoders & Multiplexers CHECKER / DECODER 7.2 7.3 Gates Gates can have more than 2 inputs but the functions stay the same AND = output = if ALL inputs are
More informationCombinational Logic Design CH002
Combinational Logic Design CH002 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications Figure 2.2 Elements and nodes Figure 2.3 Combinational logic circuit Figure 2.4 Two OR implementations
More informationPropagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPropagation Delay, Circuit Timing & Adder Design
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPaper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor
Swami Ramanand Teerth Marathwada University, Nanded B. Sc. First Year Electronics Syllabus Semester system (To be implemented from Academic Year 2009-10) Name of the Theory marks Practical marks Periods
More informationAsst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)
2145230 Aircraft Electricity and Electronics Asst. Prof. Thavatchai Tayjasanant, PhD Email: taytaycu@gmail.com aycu@g a co Power System Research Lab 12 th Floor, Building 4 Tel: (02) 218-6527 1 Chapter
More informationLecture Topics ECE 341. Lecture # 4. Decoder. 2-to-4 Decoder Circuit
ECE 34 Lecture # 4 Instructor: Zeshan Chishti zeshan@ece.pdx.edu October 8, 24 Portland State University Lecture Topics Decoders Multiplexers Programmable Logic Devices (PLDs) General Structure of PLDs
More informationIntegrated Circuit: Classification:
Integrated Circuit: It is a miniature, low cost electronic circuit consisting of active and passive components that are irreparably joined together on a single crystal chip of silicon. Classification:
More informationSubtractor Logic Schematic
Function Of Xor Gate In Parallel Adder Subtractor Logic Schematic metic functions, including half adder, half subtractor, full adder, independent logic gates to form desired circuits based on dif- by integrating
More information12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders
12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders Mr.Devanaboina Ramu, M.tech Dept. of Electronics and Communication Engineering Sri Vasavi Institute of
More informationSyllabus: Digital Electronics (DE) (Project Lead The Way)
Course Overview: Digital electronics and micro computers. This is a course in applied logic that encompasses the application of electronic circuits and devices. Computer simulation software is used to
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure NAND-NAND & NOR-NOR Networks DeMorgan
More informationGates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
More informationOverview. This lab exercise requires. A windows computer running Xilinx WebPack A Digilent board. Contains material Digilent, Inc.
Module 6: Combinational Circuit Blocks Revision: August 30, 2007 Overview This lab introduces several combinational circuits that are frequently used by digital designers, including a data selector (also
More informationCOLLEGE OF ENGINEERING, NASIK
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASIK LAB MANUAL DIGITAL ELECTRONICS LABORATORY Subject Code: 2246 27-8 PUNE VIDYARTHI GRIHA S COLLEGE OF ENGINEERING,NASHIK. INDEX Batch : - Sr.No Title
More informationMultiple input gates. The AND gate
Multiple input gates Inverters and buffers exhaust the possibilities for single-input gate circuits. What more can be done with a single logic signal but to buffer it or invert it? To explore more logic
More informationDe Morgan s second theorem: The complement of a product is equal to the sum of the complements.
Q. What is Gate? State and prove De Morgan s theorems. nswer: digital circuit having one or more input signals but only one output signal is called a gate. De Morgan s first theorem: The complement of
More informationComputer Architecture and Organization:
Computer Architecture and Organization: L03: Register transfer and System Bus By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU Outlines
More informationDIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3
DIGITAL ELECTRONICS Marking scheme : Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 Aim: This experiment will investigate the function of the
More informationPractical Workbook Logic Design & Switching Theory
Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL SYSTEM DESIGN SEMESTER III SUBJECT CODE: EC UNIT : Design of Combinational Circuits PART -A ( Marks).
More informationDIGITAL LOGIC CIRCUITS
LOGIC APPLICATIONS DIGITAL LOGIC CIRCUITS Noticed an analogy between the operations of switching devices, such as telephone switching circuits, and the operations of logical connectives What happens when
More informationTopic Notes: Digital Logic
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 20 Topic Notes: Digital Logic Our goal for the next couple of weeks is to gain a reasonably complete understanding of how
More informationUNIT-IV Combinational Logic
UNIT-IV Combinational Logic Introduction: The signals are usually represented by discrete bands of analog levels in digital electronic circuits or digital electronics instead of continuous ranges represented
More informationElectrical, Electronic and Communications Engineering Technology/Technician CIP Task Grid
Secondary Task List 100 SAFETY 101 Describe OSHA safety regulations. 102 Identify, select, and demonstrate proper hand tool use for electronics work. 103 Recognize the types and usages of fire extinguishers.
More informationLogic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 07 October 31, 2011 / November 07, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative
More informationChapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1
Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar
More informationFunction Table of 74LS138, 3-to-8 Decoder +5V 6 G1 4 G2A 5 G2B. 4-to-16 Decoder using two 74LS139, 3-to-8 Decoder
CS0 Digital Logic Design The XX8 -to-8 Decoder The -to-8, XX8 Decoder is also commonly used in logical circuits. Similar, to the -to- Decoder, the -to-8 Decoder has active-low outputs and three extra NOT
More informationCMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology
CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard
More informationLogic Symbols with Truth Tables INVERTER A B NAND A B C NOR C A B A B C XNOR A B C A B Digital Logic 1
Slide Logic Symbols with Truth Tables UFFER INVERTER ND NND OR NOR XOR XNOR 6.7 Digital Logic Digital logic can be described in terms of standard logic symbols and their corresponding truth tables. The
More informationDEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING
DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING (Regulation 2013) EE 6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL 1 SYLLABUS OBJECTIVES: Working Practice in simulators / CAD Tools / Experiment
More informationA Simulation Study of an Elevator Control System using Digital Logic
A Simulation Study of an Elevator Control System using Digital Logic Md. Mohsinur Rahman Adnan #1, Md. Zunaid Sikder #2, Mohammed Mushfiquzzoha #3, Mahdi Zulfikar #4 #1 Department of EEE, Shahjalal University
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 13 Building Blocks (Multipliers) Register Adder Shift Register Adib Abrishamifar EE Department IUST Acknowledgement This lecture note has been summarized and categorized
More informationA 2-bit/step SAR ADC structure with one radix-4 DAC
A 2-bit/step SAR ADC structure with one radix-4 DAC M. H. M. Larijani and M. B. Ghaznavi-Ghoushchi a) School of Engineering, Shahed University, Tehran, Iran a) ghaznavi@shahed.ac.ir Abstract: In this letter,
More informationName: Class: Date: 1. As more electronic systems have been designed using digital technology, devices have become smaller and less powerful.
Name: Class: Date: DE Midterm Review 2 True/False Indicate whether the statement is true or false. 1. As more electronic systems have been designed using digital technology, devices have become smaller
More informationBasic Characteristics of Digital ICs
ECEN202 Section 2 Characteristics of Digital IC s Part 1: Specification of characteristics An introductory look at digital IC s: Logic families Basic construction and operation Operating characteristics
More informationELECTROVATE. Electromania Problem Statement Discussion
ELECTROVATE Electromania Problem Statement Discussion An Competition Basic Circuiting What is Electromania? Innovation Debugging Lets Revise the Basics Electronics Digital Analog Digital Electronics Similar
More informationAim. Lecture 1: Overview Digital Concepts. Objectives. 15 Lectures
Aim Lecture 1: Overview Digital Concepts to give a first course in digital electronics providing you with both the knowledge and skills required to design simple digital circuits and preparing you for
More information8.1. Unit 8. Fundamental Digital Building Blocks: Decoders & Multiplexers
8. Unit 8 Fundamental Digital Building Blocks: Decoders & Multiplexers 8.2 Checkers / Decoders Recall AND gates output '' for only a single combination OR gates output '' for only a single combination
More informationElektrische Parameter Grundlagen der technischen Informatik
Elektrische Parameter Grundlagen der technischen Informatik Wintersemester 28/9 Folien basierend auf F. Vahid und S. Werner Wintersemester 28/9 Review - Multiple-Output Circuits Many circuits have more
More information