DIGITAL LOGIC COMPUTER SCIENCE

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1 29 DIGITL LOGIC COMPUTER SCIENCE

2 Unit of ENGINEERS CREER GROUP Head O ce: S.C.O , 2 nd Floor, Sector-34/, Chandigarh-622 Website: Toll Free: ecgpublica ons@gmail.com info@engineerscareergroup.in GTE-29: Digital Logic Detailed theor with GTE previous ear papers and detailed solu ons. b ECG Publica ons ( unit of ENGINEERS CREER GROUP) ll rights are reserved to reproduce the cop of this book in the form storage, introduced into a retrieval sstem, electronic, mechanical, photocoping, recording, screenshot or an other form without an prior wri en permission from ECG Publica ons ( Unit of ENGINEERS CREER GROUP). First Edi on: 26 Price of ook: INR 25/- ECG PULICTIONS ( Unit of ENGINEERS CREER GROUP) collected and proving data like: theor for di erent topics or previous ear solu ons ver carefull while publishing this book. If in an case inaccurac or prin ng error ma nd or occurred then ECG PULICTIONS ( Unit of ENGINEERS CREER GROUP) owes no responsibilit. The sugges ons for inaccuracies or prin ng error will alwas be welcome b us.

3 CONTENTS CHPTER PGE COMINTIONL LOGIC CIRCUIT

GTE-29 DIGITL LOGIC CHPTER - NUMER SYSTEM.

indicates that it is positive (+ve) number

Range and also has 2 unique representation

Its Range = (2n ) to + (2n ) such as for n

complement inar (r = 2) complement Octal

5 GTE-29 DIGITL LOGIC CHPTER - NUMER SYSTEM. DT REPRESENTTION Data can be an digit, character or an smbol. nd it can be represented in following categories. Magnitude Representation. Unsigned magnitude representation (positive): No sign bit 2. Signed magnitude representation (positive, negative): One extra bit (sign) as MS Complement Representation. (r complement: (positive, negative) 2. r : (positive, negative) MS = (positive) MS = (negative).. Sign Magnitude Representation. indicates that it is positive (+ve) number and negative ( ve) sign before a number indicates that it is ve number. Replace +ve with MS and ve with MS followed b binar equivalent of given number to get its sign representation. 2. Range and also has 2 unique representation for zero. Its Range = (2n ) to + (2n ) such as for n = 7 range is ( 63) to (+ 63) Example (+)2 ()2 (+.)2 (.)2 ( )2 ()2 (.)2 (.)2..2 Complement There are two tpes of complements:. (r ement 2. ment, Where, r = base of complement complement inar (r = 2) complement Octal (r = 8) Hexadecimal (r = 6) Decimal (r =) complement complement complement complement complement complement (r Complement: To determine this complement, subtract the given number from maximum number having number of digits equal to the number of digits in given number possible in given base. ECG PULICTIONS unit of ENGINEERS CREER GROUP

6 DIGITL LOGIC GTE-29 SSIGNMENT. When signed numbers are used in binar arithmetic, then which one of the following notations would have unique representation for zero? (a) sign magnitude 7. Octal equivalent of hexadecimal FFF is (a) (b) (c) (d) (77) 8 + = (X)8, the value of x is (a) 78 (b) 79 (c) 2 (d) None of these 2. In the following codes a binar number YY2Y3 is converted b the given circuit 9. Noting that 32 = 9, formulate a simple procedure for converting base 3 numbers directl to base 9 use the procedure to convert ( )3 to base 9. (a) ( )9 (b) (226244)9 (c) ( )9 (d) None of these x 2 x2 3 x3. Identif the first decimal digits in ase 4 number sstem (a),, 2, 3, 4, 5, 6,,, 2 3. ddition of all the gra codes to convert (b),, 2, 3, 4, 5, 6, 7,, (c),, 2, 3,,, 2, 3, 4 decimal (-9) into gra code is: (d),, 2, 3,,, 2, 3, 2, 2 (a) 29 (b) 8 (c) 69 (d) 53. 2? 4. Input (a) 24 (b) 234 Output X= (c) 2862 (d) 33 Gra Code XOR (a) Excess-3 Code (c) Decimal Code (b) Gra Code (d) CD Code X2= Decimal 2. X and Y are successive digits in a positional number sstem. lso XY = 25 and YX = 3. Determine the Radix value of the 5. If (23)5 = (x3), then the number of sstem and value of X and Y. possible values of x is (a) 6, 4, 2 (b) 7, 3, 4 (a) 4 (b) 3 (c) 7, 4, 3 (d) 6, 4, 3 (c) 2 (d) 3. Consider the signed inar numbers 6. computer has the following negative = and =, where is in numbers stored in binar form as shown. The m. Match the following. wrongl stored number is: List-I (a) 37 as. + (b) 89 as. (c) 48 as C. (d) 32 as D. List-II (a) (b) +3 (b) +27 (d) Zero ECG PULICTIONS unit of ENGINEERS CREER GROUP 5

7 DIGITL LOGIC GTE-29 SOLUTIONS Sol. (c) X Sol. 2 (c) 3 2 x = x2 = x3 = Let us take the binar input It forms a gra code. inar Code Gra Code Sol. 3 (d) Decimal CD Gra Code Total= Decimal Equivalent of Gra X2=? X X2 X X 2 inar number: ( ) 2 inar to Gra Code: ( )2 Gra code to Decimal: = = = +27 Sol. 5 (c) (23)5 = (x3) then = x = x = x Possible factor of 35 are: 35 : when = 35, x = is possible. 35 : when =, x = 35 is not possible 5 7 : when = 7, x = 5 is possible. 7 5: when = 5, x = 7 is not possible. Hence x has 2 possible values. Sol. 6 (c) Sol. 4 (b) X =, X 2 = ECG PULICTIONS unit of ENGINEERS CREER GROUP 9

8 DIGITL LOGIC GTE-29 GTE UESTIONS. Given the following binar number in 32-bit (single precision) IEEE 754 format: The decimal value closest to this floating point number is [GTE - 27] (a).45 (b).45 (c) 2.27 (d) Consider the equation (23)5 = (x8) with x and as unknown. The number of possible solutions are. [GTE - 24] 2. The representation of the value of a 6- bit unsigned integer X in hexadecimal number sstem is C9. The representation of the value of X in octal number sstem is [GTE - 27] (a) 5724 (b) (c) (d) 3625 [GTE - 24] 9. The base (or radix) of the number sstem such that the following equation holds is.. The decimal value.5 in IEEE single precision floating point representation has [GTE - 22] (a) value of 3. Let X be the number of distinct 6-bit value of Y be the number of distinct 6-bit integers in value of sign magnitude representation. (d) No exact representation is. [GTE - 26]. (27)8 is equivalent to [GTE - 29] 4. The 6(a) (27)6 (b) (28F)6 an integer is ; its decimal (c) (2297) (d) (7)6 representation is. 2. The two numbers repre [GTE - 26] complement form are P= and =. If is subtracted from P, the 5. Consider the equation (43)x = (3)8 where x and are unknown. The number of possible is solutions are. [GTE - 28] [GTE - 25] (a) (b) (c) (d) 6. The number of btes required to represent the decimal number in packed CD 3. In the IEEE floating point representation the (inar Coded Decimal) from is. hexadecimal value x corresponds to [GTE - 24] [GTE - 28] 7. Which of the following is an invalid state in (a) The normalized value 2-27 an inar coded decimal counter (b) The normalized value 2-26 [GTE - 24] (c) The normalized value + (a) (b) (d) The special value + (c) (d) ECG PULICTIONS unit of ENGINEERS CREER GROUP 24

9 DIGITL LOGIC GTE-29 CHPTER - 2 LOGIC GTES & OOLEN LGER 2. LOGIC GTE. The fundamental building block of digital sstem Logic gate means that o/p and i/p pattern of gate are assigned logicall. 2. The inter connection of Gates is to perform a variet of logical operations is called logic design. 3. The input and output of logic gate can occur onl in two levels. These levels are termed as high () and Low () simpl. 4. Truth table show how the logic circuit o/p responds to various combination of logic levels of i/p. 5. There are various tpes of gates (i) asic Gates: NOT, ND & OR (ii) Universal Gate: NND & NOR (iii) EXOR & ENOR: rithmetic, comparator, code converter, parit generator and parit checker. 2.. asic Gates. NOT Gate (i) It is one input and one-output gate. (ii) Its output is inverted to its corresponding input. If input is then its output is and if its input is then its output is. (iii) It is called inverter. (iv) It is represented b following smbol (v) Its all possible input combination and its corresponding output can be represented in the form of table called Truth Table. Truth table for NOT gate is following Truth Table (i) (ii) uffer Storage Switching diagram (vi) It act as basic memor element or cross coupled latch storage element and represented as ECG PULICTIONS unit of ENGINEERS CREER GROUP 3

10 DIGITL LOGIC GTE-29 SSIGNMENT. Which of the following logic expression is incorrect? (a) = (b) = (c) = (d) = x f(x, ) 2. Which of the following oolean algebra (a) Exclusive OR statements represent distributive law? (b) Exclusive NOR (a) (+) +C = + (+C) (c) NND (b). (+C) = (.) + (.C) (d) NOR (c).(.c) = (.).C (d) None of these 6. The binar number is to be converted to gra code. The number of gates and tpe 3. Which expression is computed b the required are: following NND-gate circuit diagram? (a) 6, ND (b) 6, XNOR x x z z (c) 6, XOR (d) 5, XOR NND NND NND 7. The output of the logic gate in the figure is NND Y NND F (a) x +z (c) x z (b) (x+) z (d) x + +z (a) + C +C (b) +C (c) (d) + + C 4. What is the equivalent oolean expression in 8. What is the minimum number of NND product of sum form for the K-map given gates required to implement C below? (a) (b) CD (c) 4 (d) 7 (a) D + D (b) (+C +D) ( +C+D ) (c) (+D ) ( +D) (d) ( +D ) (+D) 9. If x and are oolean variables, which one of the following is the equivalent of x x. (a) x+ (b) x+ (c) (d). Consider the following gate network which of following gates is redundant? 5. Identif the logic function performed b the circuit. ECG PULICTIONS unit of ENGINEERS CREER GROUP 47

11 DIGITL LOGIC GTE-29 SOLUTIONS Sol. (b) Sol. 6 (d) Sol. 2 (a) LS Sol. 3 (d).+.=.+.=.+.=+=.+.=+=.+.=+=.+.=+= X NND XX=X X X.Y=X+Y NND (X+Y)Z NND F Y YY=Y NND Y F=XY+Z F=X Y +Z Z NND ZZ=Z Hence answer is (a) Sol. 7 (c) Ground(G) G The Output is complemented. CD Sol. 8 (a) F C In product of sum form we take the output as D D Sol. 5 (b) x x MS It converts inar code to Gra Code. is converted to 5 XOR gates are required. Z Sol. 4 (d) x+x x x+ =x +x =x+=x It contains one ND gate and one OR gate, No NND gate is required. Sol. 9 (b) = x x = x =x f(x,) x+x=x x+ C x x = x x x x x x = x x x x x = xx xx x x....,. x x.x x.x x x x x x... ECG PULICTIONS unit of ENGINEERS CREER GROUP 57

12 DIGITL LOGIC GTE-29 (a) W, Y, XZ,XZ (b) W, Y, X Z (c) Y, XYZ (d) Y, XZ, XZ 7. The oolean expression (X Y )(X Y) X simplifies to (X Y ) [GTE - 24] (a) X (c) XY (b) Y (d) X+Y (c) P (d) P 2. Consider the following minterms expression for F:F(P,,R,S)= (,2,5,7,8,,3,5) The The minimal sum - of - products form for F is [GTE - 24] (a) S S 8. Which of the following logic circuits is a (b) S S realization of the function F whose Karnaugh (c) RS RS RS RS map is shown in figure. (d) PS PS PS [GTE - 24] C (a) C (b) C c C (c) C (d) 22. The dual of a oolean function F(x, x2, ), written as FD, is the same n,+, expression as that of F with + and swapped. F is said to be self dual if F = FD. The number of self dual functions with n oolean variable is [GTE - 24] (a) 2n (b) 2n- n (c) 2 2 (d) 22 n 23. Consider the following oolean expression for F: F(P,, R, S) = P + PR PRS The minimal sum of products form of F is [GTE - 24] (a) P + R + S (b) P + + R + S (c) P R S (d) PR PRS P 9. The SOP (sum of products) form of a oolean function is (,,3,7,), where input are,, C, D ( is MS, and D is LS). The equivalent minimized expression of the function is [GTE - 24] 24. Which one of the following expression does NOT represent exclusive NOR of x and? (a) ( C)( C)( )(C D) [GTE - 24] (b) ( C)( C)( C)(C D) (a) x + x (b) x (c) ( C)( C)( C)(C D) (c) x (d) x (d) ( C)( )( )(C D) 25. In the sum of products function f (X,Y,Z) = 2. Let denotes the Exclusive OR (XOR) (2,3,4,5),the prime implications are [GTE - 22] constants. Consider the following oolean (a) XY,XY expression for F over two variables P and. (b) XY, XYZ.XYZ F(P, ) = (( P) (P )) ((P ) ( )) (c) XYZ, XYZ XY The equivalent expression for F is [GTE - 24] (d) XYZ,XYZ,XYZ,XYZ (a) P + (b) P ECG PULICTIONS unit of ENGINEERS CREER GROUP 68

13 DIGITL LOGIC GTE-29 CHPTER - 3 COMINTIONL LOGIC CIRCUIT 3. INTRODUCTION For an logic Design it is alwas essential to design a product which meets the requirement as:.minimum cost 2. Minimum space requirement 3. Maximum speed of operations 4. Eas availabilit of component 5. Ease of inter connection of components 6. Eas to Design 3.. Sequential Logic Logic circuits whose outputs are determined b the sequence in which input signals are applied. 3.2 COMINTIONL CIRCUITS The circuits whose output depends upon the current input combinations onl are called combinational circuits. Combinational Logic circuit Where p is input binar variable term as external source. nd is output variable go to external destination Design Procedure. Statement is assigned with variable analsis. 2. The no. of input and output variable is determined 3. The logic that defined the relation between input and output are determined 4. Logic function diagram is associated Characteristic of Combinational circuit. Present output depends on onl the present input 2. No feedback is available/present 3. No storage (man) element is required Example. (i) dder and Subtractor (ii) Multiplexer and De-Multiplexer (iii) Decoder and Encoder 3.3 RITHMETIC COMINTIONL CIRCUIT dder and Subtractor are rithmetic combinational circuits Half dder It adds onl an two bits and gives their sum and carr. ECG PULICTIONS unit of ENGINEERS CREER GROUP 85

14 DIGITL LOGIC GTE-29 SSIGNMENT 3 2. The following logic circuit f(w, x,, z) indicates CD Input z 4bit-Full dder C 2 3 Decoder C D 3 2 4bit-Full dder (a) C, C,, C (c),, C, C x (b),, C, C (d) C,C,C, w 4. oolean function F with,, C as inputs is expressed on Karnaugh map as shown below. If this function is implemented with 4 : multiplexer as, C selection lines, identif the input connections C C C C C 2. Identif the function of the following logic circuit (a) inar to CD converter (b) CD to inar converter (c) CD to Decimal converter (d) CD to Excess 3 converter 3 4 C 4 bit Full dder C S4 S3 S2 S (a) 4 bit inar adder (b) 4 bit CD dder (c) 4 bit inar subtractor (d) 4 bit CD subtractor (a),,, (c),,, (b),,, (d),,, 5. The output of the 4 in figure is multiplexer shown Y I3 I2 +5V X MUX Z I I S S 3. The following logic circuit adds two digits represented in the Excess - 3 code. The correction required after adding the two digits in Y EX-3 form is as follows. (a) X Y (b) XY X If C = and + 3 (c) XY (d) X Y Identif the inputs to be given to the 2nd 4 - bit full adder? 6. Identif the output of the following logic circuit ECG PULICTIONS unit of ENGINEERS CREER GROUP

15 DIGITL LOGIC GTE-29 SOLUTIONS Sol. (d) From truth table of CD to excess z D m,3, 4,7,8 x 3 code m,2, 3, 4, 9 w For Sum = = 4ns For Carr = = 4ns Sol. 9 (b) X C C C C C m 5, 6, 7,8, 9 Sol. 2 (c) It is 4 bit binar subtractor C C C C C Sol. (c) X C C C Sol. 3 (d) If C = and 3 means i/p to 2nd 4 bit full adder should be CC C If C = subtract 3 means i/p to 2nd 4 bit full adder should be CCC So i/p to 2nd So there are 5 literal,,c, and C adder should be CCC. Sol. 2 (c) Sol. 4 (d) From K map C C C C C Output of first MUX Sol. 6 (a) F X X 2 X X 2 D c a X2 b c a b c ab ab c Z2 a bb ab b O ba ab a a c b ab abc abc ab bc ac Sol. 3 (b) Y X O O b b ab X Y D a Sol. 7 (d) For full adder Sum = C and Carr = + C ( ) So it requires 2 2 input X-OR, 2 input ND,2 2 input OR gates. Sol. 8 F Z When C =, o/p is equal to, so I = When C =, o/p is equal to, so I = When C =, o/p is equal to, so I2 = Sol. 5 (a) Z Y YX Y Y X Y Sol. (c) O/P of ND gate is (x ) x Sol. 4 (d) To construct a 5 32 line decoder -to-4 decoders are used. Sol. 5 (a) For C5 generation, 4 carr generation path will come into path. Sol. 6 (c) Total dela = = 44 ns Sol. 7 (c) (c) ECG PULICTIONS unit of ENGINEERS CREER GROUP 6

16 DIGITL LOGIC GTE-29 GTE UESTIONS b. When two 8-bit numbers 7 and 7 I representation (with I 4 and as the least significant bits) are added F I 2 MUX using a ripple - carr adder, the sum bits obtained are S7 and the carr bits are I3 S S C7. an overflow is said to have occurred if [GTE - 27] (a) (b) (a) The carr bit C7 is (c) (d) (b) ll the carr bits (C7 C) are (c) ( 7.7.S S7 ) is 5. In the figure shown, the output Y is (d) (..S..S ) is required to be Y C D. The gates G and G2 must be, respectivel 2. Consider a carr look ahead adder for [GTE - 25] adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is G [GTE - 26] G2 Y (a) (b) log n C (c) n (d) n D 3. Consider the two cascaded multiplexers as shown in the figure. R 2-to- (a) NOR, OR (c) NND, OR (b) OR, NND (d) ND, NND 6. half adder is implemented with XOR and ND gates. full adder is implemented with X two half adders and one OR gate. The R propagation dela of an XOR gate is twice that of an ND/OR gate. The propagation dela of an ND/OR gate is.2 microseconds. 4-bit P The minimal sum of products form of the output ripple-carr binar adder is implemented b using full adders. The total propagation time of X is [GTE - 26] this 4-bit binar adder in microseconds is. (a) P P R (b) P R [GTE - 25] (c) P P R (d) R PR 2-to- MUX S 2-to- MUX S 4. In the 4 multiplexer, the output F is 7. The number of min-terms after minimizing the following oolean expression is given b F =. Find the required input 3 I 2 I I [GTE - 25] [GTE - 25] ECG PULICTIONS unit of ENGINEERS CREER GROUP 8

17 DIGITL LOGIC GTE-29 CHPTER - 4 SEUENTIL LOGIC CIRCUIT 4. INTRODUCTION. In combinational circuit the present O/P depends onl upon the present input an prior level. (Input condition) does not have an effect on present output. 2. In sequential circuits, Present output depends upon the present input combinations as well as previous outputs of the sstem. Therefore, sequential circuits have feedback propert IT MEMORY CELL. The following circuits are designed to store -bit data. The use feedback propert hence the are sequential circuits that are the simplest.2. Information stored in memor element at an given time define the present state of sequential circuit. (a) (b) (c) Invert Latch using NND Gate Latch using NOR Gate Latch lock Diagram Combinational Circuit Input Output Memor element 4.3 LTCHES. 2. The are not dependent upon the clock signal for their operation. 3. latch is a sequential device that checks all its inputs continuousl and changes its output accordingl at an time independent of clock signals. Set Reset Logic smbol 4.3. S-R Latch using NOR Gate The Set Reset Latch can be designed using NOR Gates as following ECG PULICTIONS unit of ENGINEERS CREER GROUP 2

18 DIGITL LOGIC GTE-29 SSIGNMENT. counter constructed using T FFs counts the decimal digits according to 2, 4, 2, code. The input T is (a) + CD (b) + CD (c) + D (d) + D 5. N bit register is constructed using D flip flops. Match the following List-I with List-II List-I. Parallel in parallel out. Serial in serial out 2. sequential circuit is as shown below. If C. Parallel in serial out present states of, 2, are, and x =, what D. Serial in parallel out is its next state and output List-II (i) (2N ) clock pulses (ii) One clock pulses D (iii) N clock pulses CLK (iv) (N ) clock pulses Codes: D (a) -iii, -iv, C-ii, D-i CLK (b) -iv, - ii, C-i, D-iii (c) -iii, -ii, C-iv, D-i X (d) -ii, -i, C-iv, D-iii (a),, (b),, (c),, (d),, 6. Determine the output of the negative Edge 3. In a 4 bit modulo 6 ripple counter the triggered J-K flip flop for the following input proportional dela of J-K Flip flop is 5ns. waveforms at T, T2, T3, T4. ssume the hold What is the max clock frequenc that can used time FF is. without skipping a count? (a) 2MHz (b) 4 MHz J (c) 5 KHz (d) 5 MHz In the following logic circuit, the 8 bit left shift register and D Flip flop is snchronized with same clock. The D Flip flop is initiall cleared. The circuit acts as K b7 b6 b5 b4 b3 b2 b b CLK D CLK (a) inar to 2 s complement converter (b) inar to EX 3 code converter (c) inar to s complement converter (d) inar to Gra code converter (a),,, (c),,, T T2 T3 T4 (b),,, (d),,, 7. Two J K FFS having negative edge triggering are connected as shown in figure. Which of the following conditions have to be satisfied for proper functioning of the circuit. ECG PULICTIONS unit of ENGINEERS CREER GROUP 45

19 DIGITL LOGIC GTE-29 SOLUTIONS Sol. (a) Present Next State State CD TTTCTD CD Decimal 9 T CD Parallel in serial out (N ) clock pulses Serial in parallel out N clock pulses Sol. 6 (b) For T, J = and K =, so = For T2, J = and K =, so = For T3, J = and K =, so = For T4, J = and K =, so = Sol. 7 (c) For proper functioning th < tplh, so that 2nd FF can latch proper data. Sol. 8 (d) X = clock and Y = clock So waveforms are as follows cl f=mhz f=5khz f=5khz X f=5khz Y f=5khz Sol. 2 (c) Sol. 9 (c) Input to D F/F = Using 3FF counter can count 23 = 8 states Input to 2 D F/F = so after clock o/p of and 2 will be, Therefore, mod 6 counter will slip 2 counts if it is made of 3FF. respectivel so =. Sol. 3 (d) Total propagation dela = 4 maximum frequenc used 5 6 Hz ns Sol. 4 (d) Circuit act as binar to gra code convertor Sol. 5 (d) Parallel In Parallel out one clock pulse Serial in Serial out (2N ) clock pulses Sol. (d) When X = and Y = C, the outputs are cleared at the sequence C =. For all other states, the counter works in normal operation. Sol. (a) For m FF total no. of outcomes (outputs) will be 2m and total number of inputs = n (given). Hence in state table total columns will be total Sol. 2 (d) ECG PULICTIONS unit of ENGINEERS CREER GROUP 53

20 DIGITL LOGIC GTE-29 GTE UESTIONS. Consider a combination of T and D flip repeats. The minimum number of J-K flip-flops flops connected as shown below. The output of required to implement this counter is. the D flip flop is connected to the input of the [GTE - 26] T flip flop and the output of the T flip flop is connected to the input of the D flip flop. 4. Consider an eight-bit ripple-carr adder for computing the sum of and, where and D T are integers represented in 2 s complement Flip Flip- Flop Flop form. If the decimal value of is one, the decimal value of that leads to the longest latenc for the sum to stabilize is. Clock Initiall, both and are set to (before the st clock ccle). The outputs [GTE - 27] (a) after the 3rd ccle are and after the 4th ccle are respectivel (b) after the 3rd ccle are and after the 4th ccle are respectivel (c) after the 3rd ccle are and after the 4th ccle are respectivel (d) after the 3rd ccle are and after the 4th ccle are respectivel 2. The next state table of a 2-bit saturating up counter is given below. + + The counter is built as a snchronous sequential circuit using T flip flops. The expression for T and T are [GTE - 27] (a) T, T (b) T, T (c) T, T (d) T, T [GTE - 26] 5. The figure shows a digital circuit constructed using negative edge triggered J K flip flops. ssume a starting state of 2 =. This state 2 = will repeat after CLK J J2 2 Clock Clock Clock K J K K 2 2 [GTE - 25] 6. In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is =. The state (), immediatel after the 3rd clock pulse is J K J K CLK (a) (c) [GTE - 25] (b) (d) 3. We want to design a snchronous counter that 7. The figure shows a binar counter with counts the sequence and then snchronous clear input. With the decoding logic shown, the counter works as a ECG PULICTIONS unit of ENGINEERS CREER GROUP 6

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design