ECE 2300 Digital Logic & Computer Organization
|
|
- Alfred Fitzgerald
- 5 years ago
- Views:
Transcription
1 ECE 2300 Digital Logic & Computer Organization Spring 2018 Timing Analysis Lecture 11: 1
2 Announcements Lab report guidelines are uploaded on CMS As part of the assignment for Lab 3 report Lab 4(A) prelab due tomorrow Lecture 11: 2
3 Synchronous Circuits combinational The changes in the state of the memory elements are synchronized by a clock signal All flip-flops (FFs) are synchronized to capture the inputs simultaneously on the clock tick Must ensure the output of the combinational has settled before the next clock tick Lecture 11: 3
4 Review: Glitches in Synchronous Circuits X Y S S S Y S X F X S S X F Y S Y Lecture 11: 4
5 Stable FF Situation t clk stable stable t setup t hold t ffpd Flip-flop propagation delay (or clock-to-q delay): the time it takes for the FF output to be stable after the clock edge Lecture 11: 5
6 What if This Happens? IN CLK1 D CLK Q Q1 combinational D2 CLK2 D CLK Q IN CLK1 Q1 D2 CLK2 D2 input still transitioning May capture neither HIGH nor LOW Lecture 11: 6
7 Metastable State unstable t setup t hold Q stuck in the undefined region between 0 and 1 metastable Eventually moves to a stable state, but may take a while (metastable resolution time) Lecture 11: 7
8 But What About This Situation? X Y S S S Y S X F Wrong value captured X S S X F Y S Y Lecture 11: 8
9 Avoiding Timing Failure Possible causes of metastability and wrong value capture Clock pulse that is too narrow Input changes too soon before a clock edge Input changes too soon after a clock edge Avoid by meeting setup time, hold time, and minimum clock pulse width specifications Lecture 11: 9
10 Sequential Circuit Timing Analysis Timing analysis involves calculating the time delays between all FF pairs within the circuit To determine the maximum operating frequency and ensure that setup time requirements are met The clock cannot be too fast To ensure that hold time requirements are met The minimum propagation delay of the combinational (contamination delay) cannot be too small Independent of clock frequency Lecture 11: 10
11 Important Timing Parameters combinational t clk t ffpd t comb t setup t hold Lecture 11: 11
12 Setup Time Constraint t setup is the minimum amount of time before the triggering edge during which FF input must be stable t clk t ffpd t comb t setup t hold Lecture 11: 12
13 Determining Clock Cycle Time FF1 combinational FF2 t ffpd(max) + t comb(max) + t setup t clk Every circuit path between every pair of FFs must satisfy the above equation to run the circuit at a frequency of 1/t clk The longest timing path (worst case) determines the maximum clock frequency Worst case temperature and voltage Worst case manufacturing variations Lecture 11: 13
14 Example: Setup Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb What s the best achievable cycle time? Lecture 11: 14
15 Example: Setup Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb t clk >= t ffpd(max) + t comb(max) + t setup = = 19ns Lecture 11: 15
16 Hold Time Constraint FF1 combinational FF2 t hold is the minimum amount of time after the triggering edge during which FF input must remain stable Otherwise, the receiving flip-flop may be contaminated with an unexpected value Need to consider minimum propagation delays (contamination delays) for hold time calculations t ffpd(min) + t comb(min) t hold Lecture 11: 16
17 Example: Hold Time Constraint IN FF1 Q1 very short wire (assume negligible delay) D2 FF2 Q2 IN t ffpd t ffpd Q1 D2 Q2 Hold time windows (t hold ) D2 must be held stable for FF2 t ffpd(min) + t comb(min) = t ffpd(min) +0 t hold Lecture 11: 17
18 Example: Hold Time Calculations FF1 combinational FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb Hold time at FF2 met? Lecture 11: 18
19 Clock Skew Complicates Matters Further Clock may not reach all flip-flops simultaneously CLK1 FF1 combinational [long wire] CLK2 FF2 (assume nontrivial delay) tskew CLK1 (delayed) CLK2 t skew(max) : Maximum clock skew t skew(min) : Minimum clock skew Lecture 11: 19
20 Cycle Time With Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 (delayed) (delayed) (delayed) CLK2 tskew tsetup Lecture 11: 20
21 Negative Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 (delayed) (delayed) (delayed) t ffpd t comb CLK2 tskew tsetup Sending FF receives clock later than receiving FF t ffpd(max) + t comb(max) + t setup t clk t skew(max) Harmful skew for meeting setup time constraint Lecture 11: 21
22 IN CLK1 Positive Clock Skew FF1 Q1 [long wire] Combinational D2 CLK2 FF2 IN CLK1 Q1 D2 CLK2 (delayed) tskew tsetup Receiving FF receives clock later than sending FF t ffpd(max) + t comb(max) + t setup t clk + t skew(min) Beneficial skew for meeting setup time constraint Lecture 11: 22
23 Hold Time With Positive Clock Skew IN CLK1 FF1 Q1 Combinational D2 CLK2 FF2 [long wire] IN CLK1 Q1 D2 CLK2 (delayed) tskew thold (hold time window effectively widened) Receiving FF receives clock later than sending FF t ffpd(min) + t comb(min) t hold + t skew(max) Harmful skew for meeting hold time constraint Lecture 11: 23
24 Hold Time With Negative Clock Skew IN CLK1 D CLK Q Q1 Combinational D2 CLK2 D CLK Q [long wire] What if sending FF receives clock later than receiving FF? t ffpd(min) + t comb(min) t hold - t skew(min) Beneficial skew for meeting hold time constraint Lecture 11: 24
25 Example: Setup Analysis with Clock Skew FF1 combinational FF2 Clock may arrive at FF1 up to 1ns later than FF2 Prop Delay (ns) min max Setup Time (ns) Hold Time (ns) FF Comb What s the best achievable cycle time? t ffpd(max) + t comb(max) + t setup <= t clk - t skew(max) t clk >= = 20ns Lecture 11: 25
26 H&H , 5.5 Before Next Class Next Time Binary Arithmetic Lecture 11: 26
ENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis Overview Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation
More informationTiming Issues in FPGA Synchronous Circuit Design
ECE 428 Programmable ASIC Design Timing Issues in FPGA Synchronous Circuit Design Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 1-1 FPGA Design Flow Schematic capture HDL
More informationTiming analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
More informationINF3430 Clock and Synchronization
INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018
UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationLecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
More informationEC O4 403 DIGITAL ELECTRONICS
EC O4 403 DIGITAL ELECTRONICS Asynchronous Sequential Circuits - II 6/3/2010 P. Suresh Nair AMIE, ME(AE), (PhD) AP & Head, ECE Department DEPT. OF ELECTONICS AND COMMUNICATION MEA ENGINEERING COLLEGE Page2
More informationIn this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems.
1 In this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems. The important concepts are related to setup and hold times of registers
More informationWe ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits
Basic Timing Issues We ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits The fundamental timing issues we considered then apply
More information2014 Paper E2.1: Digital Electronics II
2014 Paper E2.1: Digital Electronics II Answer ALL questions. There are THREE questions on the paper. Question ONE counts for 40% of the marks, other questions 30% Time allowed: 2 hours (Not to be removed
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 4.2.1: Learn More Liang Liu liang.liu@eit.lth.se 1 Outline Crossing clock domain Reset, synchronous or asynchronous? 2 Why two DFFs? 3 Crossing clock
More informationUNIT II: Clocked Synchronous Sequential Circuits. CpE 411 Advanced Logic Circuits Design 1
UNIT II: Clocked Synchronous Sequential Circuits CpE 411 Advanced Logic Circuits Design 1 Unit Outline Analysis of Sequential Circuits State Tables State Diagrams Flip-flop Excitation Tables Basic Design
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More information6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form:
6.111 Lecture # 19 Controlling Position Servomechanisms are of this form: Some General Features of Servos: They are feedback circuits Natural frequencies are 'zeros' of 1+G(s)H(s) System is unstable if
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationECE 551: Digital System Design & Synthesis
ECE 551: Digital System Design & Synthesis Lecture Set 9 9.1: Constraints and Timing 9.2: Optimization (In separate file) 03/30/03 1 ECE 551 - Digital System Design & Synthesis Lecture 9.1 - Constraints
More informationUNIT-III ASYNCHRONOUS SEQUENTIAL CIRCUITS TWO MARKS 1. What are secondary variables? -present state variables in asynchronous sequential circuits 2. What are excitation variables? -next state variables
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory
More information1 Q' 3. You are given a sequential circuit that has the following circuit to compute the next state:
UNIVERSITY OF CALIFORNIA Department of Electrical Engineering and Computer Sciences C50 Fall 2001 Prof. Subramanian Homework #3 Due: Friday, September 28, 2001 1. Show how to implement a T flip-flop starting
More informationENGG1015: lab 3. Sequential Logic
ENGG1015: lab 3 Sequential Logic 1 st Semester 2012-13 This lab explores the world of sequential logic design. By the end of this lab, you will have implemented a working prototype of a Ball ounter that
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/3/28 6/3/28 Computer Engineering Basic Element for Sequential CircuitsSR Latch Latch Store one-bit information (two states of and ) Two inputs,
More informationTiming Verification of Sequential Domino Circuits
Timing Verification of Sequential Domino Circuits David Van Campenhout, Trevor Mudge, and Karem A. Sakallah Advanced Computer Architecture Laboratory EECS Department, University of Michigan Ann Arbor,
More informationEC4205 Microprocessor and Microcontroller
EC4205 Microprocessor and Microcontroller Webcast link: https://sites.google.com/a/bitmesra.ac.in/aminulislam/home All announcement made through webpage: check back often Students are welcome outside the
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationChapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1
Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates
More informationCSE 260 Digital Computers: Organization and Logical Design. Midterm Solutions
CSE 260 Digital Computers: Organization and Logical Design Midterm Solutions Jon Turner 2/28/2008 1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items blanked out.
More informationMux-Based Latches. Lecture 8. Sequential Circuits 1. Mux-Based Latch. Mux-Based Latch. Negative latch (transparent when CLK= 0)
Mux-Based Latches Lecture 8 equential Circuits Negative latch (transparent when = 0) Positive latch (transparent when = ) Peter Cheung epartment of Electrical & Electronic Engineering Imperial College
More informationCS/EE Homework 9 Solutions
S/EE 260 - Homework 9 Solutions ue 4/6/2000 1. onsider the synchronous ripple carry counter on page 5-8 of the notes. Assume that the flip flops have a setup time requirement of 2 ns and that the gates
More informationWinter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28
Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationDM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
August 1986 Revised February 1999 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The circuit is a synchronous, reversible, up/ down counter. Synchronous operation is provided by
More informationDM74ALS169B Synchronous Four-Bit Up/Down Counters
Synchronous Four-Bit Up/Down Counters General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B
More informationPage 1. Last time we looked at: latches. flip-flop
Last time we looked at: latches flip flops We saw that these devices hold a value depending on their inputs. A data input value is loaded into the register on the rise of the edge. Some circuits have additional
More informationDigital Circuits Laboratory LAB no. 12. REGISTERS
REGISTERS are sequential logic circuits that store and/or shift binary sequences. can be classified in: memory registers (with parallel load) - latch shift registers (with serial load) combined registers
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More informationBrought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.
Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector
More informationDM74AS169A Synchronous 4-Bit Binary Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169
More informationFan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationMetastability. 1
Metastability talarico@gonzaga.edu 1 Asynchronous Inputs Synchronous circuits can have asynchronous inputs Even a supposedly synchronous circuit like the D flip flop can have asynchronous inputs such as
More informationECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
More informationDESIGNING SEQUENTIAL LOGIC CIRCUITS
chapter7.fm Page 296 Friday, January 18, 2002 9:09 AM CHAPTER 7 ESIGNING SEUENTIAL LOGIC CIRCUITS Implementation techniques for flip-flops, latches, oscillators, pulse generators, and Schmitt triggers
More informationDESIGNING SEQUENTIAL LOGIC CIRCUITS
chapter7.fm Page 270 Tuesday, April 18, 2000 8:52 PM CHAPTER 7 ESIGNING SEUENTIAL LOGIC CIRCUITS Implementation techniques for flip-flops, latches, oscillators, pulse generators, and Schmitt triggers n
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit
Outline EES 5 - omponents and esign Techniques for igital Systems Lec 2 - Timing avid uller Electrical Engineering and omputer Sciences University of alifornia, erkeley Performance Limits of Synchronous
More informationFirst Name: Last Name: Lab Cover Page. Teaching Assistant to whom you are submitting
Student Information First Name School of Computer Science Faculty of Engineering and Computer Science Last Name Student ID Number Lab Cover Page Please complete all (empty) fields: Course Name: DIGITAL
More information1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as
BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationVLSI Design Verification and Test Delay Faults II CMPE 646
Path Counting The number of paths can be an exponential function of the # of gates. Parallel multipliers are notorious for having huge numbers of paths. It is possible to efficiently count paths in spite
More informationlogic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs
Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationSerial Addition. Lecture 29 1
Serial Addition Operations in digital computers are usually done in parallel because that is a faster mode of operation. Serial operations are slower because a datapath operation takes several clock cycles,
More information74F5074 Synchronizing dual D-type flip-flop/clock driver
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop/clock driver 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics Output skew guaranteed less than 1.5ns High source current
More informationEECS 270: Lab 7. Real-World Interfacing with an Ultrasonic Sensor and a Servo
EECS 270: Lab 7 Real-World Interfacing with an Ultrasonic Sensor and a Servo 1. Overview The purpose of this lab is to learn how to design, develop, and implement a sequential digital circuit whose purpose
More informationFinite State Machines CS 64: Computer Organization and Design Logic Lecture #16
Finite State Machines CS 64: Computer Organization and Design Logic Lecture #16 Ziad Matni Dept. of Computer Science, UCSB Lecture Outline Review of Latches vs. FFs Finite State Machines Moore vs. Mealy
More informationIES Digital Mock Test
. The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code
More informationSIMMAT A Metastability Analysis Tool
SIMMAT A Metastability Analysis Tool Simulation waveforms voltage d q Ian W. Jones and Suwen Yang, Oracle Labs, Mark Greenstreet, University of British Columbia clk time (ns) 1 November 2012 1 Outline
More informationLinear & Digital IC Applications (BRIDGE COURSE)
G. PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY Accredited by NAAC with A Grade of UGC, Approved by AICTE, New Delhi Permanently Affiliated to JNTUA, Ananthapuramu (Recognized by UGC under 2(f) and 12(B)
More informationI hope you have completed Part 2 of the Experiment and is ready for Part 3.
I hope you have completed Part 2 of the Experiment and is ready for Part 3. In part 3, you are going to use the FPGA to interface with the external world through a DAC and a ADC on the add-on card. You
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationComputer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part II First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Combinational Circuits Flips Flops Flops Sequential Circuits 204231: Computer
More informationEXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation)
EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation) PURPOSE The purpose of this experiment is to introduce you to schematic capture and logic simulation. Primarily, you
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More information74F50729 Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
INTEGRATED CIRCUITS Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics 1990 Sep 14 IC15 Data Handbook FEATURES Metastable immune characteristics
More informationAdvanced Digital Design
Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology Outline Skew versus consistency The need for a design style Hazards, Glitches & Runts Lecture "Advanced
More informationComputer Architecture (TT 2012)
Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture
More informationbus waveforms transport delta and simulation
bus waveforms transport delta and simulation Time Modelling and Data Flow Descriptions Modeling time in VHDL Different models of time delay Specify timing requirement Data flow descriptions Signal resolution
More informationClassification of Digital Circuits
Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational
More informationDM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters
DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting desig. The
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More informationDIGITAL ELECTRONICS: LOGIC AND CLOCKS
DIGITL ELECTRONICS: LOGIC ND CLOCKS L 9 INTRO: INTRODUCTION TO DISCRETE DIGITL LOGIC, MEMORY, ND CLOCKS GOLS In this experiment, we will learn about the most basic elements of digital electronics, from
More information54AC191 Up/Down Counter with Preset and Ripple Clock
54AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature
More informationModule 4: Combinational Logic Glitches and Hazards
Module 4: Combinational Logic Glitches and Hazards Wakerly: Chapter 4 (part 3) : ECEN 3233 r. Keith. Teague Spring 23 23 TIME RESPONSE in Combinational Networks emphasis on timing behavior of circuits
More information1/19/2012. Timing in Asynchronous Circuits
Timing in Asynchronous Circuits 1 What do we mean by clock? The system clock for an integrated circuit is a voltage signal that pulses at a regular frequency. 1 0 Time The clock tells each stage of a circuit
More informationController Implementation--Part I. Cascading Edge-triggered Flip-Flops
Controller Implementation--Part I Alternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time state: Divide and Counter Jump counters Microprogramming (ROM) based
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design : Conventions, Problems, Solutions Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally
More informationData Logger by Carsten Kristiansen Napier University. November 2004
Data Logger by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Data Logger. Education: Electronic and Computer Engineering.
More informationPerformance Comparison of Various Clock Gating Techniques
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 1, Ver. II (Jan - Feb. 2015), PP 15-20 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Performance Comparison of Various
More informationOBSOLETE. Digitally Programmable Delay Generator AD9501
a FEATURES Single 5 V Supply TTL- and CMOS-Compatible 10 ps Delay Resolution 2.5 ns to 10 s Full-Scale Range Maximum Trigger Rate 50 MHz APPLICATIONS Disk Drive Deskewing Data Communications Test Equipment
More informationB.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics
B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To
More informationECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice
ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit
More informationSpec. Instructor: Center
PDHonline Course E379 (5 PDH) Digital Logic Circuits Volume III Spec ial Logic Circuits Instructor: Lee Layton, P.E 2012 PDH Online PDH Center 5272 Meadow Estatess Drive Fairfax, VA 22030-6658 Phone &
More informationDIGITAL DESIGN WITH SM CHARTS
DIGITAL DESIGN WITH SM CHARTS By: Dr K S Gurumurthy, UVCE, Bangalore e-notes for the lectures VTU EDUSAT Programme Dr. K S Gurumurthy, UVCE, Blore Page 1 19/04/2005 DIGITAL DESIGN WITH SM CHARTS The utility
More informationPWM System. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff
PWM System 1 Pulse Width Modulation (PWM) Pulses are continuously generated which have different widths but the same period between leading edges Duty cycle (% high) controls the average analog voltage
More informationA Review of Clock Gating Techniques in Low Power Applications
A Review of Clock Gating Techniques in Low Power Applications Saurabh Kshirsagar 1, Dr. M B Mali 2 P.G. Student, Department of Electronics and Telecommunication, SCOE, Pune, Maharashtra, India 1 Head of
More informationUniversity of Toronto Faculty of Applied Science and Engineering. Digital Electronics. Winter Final Exam. Instructor: R.
University of Toronto Faculty of Applied Science and Engineering ECE 334 - Digital Electronics Winter 2017 Final Exam Instructor: R. Genov Duration: 150 minutes Closed book; A hand-written 8.5"xl1"one-page
More informationSN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 7: Phase Detector Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam
More informationCoincidence Rates. QuarkNet. summer workshop June 24-28, 2013
Coincidence Rates QuarkNet summer workshop June 24-28, 2013 1 Example Pulse input Threshold level (-10 mv) Discriminator output Once you have a digital logic pulse, you can analyze it using digital electronics
More informationMohit Arora. The Art of Hardware Architecture. Design Methods and Techniques. for Digital Circuits. Springer
Mohit Arora The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits Springer Contents 1 The World of Metastability 1 1.1 Introduction 1 1.2 Theory of Metastability 1 1.3 Metastability
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More informationHIGH-performance microprocessors employ advanced circuit
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 5, MAY 1999 645 Timing Verification of Sequential Dynamic Circuits David Van Campenhout, Student Member, IEEE,
More informationDesign for Testability & Design for Debug
EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin Agenda Why test? Scan: What is it?
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationExercises: Fundamentals of Computer Engineering 1 PAGE: 1
Exercises: Fundamentals of Computer Engineering PAGE: Exercise Minimise the following using the laws of Boolean algebra. f = a + ab + ab.2 f ( ) ( ) ( ) 2 = c bd + bd + ac b + d + cd a + b + ad( b + c)
More information