EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation)

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1 EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation) PURPOSE The purpose of this experiment is to introduce you to schematic capture and logic simulation. Primarily, you will use two tools from the company Cadence: Cadence Design Entry and Cadence AMS Simulator. In this experiment, two of those tools will be used: (1) Cadence Design Entry is used for schematic capture and (2) Cadence AMS Simulator is used for logic simulation. These Cadence tools run on the Dell PC computers. This experiment will familiarize you with some of the uses and limitations of logic simulators in modeling digital circuits. INTRODUCTION A logic simulator is a program that models the behavior of digital logic circuits. The simulator is given a description of the circuit and its input signals. From this information, it provides timing diagrams of outputs and internal signals in the circuit. Logic simulators are used to decrease the effort and time expended in the design and testing of logic circuits. More time and effort is then available for the construction and testing of actual circuits. Much less effort is required to edit logic diagrams with a schematic capture program and re-simulate the new circuit after changes are made than to rewire circuits and retest or to redo calculations in a manual simulation of the circuit. However, logic simulators do not fully model every aspect of practical logic circuits. For example, many logic simulators do not represent signals as continuous voltages, instead they model signals as being at one of two levels, either logic 1 or logic 0. In addition, most simulators do not account for such factors as power supply voltages, loading of the gates, gate temperature, logic family of the gates, etc., which are critical to the proper operation of practical logic circuits. The many nonideal characteristics of real logic circuits are often totally ignored. Hence, simulators cannot always be expected to reliably reflect a circuit's true behavior. In Appendix C you will find the operating procedures for the Cadence tools and also for the Dell PC computer on which they run. LOGIC SIMULATION As is usually the case, real world devices are afflicted with numerous anomalies not encountered in simple theory. Unfortunately, these anomalies materialize in virtually all aspects of practical circuit design. Logic simulators are an attempt to encompass the most important characteristics of real devices in order to make the design process easier. 2.1

2 The most significant anomaly, inherent in every design, is propagation delay. Every logic simulator makes an attempt to model this phenomenon and infer its consequences. It is unreasonable to expect that in any practical gate, changes in the inputs are reflected at the output instantaneously. The changes take time to propagate to the output. This propagation delay is a critical factor in practically all logic design, for it determines the maximum speed at which any circuit can operate. (See the discussion in Experiment 1 for a definition of some of delay parameters for gates.) Thus, the most important result of any logic simulator should be the signal levels of the outputs and internal nodes of the circuit at every instant of time, i.e., a timing diagram. From such timing diagrams, one can trace the longest signal propagation paths through the circuit in order to determine where more effort should be spent on shortening signal paths in the circuit to increase its operational speed. In addition, timing diagrams can be used to reveal glitches, which manifest themselves by erroneous output changes in combinational logic and improper state transitions in sequential circuits. (The possibility of these glitches can be determined by analyzing a circuit for hazards). Glitches will be studied in a later lab. Figure 2.1 Timing Diagrams for a NAND Gate. Figure 2.1 illustrates a timing diagram for a NAND gate with a propagation delay of 10 time units. (Both t PHL and t PLH are assumed to be 10 time units.) The two input signals, A and B, and the actual output signal CP are shown for a practical NAND gate. In addition, the theoretical signal CT generated by a theoretical idealized NAND gate with zero propagation delay is shown. The elevated lines correspond to logic 1 and the lowered lines to logic 0. Initially, the two input signals are HIGH and the theoretical and practical NAND gate outputs are low. (Recall that a NAND gate's output is LOW if and only if both of its inputs are HIGH.) At time 8, input A's signal goes low; hence, the theoretical NAND gate's output goes HIGH simultaneously. In the practical gate, however, this change in the input signal does not propagate to the output until

3 time units later, or at time 18. At time 12, input B's signal goes LOW and does not affect the NAND gate s output, which is already HIGH in the theoretical NAND gate and is in the process of going HIGH in the practical NAND gate. At time 16, input A's signal again goes HIGH; however, input B s signal is still LOW, so the output of the NAND gate is unaffected. At time 20, input B's signal also goes HIGH, and the theoretical NAND gate's output immediately goes LOW. The practical NAND gate's output doesn't go LOW until 10 time units later, at time 30. The remainder of the theoretical and practical NAND gates outputs are determined in a similar manner. However, note that at time 48, input B's signal goes HIGH while input A's signal, which is already HIGH, subsequently goes LOW at time 50. The theoretical NAND gate's output goes LOW from time 48 to 50 as a result. But the practical NAND gate's output does not reflect these input changes 10 time units later, at time 58 to 60. This phenomenon occurs because practical gates have an inertial delay time; this is the time that the input signals must remain stable before any change will be propagated to the output. After the required inertial delay time has been met, the output of the gate changes. Unless otherwise specified, the inertial delay time is equal to the gate propagation delay, so in the above example it is 10 time units. Obviously, timing diagrams are applicable not only to single gates, but also to entire networks of logic devices. Figure 2.2 illustrates the process one should use in analyzing a circuit containing more than one gate. Again, a propagation delay of ten time units is assumed. For simplicity, Figure 2.2 Timing Diagram Example of a Simple Circuit. 2.3

4 an inertial delay time equal to the propagation delay time has been assumed. Assuming the waveforms for inputs A, B, C and D are initially given, the waveforms for internal nodes E and F can then be derived. Subsequently, the waveform for output G can be determined. You should carefully analyze this example and be prepared to demonstrate your understanding of timing diagrams by generating them yourself. 2.4

5 PRELAB Before coming to the lab, you should thoroughly read through Appendix C describing the operation of the Dell PC computer and the Cadence Tools. Answer the following questions: 1. In Figure 2.2, why doesn't the output G go low at time 74, since both inputs to the gate are high during the time interval 64-66? 2. As mentioned in Appendix C, logic simulators do not "sample" signals continuously, instead the signals are examined at discrete points in time. This particular simulator is "event driven", which means that each time an event occurs a list is made of all devices whose inputs are affected by that event. Hence, a change in an input does not go undetected at the output. The situation is not the same with simulators that sample the signals only at specified intervals. In these simulators, any signal transitions that occur between these discrete sampling points go undetected until the next sampling period after the transition. Suppose the output signal G in Figure 2.2 is only sampled every 15 time units. Draw the simulator timing diagram for the output that would be generated by a simulator (not an event driven one) using this sampling rate. 3. Draw the timing diagram for the circuit below if the propagation delay of the gates is 5 time units? (The gates are NOR gates.) Repeat assuming the gate delays are 20 time units? Assume the inertial delay times are equal to the propagation delay times. A B C D E F G 2.5

6 5 unit propagation delay. 20 unit propagation delay. 2.6

7 4. Draw the actual timing diagram for the circuit below and the input changes given. Assume all gates have a propagation delay of 10 time units. Again assume the inertial delay time is the same as the propagation delay time. A B C F H D E G I 5. Determine the function realized by the circuit in Figure 2.3 below. Figure 2.3 Schematic Diagram of Logic Circuit to Be Simulated. 2.7

8 PROCEDURE Before performing the procedures listed below, read the report section of the experiment to assure you make all required measurements and record all required data. A. Introduction to the Dell PC 1. Familiarize yourself with the Dell PC and Windows software. If you do not understand the operation of a Dell PC or Windows, ask your TA for assistance. B. Creating a Schematic for Simulation Refer to Appendix C for instructions to do the following steps. 1. Open Cadence Design Entry CIS and create a new project. (It is good to have a separate project for each design or experiment, so you might want to designate the project as project2.) Create a schematic for the circuit of Figure 2.3. Label the inputs IN1 and IN2 as shown and label the output OUT. Make sure to add the input and output symbols (IN.1 and OUT.1). Also, label the internal nets (lines) at the outputs of the internal gates S2, S3, and S4 as indicated. 2. Use the Cadence AMS Simulator to simulate the circuit for the following three sets of changes on the inputs: (a) IN1 is 0 at time 0, changes to 1 at time 40ns, and changes back to 0 at time 140ns; IN2 is 0 at time 0, changes to 1 at time 20ns, and changes back to 0 at time 90ns. (b) IN1 is 0 at time 0, changes to 1 at time 40ns, and changes back to 0 at time 115ns; IN2 is the same as in part (a). (c) IN1 is 0 at time 0, changes to 1 at time 40ns, and changes back to 0 at time 100ns; IN2 is the same as in part (a). 3. Create a printout of the circuit schematic and the three waveform traces. (Note: You can capture the image of a single window by selecting it and performing Alt & Print Screen. Then the image can be pasted into a document, such as a WordPad document.) 2.8

9 EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation) FINAL REPORT Submit original copies of the printouts requested in part B.3. a). For the three simulations, sketch waveform traces for the ideal case of zero gate delays. Explain the differences between the waveforms you obtained from the simulation and the waveforms for ideal gates. 2.9

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