Unit 3 Digital Circuits (Logic)
|
|
- Mark Mathews
- 5 years ago
- Views:
Transcription
1 Unit 3 Digital Circuits (Logic) 1
2 2 A Brief History COMPUTERS AND SWITCHING TECHNOLOGY
3 3 Mechanical Computers Primarily gearbased Difference Engine and Analytic Engine designed and partially implemented by Charles Babbage Used mechanical levers, gears, and ball bearings, etc. Difference Engine (1823) prototype and not fully programmable Analytic Engine (1834) Never completed To be programmed with punch cards Designed to perform 4 basic arithmetic ops. (add, sub, mul, div) Charles Babbage and his Difference Engine
4 ENIAC was first, fully electronic computer Electronic Computers Used thousands of vacuum tubes as fundamental switching (on/off) technology Weighed 30 tons, required 15,000 square feet, and maximum size number was 10 decimal digits (i.e. ±9,999,999,999) Still required some patch panels (wire plugs) to configure it
5 5 Vacuum Tube Technology Digital, electronic computers use some sort of voltage controlled switch (on/off) Looks like a light bulb Usually 3 nodes 1 node serves as the switch value allowing current to flow between the other 2 nodes (on) or preventing current flow between the other 2 nodes (off) Example: if the switch input voltage is 5V, then current is allowed to flow between the other nodes A Switch Input (Hi or Lo Voltage) Current can flow based on voltage of input switch B Vacuum Tube
6 6 Vacuum Tube Disadvantages Relatively large Especially when you need 19,000 to make 1 computer Unreliable Can burn out just like a light bulb Dissipate a lot of heat (power)
7 7 Transistor Another switching device Invented by Bell Labs in 1948 Uses semiconductor materials (silicon) Much smaller, faster, more reliable (doesn't burn out), and dissipated less power Individual Transistors (About the size of your fingertip) Source Gate 5V Drain High voltage at gate allows current to flow from source to drain Source Gate 0V Silicon Drain Silicon Low voltage at gate prevents current from flowing from source to drain Transistor is 'on' Transistor is 'off'
8 8 Moore's Law & Transistors Moore's Law = Number of transistors able to be fabricated on a chip will double every years Transistors are the fundamental building block of computer HW Switching devices: Can conduct [on = 1] or notconduct [off = 0] based on an input voltage
9 9 How Does a Transistor Work Transistor inner workings
10 10 NMOS Transistor Physics Transistor is started by implanting two ntype silicon areas, separated by ptype ntype silicon (extra negative charges) Source Input Drain Input ptype silicon ("extra" positive charges)
11 11 NMOS Transistor Physics A thin, insulator layer (silicon dioxide or just "oxide") is placed over the silicon between source and drain Source Input Drain Output Insulator Layer (oxide) ntype silicon (extra negative charges) ptype silicon ("extra" positive charges)
12 12 NMOS Transistor Physics A thin, insulator layer (silicon dioxide or just "oxide") is placed over the silicon between source and drain Conductive polysilicon material is layered over the oxide to form the gate input Source Input Gate Input Drain Output conductive polysilicon Insulator Layer (oxide) ntype silicon (extra negative charges) ptype silicon ("extra" positive charges)
13 13 NMOS Transistor Physics Positive voltage (charge) at the gate input repels the extra positive charges in the p type silicon Result is a negativecharge channel between the source input and drain Source Input negativelycharge channel Gate Input positive charge "repelled" ptype Drain Output ntype
14 14 NMOS Transistor Physics Electrons can flow through the negative channel from the source input to the drain output The transistor is "on" Gate Input Source Input Drain Output ntype ptype Negative channel between source and drain = Current flow
15 15 NMOS Transistor Physics If a low voltage (negative charge) is placed on the gate, no channel will develop and no current will flow The transistor is "off" Gate Input Source Input Drain Output ntype ptype No negative channel between source and drain = No current flow
16 16 View of a Transistor Crosssection of transistors on an IC Moore's Law is founded on our ability to keep shrinking transistor sizes Gate/channel width shrinks Gate oxide shrinks Transistor feature size is referred to as the implementation "technology node" Electron Microscope View of Transistor CrossSection
17 DIGITAL LOGIC GATES 17
18 18 Transistors and Logic Transistors act as switches (on or off) A S1 S2 B Logic operations (AND / OR) formed by connecting them in specific patterns Series Connection Parallel Connection A Series Connection S1 AND S2 must be on for A to be connected to B S1 S2 Parallel Connection S1 OR S2 must be on for A to be connected to B B
19 19 Digital Logic Forms the basic processing circuits for digital signals (i.e. 1's and 0's) Digital Logic still abstracts many of the physical issues (voltage, current, parasitics, etc.) dealt with in the study of integrated circuits An alarm should sound if the key is in the ignition AND your seatbelt is NOT fastened If the voltage threshold sensor rises above 3 volts create a conductive channel to excite the ignition sensor Computer Architecture (Functional Blocks) Digital Logic Integrated Circuits (Transistors) OR
20 20 Gates Each logical operation (AND, OR, NOT) can be implemented in circuit form using the corresponding logic gate AND Gate OR Gate NOT Gate
21 21 AND Gates An AND gate outputs a '1' (true) if ALL inputs are '1' (true) Gates can have several inputs Behavior can be shown in a truth table (listing all possible input combinations and the corresponding output) X Y Z F X Y F X Y F=X Y F X Y Z F=X Y Z F input AND 3input AND
22 22 OR Gates An OR gate outputs a '1' (true) if ANY input is '1' (true) Gates can also have several inputs X Y Z F X Y F=XY F X Y F X Y Z F=XYZ F input OR 3input OR
23 23 NOT Gate A NOT gate outputs a '1' (true) if the input is '0' (false) Also called an "Inverter" X F X F F = X
24 24 NAND and NOR Gates Inverted versions of the AND and OR gate X Y NAND Z X Y NOR Z Z X Y Z X Y X Y Z X Y Z X Y Z X Y Z AND NAND OR NOR True if NOT ALL inputs are true True if NOT ANY input is true
25 25 XOR and XNOR Gates Exclusive OR gate. Outputs a '1' if either input is a '1', but not both. X Y Z X Y Z XOR XNOR Z X Y Z X Y X Y Z X Y Z True if an odd # of inputs are true = True if inputs are different True if an even # of inputs are true = True if inputs are same
26 26 Logic Example A B C 0 D F 1
27 27 Logic Example A B C 0 D F 0
28 28 Delay Example A B C 0 D Levels of Logic F 1 0 Change in D, C, or A must propagate through 4 levels of gates
29 29 Logical Operations Summary All digital circuits can be described using AND, OR, and NOT Note: You'll learn in future courses that digital circuits can be described with any of the following sets: {AND, NOT}, {OR, NOT}, {NAND only}, or {NOR only} Normal convention: 1 = true / 0 = false A logic circuit takes some digital inputs and transforms each possible input combination to a desired output values Triviaoftheday: The Apollo Guidance Computer that controlled the lunar spacecraft in 1969 was built out of 8,400 3input NOR gates. Inputs I 0 I 1 I 2 Logic Circuit O 0 O 1 Outputs
30 30 Sequential Devices (Registers) AND, OR, NOT, NAND, and other gates are known as combinational logic Outputs only depend on what the inputs are right now, not one second ago This implies they have no "memory" (can't remember a value) Sequential logic devices provide the ability to retain or "remember" a value by itself (even after the input is changed or removed) Outputs can depend on the current inputs, and previous states of the circuit (stored values.) Usually have a controlling signal that indicates when the device should update the value it is remembering vs. when it should simply remember that value This controlling signal is usually the "clock" signal
31 31 Registers Registers are the most common sequential device Registers sample the data input (D) on the edge of a clock pulse (CP) and stores that value at the output (Q) Analogy: Taking a picture with your digital camera when you press a button (clock pulse) the camera samples the scene (input) and remembers/saves it as a snapshot (output) Data Input (could be many bits) Clock pulse D CP Q Block Diagram of a Register Data Output (could be many bits) t = 0 ns t = 1 ns t = 5 ns t = 7 ns t = 10 ns The clock pulse (positive edge) here Clock pulse d(t) Some input value changing over time d(1) d(2) d(3) d(4) d(5) d(6) d(7) d(8) d(9) d(10) d(11) d(12) q(t) unk d(1) d(5) d(7) d(10) causes q(t) to sample and hold the current d(t) value
32 32 FlipFlops Flipflops are the building blocks of registers 1 Flipflop PER bit of input/output There are many kinds of flipflops but the most common is the D (Data) Flipflop (a.k.a. DFF) D Flipflop triggers on the clock edge and captures the Dvalue at that instant and causes Q to remember it until the next edge Positive Edge: instant the clock transition from low to high (0 to 1) PositiveEdge Triggered DFF Clock pulse d(t) Clock Signal D DFF CLK Q q(t) d(t) q(t)
33 33 Registers and Flipflops A register is simply a group of D flipflops that all trigger on a single clock pulse D0 D1 4bit Register D Q DFF D Q Q0 Q1 DFF CLK Q t1 D2 D Q Q2 Steady level of 0 or 1 0 Q t 1 Q t DFF Positive Edge D t D3 D Q Q3 CP DFF
34 34 Pulses and Clocks Registers need an edge to trigger We can generate pulses at specific times (creating an irregular pattern) when we know the data we want has arrived Other registers in our hardware should trigger at a regular interval For that we use a clock signal Alternating high/low voltage pulse train Controls the ordering and timing of operations performed in the processor 1 cycle is usually measured from rising/positive edge to rising/positive edge Clock frequency (F) = # of cycles per second Clock Period (T) = 1 / Freq. 1 (5V) 0 (0V) Clock Pulses Clock Signal 1 cycle Op. 1 Op. 2 Op GHz = 2.8*10 9 cycles per second = ns/cycle Processor
35 35 Combinational vs. Sequential Sequential logic (i.e. registers) is used to store values Each register is analogous to a variable in your software program (a variable stores a number until you need it) Combinational logic is used to process bits (i.e. perform operations on values Analogous to operators (,,*) in your software program
Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates
18.1 Spiral 1 / Unit 8 Transistor Implementations CMOS Logic Gates 18.2 Spiral Content Mapping Spiral Theory Combinational Design Sequential Design System Level Design Implementation and Tools Project
More informationOutcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates
18.1 18.2 Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand
More informationB.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics
B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To
More informationIntroduction (concepts and definitions)
Objectives: Introduction (digital system design concepts and definitions). Advantages and drawbacks of digital techniques compared with analog. Digital Abstraction. Synchronous and Asynchronous Systems.
More informationINTRODUCTION TO MOS TECHNOLOGY
INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor
More informationChapter # 1: Introduction
Chapter # : Randy H. Katz University of California, erkeley May 993 ฉ R.H. Katz Transparency No. - The Elements of Modern Design Representations, Circuit Technologies, Rapid Prototyping ehaviors locks
More informationCMOS Digital Logic Design with Verilog. Chapter1 Digital IC Design &Technology
CMOS Digital Logic Design with Verilog Chapter1 Digital IC Design &Technology Chapter Overview: In this chapter we study the concept of digital hardware design & technology. This chapter deals the standard
More informationECE/CoE 0132: FETs and Gates
ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will
More informationDigital Design and System Implementation. Overview of Physical Implementations
Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops
More informationComputer Architecture (TT 2012)
Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More informationSpiral Content Mapping. Spiral 1 / Unit 8. Outcomes DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates
18.1 18.2 Spiral ontent Mapping Spiral Theory ombinational esign Sequential esign System Level esign Implementation and Tools Project Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Performance
More informationLecture 3: Logic circuit. Combinational circuit and sequential circuit
Lecture 3: Logic circuit Combinational circuit and sequential circuit TRAN THI HONG HONG@IS.NAIST.JP Content Lecture : Computer organization and performance evaluation metrics Lecture 2: Processor architecture
More informationDesigning Information Devices and Systems II Fall 2017 Note 1
EECS 16B Designing Information Devices and Systems II Fall 2017 Note 1 1 Digital Information Processing Electrical circuits manipulate voltages (V ) and currents (I) in order to: 1. Process information
More informationIntroduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi.
Introduction Reading: Chapter 1 Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Why study logic design? Obvious reasons
More informationEMT 251 Introduction to IC Design
EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is
More informationChapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1
Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar
More informationReading. Lecture 17: MOS transistors digital. Context. Digital techniques:
Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward
More informationDesign cycle for MEMS
Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor
More informationDepartment of Electronics and Communication Engineering
Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of
More information420 Intro to VLSI Design
Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem
More informationLogic Design (Part 1) Transistors & Gates (Chapter 3)
Agenda next 3 weeks: Inside a microprocessor Logic Design (Part 1) Transistors & Gates (Chapter 3) Based on slides McGrawHill Additional material 2004/2005/2006 Lewis/Martin Additional material 2008 Roth
More informationDigital Systems Laboratory
2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing
More informationDigital Electronics Part II - Circuits
Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits
More informationPropagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPropagation Delay, Circuit Timing & Adder Design
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationDesign of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer
Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate
More informationIntroduction to Computer Engineering EECS 203 dickrp/eecs203/ Grading scheme. Review.
Introduction to Computer Engineering EECS 203 http://ziyang.eecs.northwestern.edu/ dickrp/eecs203/ Grading scheme Instructor: Robert Dick Office: 77 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298
More informationLecture Integrated circuits era
Lecture 1 1.1 Integrated circuits era Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:-
More informationBasic Logic Circuits
Basic Logic Circuits Required knowledge Measurement of static characteristics of nonlinear circuits. Measurement of current consumption. Measurement of dynamic properties of electrical circuits. Definitions
More informationLOGIC FAMILY LOGIC FAMILY
In computer engineering, a logic family may refer to one of two related concepts. A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using
More informationLOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.
LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationLogic diagram: a graphical representation of a circuit
LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate
More informationInvestigation on Performance of high speed CMOS Full adder Circuits
ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI
More informationLecture 4 - Digital Representations III + Transistors
Lecture 4 - Digital Representations III + Transistors Video: Seems like a natural extension from images no? We just have a new dimension (time) Each frame is just an image made up of pixels Display n frames
More informationUNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts.
UNIT III VLSI CIRCUIT DESIGN PROCESSES In this chapter we will be studying how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: N-diffusion P-diffusion
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple
More informationA HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY
A HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY Jasbir kaur 1, Neeraj Singla 2 1 Assistant Professor, 2 PG Scholar Electronics and Communication
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationCS61c: Introduction to Synchronous Digital Systems
CS61c: Introduction to Synchronous Digital Systems J. Wawrzynek March 4, 2006 Optional Reading: P&H, Appendix B 1 Instruction Set Architecture Among the topics we studied thus far this semester, was the
More informationVLSI Designed Low Power Based DPDT Switch
International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 8, Number 1 (2015), pp. 81-86 International Research Publication House http://www.irphouse.com VLSI Designed Low
More informationLab 2 Revisited Exercise
Lab 2 Revisited Exercise +15V 100k 1K 2N2222 Wire up led display Note the ground leads LED orientation 6.091 IAP 2008 Lecture 3 1 Comparator, Oscillator +5 +15 1k 2 V- 7 6 Vin 3 V+ 4 V o Notice that power
More informationTransistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
More informationAn introduction to Depletion-mode MOSFETs By Linden Harrison
An introduction to Depletion-mode MOSFETs By Linden Harrison Since the mid-nineteen seventies the enhancement-mode MOSFET has been the subject of almost continuous global research, development, and refinement
More informationGates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
More informationLow Power 8-Bit ALU Design Using Full Adder and Multiplexer
Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Gaddam Sushil Raj B.Tech, Vardhaman College of Engineering. ABSTRACT: Arithmetic logic unit (ALU) is an important part of microprocessor. In
More informationTransistors, Gates and Busses 3/21/01 Lecture #
Transistors, Gates and Busses 3/2/ Lecture #8 6.7 The goal for today is to understand a bit about how a computer actually works: how it stores, adds, and communicates internally! How transistors make gates!
More informationCourse Overview. Course Overview
Course Overview Where does this course fit into the Electrical Engineering curriculum? Page 5 Course Overview Where does this course fit into the Computer Engineering curriculum? Page 6 3 Course Content
More informationQUIZ. What do these bits represent?
QUIZ What do these bits represent? 1001 0110 1 QUIZ What do these bits represent? Unsigned integer: 1101 1110 Signed integer (2 s complement): Fraction: IBM 437 character: Latin-1 character: Huffman-compressed
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationField Programmable Gate Array
9 Field Programmable Gate Array This chapter introduces the principles, implementation and programming of configurable logic circuits, from the point of view of cell design and interconnection strategy.
More informationIntroduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.
More informationEE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng
EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html
More informationECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics
ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More informationFan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationLow Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique
Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique Mohd Shahid M.Tech Student Al-Habeeb College of Engineering and Technology. Abstract Arithmetic logic unit (ALU) is an
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More information0 A. Review. Lecture #16. Pipeline big-delay CL for faster clock Finite State Machines extremely useful You!ll see them again in 150, 152 & 164
CS61C L15 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #16 Representations of Combinatorial Logic Circuits CPS today! 2005-10-26
More informationLecture 0: Introduction
Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits
More information2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
More informationDigital Electronics Course Objectives
Digital Electronics Course Objectives In this course, we learning is reported using Standards Referenced Reporting (SRR). SRR seeks to provide students with grades that are consistent, are accurate, and
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationCS302 - Digital Logic Design Glossary By
CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital
More informationGates and and Circuits
Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More information3.1 There are three basic logic functions from which all circuits can be designed: NOT (invert), OR, and
EE 2449 Experiment 3 Jack Levine and Nancy Warter-Perez, Revised 6/12/17 CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 3
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Electric Circuits
Introduction to Digital Logic Missouri S&T University CPE 2210 Electric Circuits Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and
More information+1 (479)
Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS August 29, 2002 John Wawrzynek Fall 2002 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
More informationVLSI Design. Introduction
VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated
More informationFirst Optional Homework Problem Set for Engineering 1630, Fall 2014
First Optional Homework Problem Set for Engineering 1630, Fall 014 1. Using a K-map, minimize the expression: OUT CD CD CD CD CD CD How many non-essential primes are there in the K-map? How many included
More informationLecture 8. MOS Transistors; Cheap Computers; Everycircuit
Lecture 8 MOS Transistors; Cheap Computers; Everycircuit Copyright 2017 by Mark Horowitz 1 Reading The rest of Chapter 4 in the reader For more details look at A&L 5.1 Digital Signals (goes in much more
More informationLearning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES
26.1 26.2 Learning Outcomes Spiral 26 Semiconductor Material MOS Theory I underst why a diode conducts current under forward bias but does not under reverse bias I underst the three modes of operation
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More informationContents 1 Introduction 2 MOS Fabrication Technology
Contents 1 Introduction... 1 1.1 Introduction... 1 1.2 Historical Background [1]... 2 1.3 Why Low Power? [2]... 7 1.4 Sources of Power Dissipations [3]... 9 1.4.1 Dynamic Power... 10 1.4.2 Static Power...
More informationEECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations
EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationEECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies
EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationMICROPROCESSOR TECHNOLOGY
MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to
More informationDigital Logic Design ELCT 201
Faculty of Information Engineering and Technology Dr. Haitham Omran and Dr. Wassim Alexan Digital Logic Design ELCT 201 Winter 2017 Midterm Exam Second Chance Please tick the box of your major: IET MET
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationModule-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families
1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter
More information3. COMPARING STRUCTURE OF SINGLE GATE AND DOUBLE GATE MOSFET WITH DESIGN AND CURVE
P a g e 80 Available online at http://arjournal.org APPLIED RESEARCH JOURNAL RESEARCH ARTICLE ISSN: 2423-4796 Applied Research Journal Vol. 3, Issue, 2, pp.80-86, February, 2017 COMPARATIVE STUDY ON SINGLE
More informationBasic digital logic functions and gates
Basic digital logic functions and gates Digital logic functions and gates are the main blocks behind digital logic design. s and 1s combine to produce values that are generated by basic gates such as NOT,
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationPS 12b Lab 1c IV Curves
Names: 1.) 2.) 3.) PS 12b Lab 1c IV Curves Learning Goal: Understand I- V curves for ohmic and non- ohmic devices (light bulb, resistor, Light Emitting Diode (LED), and Thermistor. Work with a Field Effect
More information5. (Adapted from 3.25)
Homework02 1. According to the following equations, draw the circuits and write the matching truth tables.the circuits can be drawn either in transistor-level or symbols. a. X = NOT (NOT(A) OR (A AND B
More informationFigure.1. Schematic of 4-bit CLA JCHPS Special Issue 9: June Page 101
Delay Depreciation and Power efficient Carry Look Ahead Adder using CMOS T. Archana*, K. Arunkumar, A. Hema Malini Department of Electronics and Communication Engineering, Saveetha Engineering College,
More information