Transistors, Gates and Busses 3/21/01 Lecture #

Size: px

Start display at page:

Download "Transistors, Gates and Busses 3/21/01 Lecture #"

Hilary Woods
5 years ago
Views:

1 Transistors, Gates and Busses 3/2/ Lecture #8 6.7 The goal for today is to understand a bit about how a computer actually works: how it stores, adds, and communicates internally! How transistors make gates! How gates make useful elements like memory and adders! How information is communicated within a computer NB: Models today are in some cases simplified - this is how it works in principle, not necessarily in exact detail Fesq, 3/9/ 6.7

2 Learning Objectives Students should be able to! Explain TTL logic! Identify how gates are made! Explain how gates produce useful elements! Discuss data busses and their operation Fesq, 3/9/ 2 6.7

3 Silicon (The material, not the Valley) Silicon is the basis for (almost) all modern electronics! It is a semi-conductor -- it has resistance midway between conductors and insulators! Each Si atom has 4 covalent bonds to neighbors! It can be doped by adding similar, but not identical atoms Molecules with 5 outer electrons (e.g., arsenic) brings an extra electron which is somewhat free - an n-type Molecules with 3 outer electrons (e.g., boron) brings a deficit of an electron (a hole) - a p-type Both types are electrically neutral but have mobile electrons and holes - free charge carriers Fesq, 3/9/ 3 6.7

4 P-N Junctions Make Diodes P and n material are "placed" next to one another Some holes in p diffuse toward n, and some electrons in n diffuse toward p The electrons and holes combine, creating a depletion region with no free charge carriers Due to loss of holes and electrons, p- now has a net negative charge, n- has a net positive charge! Now there is a potential difference (.6V), which prevents any further charge motion! This blocks any current flow -- like an insulator Fesq, 3/9/ 4 6.7

5 P-N Junctions If an external voltage is connected (+) to p, (-) to n, the free charge carriers are attracted as shown, collapsing the depletion region " current can flow! Current will increase with increasing voltage! This is forward bias Fesq, 3/9/ 5 6.7

6 n-p-n Junctions Make TTL Transistors A bipolar transistor consists of n-p-n collector-base-emitter. This is transistor-transistor logic (TTL) Fesq, 3/9/ 6 6.7

7 TTL Operation A TTL device operates in one of three modes! When V in "Low" (near ), the base-emitter junction is "closed," no current flows (cut off), and V out goes Hi towards V cc (+5V) - this is a low V in high V out switch! When V B gets towards.6v, the base-emitter junction is forward biased, and current flows -- the larger V in the larger I c - this is a linear amplifier! When V in gets sufficiently large, I c is large enough that most of the voltage drop occurs across R c, so V out goes low- this is a a high V in low V out switch +5V Rc Ic Vout Vin collector base emitter Fesq, 3/9/ 7 6.7

8 TTL Logic For positive logic, High is defined as, Low is defined as! For TTL in: > 2.V is High, <.8V is Low! For TTL out: > 2.4V is High, <.4V is Low! Transition Status is undefined Vout What Logical gate does this represent? Other common Logics are ECL (Emitter-Coupled Logic) and CMOS/FET (Complementary Metal-Oxide Semiconductor/Field Effect Transistor) - choice is made based on speed, power drain 5 Hi Lo Lo Hi Vin Fesq, 3/9/ 8 6.7

9 Logic to Gates built of TTL Useful gates can be built up out of Transistors and Resistors The fundamental TTL gate is a NAND, made up (in principle) of two transistors!(v in ) or (V in2 ) or (V in and V in2 ) Low Current through R flows to emitter. Collector of T drawn Lo No current through T 2, V out High! V in and V in2 High Collector of T High Current flows through T 2, V out Low Vin TWO-EMITTER TRANSISTOR T E Vin2 +5V B R C T2 B +5V C E RC Vout Fesq, 3/9/ 9 6.7

10 Voltage Table and Truth Table What is truth table? V V 2 V out x y z LO LO LO HI # HI LO Positive HI HI logic x y z NAND Fesq, 3/9/ 6.7

11 Real Tri-State NAND Real NAND gates have more components and one more function +5V! OE (Output Enable) causes the output to be specified by the gate when the OE is High OE IN IN2 T2 Vout! Allows the output to float (i.e., be set by other devices hanging on the same output line) when OE is low OE IN IN 2 OUT Gate 2 ALL ALL FLOAT Gate 3 Vout x z y OE Fesq, 3/9/ 6.7

12 NAND is a Logical Building Block Other gates can be built up from NAND's (and NOR's) NOT: x z x z AND: x y z =x y x y z OR: x y Not necessarily the most efficient way, but gates could be built up this way So how many transistors (on average) to a gate? How many gates to a modern processor/memory chip? z =x + y Transistor " NAND " All Gates x y z Fesq, 3/9/ 2 6.7

13 Adding The basic function of the Arithmetic Logic Unit is to add Half Adder can add two one-digit binary numbers Input Bits + DECIMAL BINARY AND XOR BINARY = 2 DECIMAL Fesq, 3/9/ 3 6.7

14 Full Adder Full Adder is needed when there is a result to carry over Modern processors have 32 full adders in ALU Fesq, 3/9/ 4 6.7

15 Writing to Static RAM (Random Access Memory) In order to store a piece of digital information to memory, 3 functional inputs are required we! The address to which you write (A)! The information you write (x in )! The command signals that instruct the memory write When we (write enable) goes high, writes 3 ( 2 ) to address 2 ( 2 ) and latches address A address decoder () () () () a3 a2 a a x3 din dout din dout L L () () () () x2 etc. x Data in, out (din, dout) x Numbers in () are example Fesq, 3/9/ 5 6.7

16 Details of RAM Write Need a few more functions to make this write cycle work! Address decoder, which reads a digital address, and activates a single address line! A latch, which when the data appears at its input, and the proper clock stroke is activated, latches or stores the bit until told to do otherwise (more in next lecture)! The timing and control signals to drive the "write enable" (we) Fesq, 3/9/ 6 6.7

17 Read/Write Timing and Control The computer is synchronized by a master clock, which establishes the clock cycle and its associated clock strobe (CS) During certain specified clock cycles, write to RAM is enabled (WE). During all other clock cycles, read from memory is enabled din we dout Tri-state gate! Din CS Dout WE re! Timing for write Timing for read CS CS A address valid A address valid Din WE data valid write Dout data valid Fesq, 3/9/ 7 6.7

18 Communication The processor/alu communicates with memory (and all other devices internal to the computer) via an internal bus The information transfer function on the bus is driven by memory transfer! Address! Data! Control All internal busses are parallel; i.e., there is a line for each bit of address, each bit of data, and each type of control signal Within these common features, there is a great deal of variance - "width" of bus (what # of bits can be transmitted simultaneously), address space, speed/timing, and sophistication of commanding CS WE address data commands Fesq, 3/9/ 8 6.7

19 Parallel Internal Busses Handyboard Memory and CPU schematic Fesq, 3/9/ 9 6.7

20 Bus Control and Protocols Typically one device on the bus is the controller, which maintains the master clock, and issues instructions All other devices hang on the bus, and listen to the controller, responding to instructions The combination of the device driver software is the CPU CPU RAM Disk controller plus the hardware that hangs on the bus allows the CPU to transfer information to and from a wide variety of devices transparently Other busses connect to peripherals (next time) A/D (Analog to Digital ) conversions and D/A (Digital to Analog) allow communication with analog world (next time) Disk Peripheral interface Peripheral A/D analog in D/A analog out address data commands Fesq, 3/9/ 2 6.7

21 Summary The world runs on aluminum and silicon, the latter being the basis for semiconductors, which are built up into gates Gates are the building blocks for adders, stacks, memories, etc. which form devices (CPU, ALU, RAM, ) Devices communicate command, address and data via busses Note Issue: Length of time to do problem sets Fesq, 3/9/ 2 6.7

420 Intro to VLSI Design

Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem