Basic digital logic functions and gates

Transcription

1 Basic digital logic functions and gates Digital logic functions and gates are the main blocks behind digital logic design. s and 1s combine to produce values that are generated by basic gates such as NOT, NAND and NOR. The NOT gate is often called inverter. NOT, NAND and NOR functions represent the fundamental operations in digital logic 1. A set of so-called truth tables is necessary to illustrate them. Basic digital logic functions A and B are two independent inputs. When they combine, each function produces a specific outcome. NOT flips the value of an input, NAND produces a when both inputs are 1 and NOR produces a 1 when both inputs are. The gates that follow are implemented with CMOS technology. The expressions for NOT, NAND and NOR are A, A B and A B respectively. NOT inverts A. NAND inverts the multiplication of A and B. NOR inverts the summation of A and B. The bar on top of each expression indicates the inversion and it has the lowest priority in the operation. A function is uniquely defined although there could be several implementations. A schematic is used to show the physical implementation of a specific function. A symbol is uniquely associated to each function. A set of waveforms is generated to verify the correct logic has been obtained. A layout can be produced for circuit fabrication of the specific function. Except for the inverter, the gates that follow have only two inputs. More inputs can be available. However, a gate with a higher number of inputs has more capacitance and therefore lower speed. Therefore, it is important to keep the number of gate inputs low. 1 This is also true for CMOS since NAND and NOR have less hardware than AND and OR. 1

2 NOT The NOT function has the following truth table: The schematic for the NOT gate is: NOT function 1 5dc M2 OFFTIME = 1nS ONTIME = 1nS CLK DELAY = STARTL = 1 OPPL = M1 IRFP9141 IRFP253 NOT schematic Two MOSFETS are stacked on top of each other. The PMOS is at the top and the NMOS is at the bottom. The body of the PMOS is connected to DD and the body of the NMOS is connected to GND (this is a common design solution that attempts to reduce recombination within the substrates of the devices). 2

3 The symbol for the NOT gate is: 1 2 NOT symbol The symbol looks like a triangle with a bubble in front of it. The circle is there to point out that the block performs inversion at the output. The waveforms for the NOT gate are: s 2ns 4ns 6ns 8ns 1ns 12ns 14ns 16ns 18ns 2ns (:1) (M1:d) Time NOT waveforms The transient response for the inverter shows what the circuit produces when it is excited by a voltage source. On the left, when the input is low, the output is high. On the right, when the input is high, the output is low. The transistors have the following characteristics: W p =1µ, L p =2µ, tpo =-.7, C bdp =2.293pF, C gspo =818.1pF, C gdpo =511.3pF W n =1µ, L n =2µ, tno =+.7, C bdn =4.368pF, C gsno =1.329pF, C gdno =496pF 3

4 The layout for the NOT gate is shown below: NOT layout The layout for the inverter consists of a PMOS (upper right), an NMOS (lower right), DD (upper rail), GND (lower rail), ptap (upper left), ntap (lower left), metal1 lines (blue) and polysilicon (red). The input is the polysilicon (gates of NMOS and PMOS). The output is the vertical metal1 line (connection between drain of NMOS and source of PMOS). A low voltage at the input turns off the NMOS and turns on the PMOS. In this condition, the PMOS passes a high voltage to the output. This is how voltage is inverted and this is why the above circuit is called an inverter. Note: the NOT gate consists of only 2 transistors. 4

5 NAND The NAND function has the following truth table: The schematic for the NAND gate is: NAND function 1 5dc M3 M4 IRFP9141 IRFP9141 M1 IRFP253 OFFTIME = 1nS ONTIME = 1nS CLK DELAY = STARTL = 1 OPPL = M2 IRFP253 OFFTIME = 2nS ONTIME = 2nS CLK DELAY = STARTL = 1 OPPL = NAND schematic The circuit can be split in two sections. The bottom section consists of two NMOS transistors which are stacked on top of each other. The top section consists of two PMOS transistors which are placed in parallel. 5

6 The symbol for the NAND gate is: NAND symbol The symbol looks like a bell with a circle in front of it. The circle is there to point out that the block performs inversion at the output. The waveforms for the NAND gate are: () () 2.5 SEL>> s 5ns 1ns 15ns 2ns 25ns 3ns 35ns 4ns (M4:d) Time NAND waveforms The transient response for the NAND shows what the circuit produces when it is excited by a voltage source., 1, 1 and 11 inputs will produce 1, 1, 1 and outputs respectively. The transistors have the following characteristics: W p =1µ, L p =2µ, tpo =-.7, C bdp =2.293pF, C gspo =818.1pF, C gdpo =511.3pF W n =1µ, L n =2µ, tno =+.7, C bdn =4.368pF, C gsno =1.329pF, C gdno =496pF 6

7 The layout for the NAND gate is shown below: NAND layout The layout for the NAND gate consists of two PMOS transistors (upper right), two NMOS transistors (lower right), DD (upper rail), GND (lower rail), ptap (upper left), ntap (lower left), metal1 lines (blue) and polysilicon (red). The inputs are the polysilicon lines (gates of NMOS and PMOS transistors). The output is the metal1 line that starts in the middle of the PMOS region and ends on the right of the NMOS region (connection between drain of the top NMOS and sources of the PMOS transistors). The PMOS transistors are effectively in parallel (the drains overlap and the sources are connected to DD). The NMOS transistors are placed in series (the source of the top NMOS overlaps with the drain of the bottom NMOS). Overlapping of transistors is done to reduce space and capacitance. Note: the NAND gate consists of 4 transistors. 7

8 NOR The NOR function has the following truth table: The schematic for the NOR gate is: NOR function 1 5dc M3 IRFP9141 OFFTIME = 1nS ONTIME = 1nS CLK DELAY = STARTL = 1 OPPL = OFFTIME = 2nS ONTIME = 2nS CLK DELAY = STARTL = 1 OPPL = M4 IRFP9141 M1 M2 IRFP253 IRFP253 NOR schematic The circuit can be split in two sections. The top section consists of two PMOS transistors which are stacked on top of each other. The bottom section consists of two NMOS transistors which are placed in parallel. 8

9 The symbol for the NOR gate is: NOR symbol The symbol looks similar to a bell with a circle in front of it. The circle is there to point out that the block performs inversion at the output. The waveforms for the NOR gate are: () () 2.5 SEL>> s 5ns 1ns 15ns 2ns 25ns 3ns 35ns 4ns (M1:d) Time NOR waveforms The transient response for the NOR shows what the circuit produces when it is excited by a voltage source., 1, 1 and 11 inputs will produce 1,, and outputs respectively. The transistors have the following characteristics: W p =1µ, L p =2µ, tpo =-.7, C bdp =2.293pF, C gspo =818.1pF, C gdpo =511.3pF W n =1µ, L n =2µ, tno =+.7, C bdn =4.368pF, C gsno =1.329pF, C gdno =496pF 9

10 The layout for the NOR gate is shown below: NOR layout The layout for the NOR gate consists of two PMOS transistors (upper right), two NMOS transistors (lower right), DD (upper rail), GND (lower rail), ptap (upper left), ntap (lower left), metal1 lines (blue) and polysilicon (red). The inputs are the polysilicon lines (gates of NMOS and PMOS transistors). The output is the metal1 line that starts on the right of the PMOS region and ends in the middle of the NMOS region (connection between drains of NMOS transistor and the source of the bottom PMOS transistors). The NMOS transistors are effectively in parallel (the drains overlap and the sources are connected to GND). The PMOS transistors are placed in series (the drain of the top PMOS overlaps with the source the bottom PMOS). Overlapping of transistors is done to reduce space and capacitance. Note: the NOR gate consists of 4 transistors. 1