ECE 3160 DIGITAL SYSTEMS LABORATORY

Transcription

1 ECE 3160 DIGITAL SYSTEMS LABORATORY Experiment 2 Voltage and Current Characteristics of HC Device Electronics Reference: Wakerly chapter 3. Objectives: 1. To measure certain performance and voltage/current properties of a typical HC gate. 2. To read and verify a HC IC data sheet. Background: High speed Complementary metaloxide semiconductor (HC) logic packages are available with varying speeds and performance parameters. The propagation delay indicates how long it takes for an input voltage change to cause a corresponding change in the output voltage. This time delay can be different for a change from hightolow (HL) than from lowtohigh (LH) for other families such as (TTL). Other important characteristics of a HC device include those of voltage limitations. Each HC device has voltage levels that control its corresponding logic levels; it is important to have a reasonable voltage noise margin to assure that small variations in voltage do not change the logic of the circuit. The ideal HC gate would be able to drive ideal logic voltage levels to any number of HC gates. However, a single gate can only source or sink a finite amount of current to a limited number of gates. The respective fanouts of each gate are very important to a digital engineer. Understanding the limits of HC logic is important to a successful digital design. And the amount of current a single output is able to supply to a load plays a vital role in the voltage level of the HC device due to its internal resistances; this in turn affects the logic of the circuit. Prelab: 1. Read Wakerly sections: 4 th Edition: 3.3.1, 3.6.2, Become familiar with the lab procedure below. Equipment: Function generator (FG) Oscilloscope (scope) Connecting cables Digital/Analog Trainer HP Triple output power supply Multimeter 7404 hex inverter IC Resistor substitution box 1

2 Part 1: Measure the propagation delays t phl and t plh of a 7400series HC SSI IC: 1. Using the pin layout printout found at each table, set up the circuit shown in Figure 1 on the Digital/Analog Trainer breadboard. 2. Connect CH1 of the scope to the input of the inverter (Pin 1) and the OUTPUT of the function generator. Turn on the function generator and adjust for a HC level 1 khz square wave with no DC offset (i.e. 0 to 4 V). 3. Connect CH2 of the scope to the output of the inverter (Pin 2). 4. Turn the vertical position knobs of both CH1 & CH2 on the scope such that their 0V markers coincide with one another. 5. To measure the propagation delay for an output transition from high to low (t phl ), align where the rising edge of the input trace (CH1) reaches approximately 2.5 V with the Yaxis of the oscilloscope using the horizontal position knob and trigger. 6. Observe the gate propagation delay measured from the 2.5 V threshold of the input pulse to the 2.5 V threshold of the inverter output. Make sure that the time per division scale is as great as possible. 7. Measure and record this hightolow propagation delay, t phl, using the gridlines on the oscilloscope and the known Sec/Div value. Change the horizontal scale for sufficient resolution for accurate measurement. Sketch both waveforms, marking pertinent time and voltage measurements. Show to the Lab TA. 8. To measure the propagation delay for a transition from low to high (t plh ), align where the falling edge of the input trace (CH1) reaches approximately 2.5 V with the Yaxis of the oscilloscope using the horizontal position knob and trigger. 9. Observe the gate propagation delay measured from the 2.5 V threshold of the input pulse to the 2.5 V threshold of the inverter output. 10. Measure and record this lowtohigh propagation delay, t plh, using the gridlines on the oscilloscope and the known Sec/Div value. Change the horizontal scale for sufficient resolution for accurate measurement. Sketch both waveforms, marking pertinent time and voltage measurements. Show to the Lab TA. Pulse Generator GND Figure 1. Part 2: Measure highlevel threshold voltage (V IHmin ) and lowlevel threshold voltage (V ILmax ) of a 7400series HC SSI IC: 1. Turn off the power to the test circuit and replace the function generator with the 6 V section of the HP power supply in order to apply a DC signal to the input of the inverting gate (see Figure 2). Note: Make sure the power supply is not energized upon connection. 2. Make sure METER selection switch is in the 6 V position and adjust the 2

3 VOLTAGE 6 V knob to its full counterclockwise position (in other words, make sure the output of the supply is 0 VDC). 3. Connect the scope s CH1 probe to the output of the test circuit and measure the input s DC voltage level with the multimeter. 4. Turn on the power to the test circuit and the power supply. 5. Slowly increase the DC voltage at the test circuit s input while watching the inverter s output for a voltage less than 4.4 V. HC devices typically have a V OHmin of 4.4 V, therefore, the V ILmax of the device can be estimated as the measured value of the respective input voltage (record this from the multimeter). Show to the Lab TA. 6. Continue increasing the input DC voltage while watching the inverter s output for a voltage less than 0.1 V. HC devices have a V OLmax of 0.1 V, therefore, the V IHmin for the device can be estimated as the measured value of the respective input voltage (record this from the multimeter). Show to the Lab TA. HP Supply GND Figure 2. Part 3: Measure the input current of a 7400series HC SSI IC at both a highlevel (I IH ) and lowlevel (I IL ). 1. Set up the circuit shown in Figure 3 with one (U1b) gate connected to the output of through a multimeter set to measure amperage. Apply a low logic level to the input of using one of the data switches on the test board and measure the voltage V in and current I in at the input of U1b. Note the voltage at node V in (V IH ) and the current through the ammeter I in (I IH ). 2. Apply a high logic level to the input of using one of the data switches on the test board and measure the voltage at node V in and current I in at the input of U1b. Note: these values represent V IL and I IL. 3. Repeat steps 1 and 2 of Part 2, first with two gates (U1b and U1c) connected at node V in and then with three gates (U1b, U1c, and U1d) connected at node V in. Make a table with V IH, I IH, V IL, I IL per every circuit instance (3 cases). Show to the Lab TA. 3

4 5V I in U1b V in U1c U1d Note: Circuit built into Digital Trainer Figure 3. Part 4: Measure the output current of a 7400series HC SSI IC into a resistive load at both a highlevel (I OH ) and lowlevel (I OL ). 1. Set up the circuit shown in Figure 4a. Use a decade resistance substitution box to implement R up. Begin with a pullup resistor value R up =100 KΩ. Apply a high logic level using data switch. Measure the voltage V out of and the current I out. Note V out (V OL ) and I out (I OL ) for the given R up value and record in a table. Apply a low logic level using a data switch. Again, measure the voltage V out of and the current I out. Note V out (V OH ) and I out (I OH ) for the given R up value and record in a table. Repeat the above process for R up = 5.1 KΩ, 1 KΩ, 220 Ω, 100 Ω, and 47 Ω. Show to the Lab TA. 5V 5V R up I out V out Figure 4a. 2. Set up the circuit shown in Figure 4b. Use a decade resistance substitution box to implement R dn. Begin with a pulldown resistor value R dn =100 KΩ. Apply a high logic level using data switch. Measure the voltage V out of and the current I out. Note V out (V OL ) and I out (I OL ) for the given R dn value and record in a table. Apply a low logic level using a data switch. Again, measure the voltage V out of and the current I out. Note V out (V OH ) and I out 4

5 (I OH ) for the given R dn value and record in a table. Repeat the above process for R dn = 5.1 KΩ, 1 KΩ, 220 Ω, 100 Ω, and 47 Ω. Show to the Lab TA. 5V I out V out R dn Figure 4b. Lab report questions: 1. Why is important to know the propagation delay of a device? State the values of the HightoLow propagation delay and LowtoHigh propagation delay you measured in Part Given both the t phl and t plh measured in the experiment what is the most conservative estimate of maximum system operating frequency. 3. What were the measured logic threshold values measured in Part 2? What would happen if an input signal was right at the threshold and noise was added to the signal? 4. The datasheet might imply that there is a band of input values between V IHmin and V OHmax that cause indefinite output voltages at the gate. How is this different from what you measured in the lab? Is the band of instability broad or narrow. 5. Assuming that all the loads (7404 inputs) consistently drew the average amount of current you measured per load in Part 3, how many inputs (overall fanout) could you connect to the output of the gate, without violating the device maximum output current specifications from the 7404 datasheet? 6. On the same graph, plot V out vs. I out curves for the set of different resistor values for both circuit configurations from the tables you made in Part 4 (one curve for each section of Part 4, giving 4 curves all together; e.g. plot one curve of V OH vs. I OH for all R up values). On the V out axis, mark V OHmin and V OLmax and on the I out axis, mark I OHmax and I OLmax. Approximate the minimum and maximum values of the pullup (R up ) and pulldown (R dn ) resistors possible for proper operation, without violating the device output voltage specifications. 7. Use the plot in question 7 to estimate I OHmax and I OLmax, i.e., the maximum current supplied for valid HC voltage levels. Using these estimates, and the average input current values from Part 1, calculate the overall fanout for your Is this a suitable design value? Explain. 8. Search for a datasheet for the 74HC04 part. Attach it to your report. Compare each of the measured experimental results with the device s typical and min/max values on the attached datasheet. Are any considerably different? Does this seem reasonable? Explain. 5