Outline. CPE/EE 422/522 Advanced Logic Design L02. Review: Combinational-Circuit Building Blocks. Multiplexers: 2-to-1 Multiplexer
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1 Outline CPE/EE 422/522 Avance Logic Design L2 Electrical an Computer Engineering University o Alabama in Huntsville What we know Laws an Theorems o Boolean Algebra Simpliication o Logic Epressions Using Laws an Theorems o Boolean Algebra or Using Kmaps Design Using only NAND or only NOR gates Tristate buers Basic Combinational Builing Blocks Multipleers, Decoers, Encoers,... What we o not know Hazars in Combinational Networks How to implement unctions using ROMs, PLAs, an PALs Sequential Networks (i time) 2/6/23 UAHCPE/EE 422/522 AM 2 Review: CombinationalCircuit Builing Blocks Multipleers Decoers Encoers Coe Converters Comparators Aers/Subtractors Multipliers Shiters Multipleers: 2to Multipleer Have number o ata inputs, one or more select inputs, an one output It passes the signal value on one o ata inputs to the output s w w s (a) Graphical symbol s w w w (c) Sumo proucts circuit = s' w + sw w (b) Truth table 2/6/23 UAHCPE/EE 422/522 AM 3 2/6/23 UAHCPE/EE 422/522 AM 4 Review: Synthesis o Logic Functions Using Mues w w 2 w 3 w w 2 (a) Moiie truth table w 3 w3 2/6/23 UAHCPE/EE 422/522 AM 5 w 3 w 2 w (b) Circuit Decoers: nto2 n Decoer Decoe encoe inormation: n inputs, 2 n outputs I En =, only one output is asserte at a time Onehot encoe output n inputs mbit binary coe where eactly one bit is set to Enable w w n En y y 2 n 2 n outputs y = wn '... w ' w' En y = wn '... w ' wen y2 = wn '... ww ' En... y n = wn... ww En 2 2/6/23 UAHCPE/EE 422/522 AM 6
2 Decoers: 2to4 Decoer Encoers En w w y y y 2 y 3 (a) Truth table w y w y y 2 En y 3 w w En y y y 2 y 3 Opposite o ecoers Encoe given inormation into a more compact orm Binary encoers 2 n inputs into nbit coe Eactly one o the input signals shoul have a value o, an outputs present the binary number that ientiies which input is equal to Use: reuce the number o bits (transmitting an storing inormation) (b) Graphic symbol (c) Logic circuit 2 n inputs w w 2 n y y n n outputs 2/6/23 UAHCPE/EE 422/522 AM 7 2/6/23 UAHCPE/EE 422/522 AM 8 Encoers: 4to2 Encoer Encoers: Priority Encoers w 3 w 2 w w y (a) Truth table y w w y w 2 w y 3 (b) Circuit Each input has a priority level associate with it The encoer outputs inicate the active input that has the highest priority (a) Truth table or a 4to2 priority encoer w 3 w 2 w w y y z 2/6/23 UAHCPE/EE 422/522 AM 9 2/6/23 UAHCPE/EE 422/522 AM Coe Converters Convert rom one type o input encoing to a ierent output encoing E. g., BCDto7segment ecoer w w w 2 w 3 a b c e (a) Coe converter g e a g (b) 7 segment isplay b c w 3 w 2 w w a b c e g Hazars in Combinational Networks What are hazars in CM? Unwante switching transients at the output (glitches) Eample ABC =, B changes to Assume each gate has propagation elay o ns (c) Truth table 2/6/23 UAHCPE/EE 422/522 AM 2/6/23 UAHCPE/EE 422/522 AM 2 2
3 Hazars in Combinational Networks Occur when ierent paths rom input to output have ierent propagation elays Static hazar a network output momentarily go to the when it shoul remain a constant Static hazar a network output momentarily go to the when it shoul remain a constant Dynamic hazar i an output change three or more times, when the output is suppose to change rom to ( to ) 2/6/23 UAHCPE/EE 422/522 AM 3 AB C Hazars in Combinational Circuits = AB' + BC AB C 2/6/23 UAHCPE/EE 422/522 AM 4 = AB' + BC + AC To avoi hazars: every par o ajacent s shoul be covere by a term Hazars in Combinational Circuits Why o we care about hazars? Combinational networks on t care the network will unction correctly Synchronous sequential networks on t care the input signals must be stable within setup an hol time o liplops Asynchronous sequential networks hazars can cause the network to enter an incorrect state circuitry that generates the netstate variables must be hazarree Power consumption is proportional to the number o transitions 2/6/23 UAHCPE/EE 422/522 AM 5 Programmable Logic Devices Rea Only Memories (ROMs) Programmable Logic Arrays (PLAs) Programmable Array Logic Devices (PALs) 2/6/23 UAHCPE/EE 422/522 AM 6 ReaOnly Memories Basic ROM Structure Store binary ata ata can be rea out whenever esire cannot be change uner normal operating conitions n input lines, m output lines => array o 2 n mbit wors Input lines serve as an aress to select one o 2 n wors Use ROM to implement logic unctions? n variables, m unctions 2/6/23 UAHCPE/EE 422/522 AM 7 2/6/23 UAHCPE/EE 422/522 AM 8 3
4 ROM Types Maskprogrammable ROM Data is permanently store (inclue or omit the switching elements) Economically easible or a large quantity EPROM (Erasable Programmable ROM) Use special chargestorage mechanism to enable or isable the switching elements in the memory array PROM programmer is use to provie appropriate voltage pulses to store electronic charges Data is permanent until erase using an ultraviolet light EEPROM Electrically Erasable PROM erasure is accomplishe using electrical pulses (can be reprogramme typically to times) Flash memories similar to EEPROM ecept they use a ierent chargestorage mechanism usually have builtin programming an erase capability, so the ata can be written to the lash memory while it is in place, without the nee or a separate programmer 2/6/23 UAHCPE/EE 422/522 AM 9 Programmable Logic Arrays (PLAs) Perorm the same unction as a ROM n inputs an m outputs m unctions o n variables AND array realizes prouct terms o the input variables OR array ORs together the prouct terms 2/6/23 UAHCPE/EE 422/522 AM 2 PLA: 3 inputs, 5 p.t., 4 outputs nmos NOR Gate F,, = A' B' + AC' F,, = A' B' + AC' F 7) = B + AC',, = A' B' + BC' 5, 7) = AC+ B 2/6/23 UAHCPE/EE 422/522 AM 2 2/6/23 UAHCPE/EE 422/522 AM 22 ANDOR Array Equivalent Moiie Truth Table or PLA F,, = A' B' + AC' F 7) = B+ AC' = m(,, = A' B' + BC' 5, 7) = AC + B variable is complemente variable is not complemente not present in the term Prouct Term Inputs Outputs A B C F F A B AC B BC AC 2/6/23 UAHCPE/EE 422/522 AM 23 2/6/23 UAHCPE/EE 422/522 AM 24 4
5 Using PLA: An Eample Using PLA: An Eample F 5, 7, 8, 9,,, 5) 5, 7,,, 5) F = m( 7, 8, 9, 5) 3 ab c ab c ab c F = b + b' c + ab' = c + a' b = bc + ab' c' + ab Eight ierent prouct terms are require!? For PLA we want to minimize the total number o prouct terms, not the number o prouct terms or each unction separately! F b' c a' b bc ab ab' c' 2/6/23 UAHCPE/EE 422/522 AM 25 2/6/23 UAHCPE/EE 422/522 AM 26 Using PLA: An Eample F = a' b + ab+ ab' c' + b' c = a' b + b' c + bc = ab+ ab' c' + bc Programmable Array Logic (PALs) PAL is a special case o PLA AND array is programmable an OR array is ie PAL is less epensive easier to program 2/6/23 UAHCPE/EE 422/522 AM 27 2/6/23 UAHCPE/EE 422/522 AM 28 Programmable Array Logic (PALs) Unprogramme PALs Typical PALs have rom to 2 inputs rom 2 to outputs rom 2 to 8 AND gates riving each OR gate oten inclue D liplops Programme 2/6/23 UAHCPE/EE 422/522 AM 29 2/6/23 UAHCPE/EE 422/522 AM 3 5
6 Logic Diagram or 6R4 PAL Logic Diagram or 6R4 PAL 2/6/23 UAHCPE/EE 422/522 AM 3 2/6/23 UAHCPE/EE 422/522 AM 32 Using PALs: An Eample Using PALs: An Eample 2 3 Implement the ollowing: 2 3 = 2' 3+ ' ' = ' ' = 2' 3+ ' ' = ' ' P P P 2 P 2 P 3 P 3 2 P 4 P 4 AND plane 2/6/23 UAHCPE/EE 422/522 AM 33 AND plane 2/6/23 UAHCPE/EE 422/522 AM 34 Typical PALs To Do Typical PALs have rom to 2 inputs rom 2 to outputs rom 2 to 8 AND gates riving each OR gate oten inclue D liplops Select Enable Rea Tetbook chapters.5, 3., Fliplop D Q Clock To AND plane MUX output is e back to the AND plane. Why? 2/6/23 UAHCPE/EE 422/522 AM 35 2/6/23 UAHCPE/EE 422/522 AM 36 6
7 Sequential Networks Have memory (state) Present state epens not only on the current input, but also on all previous inputs (history) Future state epens on the current input an state Clocke D FlipFlop with Risingege Trigger X = 2... n Q = Q Q 2... Q k 2 n Z ( t ) = + Q ( t ) = Z = z z 2... z m Q F ( X ( t ), Q ( t )) G ( X ( t ), Q ( t 2/6/23 UAHCPE/EE 422/522 AM 37 )) z z 2 z m Fliplops are commonly use as storage evices: DFF, JKFF, TFF Net state The net state in response to the rising ege o the clock is equal to the D input beore the rising ege 2/6/23 UAHCPE/EE 422/522 AM 38 Clocke JK FlipFlop Clocke JK FlipFlop Net state JK = => no state change occurs JK = => the liplop is set to, inepenent o the current state JK = => the liplop is always reset to JK = => the liplop changes the state Q + = Q 2/6/23 UAHCPE/EE 422/522 AM 39 Net state T = => the liplop changes the state Q + = Q T = => no state change 2/6/23 UAHCPE/EE 422/522 AM 4 SR Latch Transparent D Latch 2/6/23 UAHCPE/EE 422/522 AM 4 2/6/23 UAHCPE/EE 422/522 AM 42 7
8 Transparent D Latch Mealy Sequential Networks General moel o Mealy Sequential Network () X inputs are change to a new value (2) Ater a elay, the Z outputs an net state appear at the output o CM (3) The net state is clocke into the state register an the state changes 2/6/23 UAHCPE/EE 422/522 AM 43 2/6/23 UAHCPE/EE 422/522 AM 44 An Eample: 842 BCD to Ecess3 BCD Coe Converter Q z t3 X (inputs) t2 t t t3 Z (outputs) t2 t t State Graph an Table or Coe Converter 2/6/23 UAHCPE/EE 422/522 AM 45 2/6/23 UAHCPE/EE 422/522 AM 46 State Assignment Rules Transition Table 2/6/23 UAHCPE/EE 422/522 AM 47 2/6/23 UAHCPE/EE 422/522 AM 48 8
9 Kmaps Realization 2/6/23 UAHCPE/EE 422/522 AM 49 2/6/23 UAHCPE/EE 422/522 AM 5 9
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