Outline. CPE/EE 422/522 Advanced Logic Design L02. Review: Combinational-Circuit Building Blocks. Multiplexers: 2-to-1 Multiplexer

Size: px
Start display at page:

Download "Outline. CPE/EE 422/522 Advanced Logic Design L02. Review: Combinational-Circuit Building Blocks. Multiplexers: 2-to-1 Multiplexer"

Transcription

1 Outline CPE/EE 422/522 Avance Logic Design L2 Electrical an Computer Engineering University o Alabama in Huntsville What we know Laws an Theorems o Boolean Algebra Simpliication o Logic Epressions Using Laws an Theorems o Boolean Algebra or Using Kmaps Design Using only NAND or only NOR gates Tristate buers Basic Combinational Builing Blocks Multipleers, Decoers, Encoers,... What we o not know Hazars in Combinational Networks How to implement unctions using ROMs, PLAs, an PALs Sequential Networks (i time) 2/6/23 UAHCPE/EE 422/522 AM 2 Review: CombinationalCircuit Builing Blocks Multipleers Decoers Encoers Coe Converters Comparators Aers/Subtractors Multipliers Shiters Multipleers: 2to Multipleer Have number o ata inputs, one or more select inputs, an one output It passes the signal value on one o ata inputs to the output s w w s (a) Graphical symbol s w w w (c) Sumo proucts circuit = s' w + sw w (b) Truth table 2/6/23 UAHCPE/EE 422/522 AM 3 2/6/23 UAHCPE/EE 422/522 AM 4 Review: Synthesis o Logic Functions Using Mues w w 2 w 3 w w 2 (a) Moiie truth table w 3 w3 2/6/23 UAHCPE/EE 422/522 AM 5 w 3 w 2 w (b) Circuit Decoers: nto2 n Decoer Decoe encoe inormation: n inputs, 2 n outputs I En =, only one output is asserte at a time Onehot encoe output n inputs mbit binary coe where eactly one bit is set to Enable w w n En y y 2 n 2 n outputs y = wn '... w ' w' En y = wn '... w ' wen y2 = wn '... ww ' En... y n = wn... ww En 2 2/6/23 UAHCPE/EE 422/522 AM 6

2 Decoers: 2to4 Decoer Encoers En w w y y y 2 y 3 (a) Truth table w y w y y 2 En y 3 w w En y y y 2 y 3 Opposite o ecoers Encoe given inormation into a more compact orm Binary encoers 2 n inputs into nbit coe Eactly one o the input signals shoul have a value o, an outputs present the binary number that ientiies which input is equal to Use: reuce the number o bits (transmitting an storing inormation) (b) Graphic symbol (c) Logic circuit 2 n inputs w w 2 n y y n n outputs 2/6/23 UAHCPE/EE 422/522 AM 7 2/6/23 UAHCPE/EE 422/522 AM 8 Encoers: 4to2 Encoer Encoers: Priority Encoers w 3 w 2 w w y (a) Truth table y w w y w 2 w y 3 (b) Circuit Each input has a priority level associate with it The encoer outputs inicate the active input that has the highest priority (a) Truth table or a 4to2 priority encoer w 3 w 2 w w y y z 2/6/23 UAHCPE/EE 422/522 AM 9 2/6/23 UAHCPE/EE 422/522 AM Coe Converters Convert rom one type o input encoing to a ierent output encoing E. g., BCDto7segment ecoer w w w 2 w 3 a b c e (a) Coe converter g e a g (b) 7 segment isplay b c w 3 w 2 w w a b c e g Hazars in Combinational Networks What are hazars in CM? Unwante switching transients at the output (glitches) Eample ABC =, B changes to Assume each gate has propagation elay o ns (c) Truth table 2/6/23 UAHCPE/EE 422/522 AM 2/6/23 UAHCPE/EE 422/522 AM 2 2

3 Hazars in Combinational Networks Occur when ierent paths rom input to output have ierent propagation elays Static hazar a network output momentarily go to the when it shoul remain a constant Static hazar a network output momentarily go to the when it shoul remain a constant Dynamic hazar i an output change three or more times, when the output is suppose to change rom to ( to ) 2/6/23 UAHCPE/EE 422/522 AM 3 AB C Hazars in Combinational Circuits = AB' + BC AB C 2/6/23 UAHCPE/EE 422/522 AM 4 = AB' + BC + AC To avoi hazars: every par o ajacent s shoul be covere by a term Hazars in Combinational Circuits Why o we care about hazars? Combinational networks on t care the network will unction correctly Synchronous sequential networks on t care the input signals must be stable within setup an hol time o liplops Asynchronous sequential networks hazars can cause the network to enter an incorrect state circuitry that generates the netstate variables must be hazarree Power consumption is proportional to the number o transitions 2/6/23 UAHCPE/EE 422/522 AM 5 Programmable Logic Devices Rea Only Memories (ROMs) Programmable Logic Arrays (PLAs) Programmable Array Logic Devices (PALs) 2/6/23 UAHCPE/EE 422/522 AM 6 ReaOnly Memories Basic ROM Structure Store binary ata ata can be rea out whenever esire cannot be change uner normal operating conitions n input lines, m output lines => array o 2 n mbit wors Input lines serve as an aress to select one o 2 n wors Use ROM to implement logic unctions? n variables, m unctions 2/6/23 UAHCPE/EE 422/522 AM 7 2/6/23 UAHCPE/EE 422/522 AM 8 3

4 ROM Types Maskprogrammable ROM Data is permanently store (inclue or omit the switching elements) Economically easible or a large quantity EPROM (Erasable Programmable ROM) Use special chargestorage mechanism to enable or isable the switching elements in the memory array PROM programmer is use to provie appropriate voltage pulses to store electronic charges Data is permanent until erase using an ultraviolet light EEPROM Electrically Erasable PROM erasure is accomplishe using electrical pulses (can be reprogramme typically to times) Flash memories similar to EEPROM ecept they use a ierent chargestorage mechanism usually have builtin programming an erase capability, so the ata can be written to the lash memory while it is in place, without the nee or a separate programmer 2/6/23 UAHCPE/EE 422/522 AM 9 Programmable Logic Arrays (PLAs) Perorm the same unction as a ROM n inputs an m outputs m unctions o n variables AND array realizes prouct terms o the input variables OR array ORs together the prouct terms 2/6/23 UAHCPE/EE 422/522 AM 2 PLA: 3 inputs, 5 p.t., 4 outputs nmos NOR Gate F,, = A' B' + AC' F,, = A' B' + AC' F 7) = B + AC',, = A' B' + BC' 5, 7) = AC+ B 2/6/23 UAHCPE/EE 422/522 AM 2 2/6/23 UAHCPE/EE 422/522 AM 22 ANDOR Array Equivalent Moiie Truth Table or PLA F,, = A' B' + AC' F 7) = B+ AC' = m(,, = A' B' + BC' 5, 7) = AC + B variable is complemente variable is not complemente not present in the term Prouct Term Inputs Outputs A B C F F A B AC B BC AC 2/6/23 UAHCPE/EE 422/522 AM 23 2/6/23 UAHCPE/EE 422/522 AM 24 4

5 Using PLA: An Eample Using PLA: An Eample F 5, 7, 8, 9,,, 5) 5, 7,,, 5) F = m( 7, 8, 9, 5) 3 ab c ab c ab c F = b + b' c + ab' = c + a' b = bc + ab' c' + ab Eight ierent prouct terms are require!? For PLA we want to minimize the total number o prouct terms, not the number o prouct terms or each unction separately! F b' c a' b bc ab ab' c' 2/6/23 UAHCPE/EE 422/522 AM 25 2/6/23 UAHCPE/EE 422/522 AM 26 Using PLA: An Eample F = a' b + ab+ ab' c' + b' c = a' b + b' c + bc = ab+ ab' c' + bc Programmable Array Logic (PALs) PAL is a special case o PLA AND array is programmable an OR array is ie PAL is less epensive easier to program 2/6/23 UAHCPE/EE 422/522 AM 27 2/6/23 UAHCPE/EE 422/522 AM 28 Programmable Array Logic (PALs) Unprogramme PALs Typical PALs have rom to 2 inputs rom 2 to outputs rom 2 to 8 AND gates riving each OR gate oten inclue D liplops Programme 2/6/23 UAHCPE/EE 422/522 AM 29 2/6/23 UAHCPE/EE 422/522 AM 3 5

6 Logic Diagram or 6R4 PAL Logic Diagram or 6R4 PAL 2/6/23 UAHCPE/EE 422/522 AM 3 2/6/23 UAHCPE/EE 422/522 AM 32 Using PALs: An Eample Using PALs: An Eample 2 3 Implement the ollowing: 2 3 = 2' 3+ ' ' = ' ' = 2' 3+ ' ' = ' ' P P P 2 P 2 P 3 P 3 2 P 4 P 4 AND plane 2/6/23 UAHCPE/EE 422/522 AM 33 AND plane 2/6/23 UAHCPE/EE 422/522 AM 34 Typical PALs To Do Typical PALs have rom to 2 inputs rom 2 to outputs rom 2 to 8 AND gates riving each OR gate oten inclue D liplops Select Enable Rea Tetbook chapters.5, 3., Fliplop D Q Clock To AND plane MUX output is e back to the AND plane. Why? 2/6/23 UAHCPE/EE 422/522 AM 35 2/6/23 UAHCPE/EE 422/522 AM 36 6

7 Sequential Networks Have memory (state) Present state epens not only on the current input, but also on all previous inputs (history) Future state epens on the current input an state Clocke D FlipFlop with Risingege Trigger X = 2... n Q = Q Q 2... Q k 2 n Z ( t ) = + Q ( t ) = Z = z z 2... z m Q F ( X ( t ), Q ( t )) G ( X ( t ), Q ( t 2/6/23 UAHCPE/EE 422/522 AM 37 )) z z 2 z m Fliplops are commonly use as storage evices: DFF, JKFF, TFF Net state The net state in response to the rising ege o the clock is equal to the D input beore the rising ege 2/6/23 UAHCPE/EE 422/522 AM 38 Clocke JK FlipFlop Clocke JK FlipFlop Net state JK = => no state change occurs JK = => the liplop is set to, inepenent o the current state JK = => the liplop is always reset to JK = => the liplop changes the state Q + = Q 2/6/23 UAHCPE/EE 422/522 AM 39 Net state T = => the liplop changes the state Q + = Q T = => no state change 2/6/23 UAHCPE/EE 422/522 AM 4 SR Latch Transparent D Latch 2/6/23 UAHCPE/EE 422/522 AM 4 2/6/23 UAHCPE/EE 422/522 AM 42 7

8 Transparent D Latch Mealy Sequential Networks General moel o Mealy Sequential Network () X inputs are change to a new value (2) Ater a elay, the Z outputs an net state appear at the output o CM (3) The net state is clocke into the state register an the state changes 2/6/23 UAHCPE/EE 422/522 AM 43 2/6/23 UAHCPE/EE 422/522 AM 44 An Eample: 842 BCD to Ecess3 BCD Coe Converter Q z t3 X (inputs) t2 t t t3 Z (outputs) t2 t t State Graph an Table or Coe Converter 2/6/23 UAHCPE/EE 422/522 AM 45 2/6/23 UAHCPE/EE 422/522 AM 46 State Assignment Rules Transition Table 2/6/23 UAHCPE/EE 422/522 AM 47 2/6/23 UAHCPE/EE 422/522 AM 48 8

9 Kmaps Realization 2/6/23 UAHCPE/EE 422/522 AM 49 2/6/23 UAHCPE/EE 422/522 AM 5 9

DIGITAL ELECTRONICS QUESTION BANK

DIGITAL ELECTRONICS QUESTION BANK DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure

More information

Topics. FPGA Design EECE 277. Combinational Logic Blocks. From Last Time. Multiplication. Dr. William H. Robinson February 25, 2005

Topics. FPGA Design EECE 277. Combinational Logic Blocks. From Last Time. Multiplication. Dr. William H. Robinson February 25, 2005 FPGA Design EECE 277 Combinational Logic Blocks Dr. William H. Robinson Februar5, 25 http://eecs.vanderbilt.edu/courses/eece277/ Topics Computer, compute to the last digit the value o pi. Mr. Spock (Star

More information

Fan in: The number of inputs of a logic gate can handle.

Fan in: The number of inputs of a logic gate can handle. Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

Objective Questions. (a) Light (b) Temperature (c) Sound (d) all of these

Objective Questions. (a) Light (b) Temperature (c) Sound (d) all of these Objective Questions Module 1: Introduction 1. Which of the following is an analog quantity? (a) Light (b) Temperature (c) Sound (d) all of these 2. Which of the following is a digital quantity? (a) Electrical

More information

Memory, Latches, & Registers

Memory, Latches, & Registers Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers 1 General Table Lookup Synthesis A B 00

More information

In this lecture: Lecture 8: ROM & Programmable Logic Devices

In this lecture: Lecture 8: ROM & Programmable Logic Devices In this lecture: Lecture 8: ROM Programmable Logic Devices Dr Pete Sedcole Department of EE Engineering Imperial College London http://caseeicacuk/~nps/ (Floyd, 3 5, 3) (Tocci 2, 24, 25, 27, 28, 3 34)

More information

UNIT-III ASYNCHRONOUS SEQUENTIAL CIRCUITS TWO MARKS 1. What are secondary variables? -present state variables in asynchronous sequential circuits 2. What are excitation variables? -next state variables

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page

More information

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As

More information

CS302 - Digital Logic Design Glossary By

CS302 - Digital Logic Design Glossary By CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital

More information

Digital Logic Circuits

Digital Logic Circuits Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals

More information

Electronics. Digital Electronics

Electronics. Digital Electronics Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital

More information

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Lecture 5 Doru Todinca Textbook This chapter is based on the book [RothKinney]: Charles H. Roth, Larry L. Kinney, Fundamentals

More information

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1 Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates

More information

2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.

2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. 2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

Gates and Circuits 1

Gates and Circuits 1 1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior

More information

IES Digital Mock Test

IES Digital Mock Test . The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC

More information

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28 Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,

More information

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true

More information

Unit level 4 Credit value 15. Introduction. Learning Outcomes

Unit level 4 Credit value 15. Introduction. Learning Outcomes Unit 20: Unit code Digital Principles T/615/1494 Unit level 4 Credit value 15 Introduction While the broad field of electronics covers many aspects, it is digital electronics which now has the greatest

More information

Module -18 Flip flops

Module -18 Flip flops 1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip

More information

UNIT-IV Combinational Logic

UNIT-IV Combinational Logic UNIT-IV Combinational Logic Introduction: The signals are usually represented by discrete bands of analog levels in digital electronic circuits or digital electronics instead of continuous ranges represented

More information

Digital Fundamentals. Logic gates

Digital Fundamentals. Logic gates Digital Fundamentals Logic gates Objectives Describe the operation of the inverter, the AND gate, and the OR gate Describe the operation of the NAND gate and the NOR gate Express the operation of the NOT,

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.

This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations. Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture

More information

FPGA Based System Design

FPGA Based System Design FPGA Based System Design Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Why VLSI? Integration improves the design: higher speed; lower power; physically smaller. Integration reduces

More information

CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits Analysis and Design CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative

More information

Chapter 3 Describing Logic Circuits Dr. Xu

Chapter 3 Describing Logic Circuits Dr. Xu Chapter 3 Describing Logic Circuits Dr. Xu Chapter 3 Objectives Selected areas covered in this chapter: Operation of truth tables for AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. Boolean

More information

Outline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit

Outline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit Outline EES 5 - omponents and esign Techniques for igital Systems Lec 2 - Timing avid uller Electrical Engineering and omputer Sciences University of alifornia, erkeley Performance Limits of Synchronous

More information

HAZARDS AND PULSE MODE SEQUENTIAL CIRCUITS

HAZARDS AND PULSE MODE SEQUENTIAL CIRCUITS Chapter 19 HAZARDS AND PULSE MODE SEQUENTIAL CIRCUITS Ch19L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 1 Lesson 5 Dynamic Hazards, Essential Hazards and Pulse mode sequential

More information

Digital Electronics Course Objectives

Digital Electronics Course Objectives Digital Electronics Course Objectives In this course, we learning is reported using Standards Referenced Reporting (SRR). SRR seeks to provide students with grades that are consistent, are accurate, and

More information

EXPERIMENT #5 COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

EXPERIMENT #5 COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 La Rosa EXPERIMENT #5 COMINTIONL and SEUENTIL LOGIC CIRCUITS Hardware implementation and software design I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational

More information

EECS 150 Homework 4 Solutions Fall 2008

EECS 150 Homework 4 Solutions Fall 2008 Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring

More information

Digital Systems Principles and Applications TWELFTH EDITION. 3-3 OR Operation With OR Gates. 3-4 AND Operations with AND gates

Digital Systems Principles and Applications TWELFTH EDITION. 3-3 OR Operation With OR Gates. 3-4 AND Operations with AND gates Digital Systems Principles and Applications TWELFTH EDITION CHAPTER 3 Describing Logic Circuits Part -2 J. Bernardini 3-3 OR Operation With OR Gates An OR gate is a circuit with two or more inputs, whose

More information

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.

! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology.  Gate choice, logical optimization.  Fanin, fanout, Serial vs. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!

More information

Practical Workbook Logic Design & Switching Theory

Practical Workbook Logic Design & Switching Theory Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering

More information

ECE 172 Digital Systems. Chapter 2 Digital Hardware. Herbert G. Mayer, PSU Status 6/30/2018

ECE 172 Digital Systems. Chapter 2 Digital Hardware. Herbert G. Mayer, PSU Status 6/30/2018 ECE 172 Digital Systems Chapter 2 Digital Hardware Herbert G. Mayer, PSU Status 6/30/2018 1 Syllabus l Term Sharing l Standard Forms l Hazards l Decoders l PLA vs. PAL l PROM l Bibliography 2 Product Term

More information

INF3430 Clock and Synchronization

INF3430 Clock and Synchronization INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability

More information

Lecture 2: Digital Logic Basis

Lecture 2: Digital Logic Basis Lecture 2: Digital Logic Basis Xufeng Kou School of Information Science and Technology ShanghaiTech University 1 Outline Truth Table Basic Logic Operation and Gates Logic Circuits NOR Gates and NAND Gates

More information

Chapter 2 Introduction to Logic Circuits

Chapter 2 Introduction to Logic Circuits Chapter 2 Introduction to Logic Circuits Logic unctions and circuits Boolean algebra Snthesis o digital circuits Introduction to CAD tools Introduction to VHDL Logic unctions and Circuits and 2 are binar

More information

Chapter 9. sequential logic technologies

Chapter 9. sequential logic technologies Chapter 9. sequential logic technologies In chapter 4, we looked at diverse implementation technologies for combinational logic circuits: random logic, regular logic, programmable logic. The similar variants

More information

Chapter 9. sequential logic technologies

Chapter 9. sequential logic technologies Chapter 9. sequential logic technologies In chapter 4, we looked at diverse implementation technologies for combinational logic circuits: random logic, regular logic, programmable logic. Similarly, variations

More information

Combinational Logic Design CH002

Combinational Logic Design CH002 Combinational Logic Design CH002 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications Figure 2.2 Elements and nodes Figure 2.3 Combinational logic circuit Figure 2.4 Two OR implementations

More information

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression

More information

Course Overview. Course Overview

Course Overview. Course Overview Course Overview Where does this course fit into the Electrical Engineering curriculum? Page 5 Course Overview Where does this course fit into the Computer Engineering curriculum? Page 6 3 Course Content

More information

Name: Class: Date: 1. As more electronic systems have been designed using digital technology, devices have become smaller and less powerful.

Name: Class: Date: 1. As more electronic systems have been designed using digital technology, devices have become smaller and less powerful. Name: Class: Date: DE Midterm Review 2 True/False Indicate whether the statement is true or false. 1. As more electronic systems have been designed using digital technology, devices have become smaller

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

EE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30

EE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30 EE 330 Lecture 44 igital Circuits Ring Oscillators Sequential Logic Array Logic Memory Arrays Final: Tuesday May 2 7:30-9:30 Review from Last Time ynamic Logic Basic ynamic Logic Gate V F A n PN Any of

More information

Memory, Latches, & Registers

Memory, Latches, & Registers Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather

More information

PE713 FPGA Based System Design

PE713 FPGA Based System Design PE713 FPGA Based System Design Why VLSI? Dept. of EEE, Amrita School of Engineering Why ICs? Dept. of EEE, Amrita School of Engineering IC Classification ANALOG (OR LINEAR) ICs produce, amplify, or respond

More information

Logic diagram: a graphical representation of a circuit

Logic diagram: a graphical representation of a circuit LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate

More information

Combinational Logic Circuits. Combinational Logic

Combinational Logic Circuits. Combinational Logic Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The

More information

Logic Circuit Design

Logic Circuit Design Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic

More information

Chapter 2 Combinational Circuits

Chapter 2 Combinational Circuits Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits

More information

By: Dr. Ahmed ElShafee

By: Dr. Ahmed ElShafee Lecture (03) COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II Design of Circuits with Limited Gate Fan In In

More information

Syllabus: Digital Electronics (DE) (Project Lead The Way)

Syllabus: Digital Electronics (DE) (Project Lead The Way) Course Overview: Digital electronics and micro computers. This is a course in applied logic that encompasses the application of electronic circuits and devices. Computer simulation software is used to

More information

Gates and and Circuits

Gates and and Circuits Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

More information

Number of Lessons:155 #14B (P) Electronics Technology with Digital and Microprocessor Laboratory Completion Time: 42 months

Number of Lessons:155 #14B (P) Electronics Technology with Digital and Microprocessor Laboratory Completion Time: 42 months PROGRESS RECORD Study your lessons in the order listed below. Number of Lessons:155 #14B (P) Electronics Technology with Digital and Microprocessor Laboratory Completion Time: 42 months 1 2330A Current

More information

UNIT IV. Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below.

UNIT IV. Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below. UNIT IV Digital Logic Families Logic families can be classified broadly according to the technologies they are built with. The various technologies are listed below. DL : Diode Logic. RTL : Resistor Transistor

More information

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered

More information

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits 1 Module-4 Design and Analysis of Combinational Circuits 4.1 Motivation: This topic develops the fundamental understanding and design of adder, substractor, code converter multiplexer, demultiplexer etc

More information

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation

More information

Associate In Applied Science In Electronics Engineering Technology Expiration Date:

Associate In Applied Science In Electronics Engineering Technology Expiration Date: PROGRESS RECORD Study your lessons in the order listed below. Associate In Applied Science In Electronics Engineering Technology Expiration Date: 1 2330A Current and Voltage 2 2330B Controlling Current

More information

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean

More information

EE19D Digital Electronics. Lecture 1: General Introduction

EE19D Digital Electronics. Lecture 1: General Introduction EE19D Digital Electronics Lecture 1: General Introduction 1 What are we going to discuss? Some Definitions Digital and Analog Quantities Binary Digits, Logic Levels and Digital Waveforms Introduction to

More information

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for

More information

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,

More information

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1 LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design

More information

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700: SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted SR Latch S R S R SR LATCH WITH NABL: R R' S R t+ t t+ t t t S S' LATCH WITH NABL: This is

More information

Analysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows:

Analysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows: Combinational Logic Logic circuits for digital systems may be combinational or sequential. combinational circuit consists of input variables, logic gates, and output variables. 1 nalysis procedure To obtain

More information

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1

More information

Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitII 2. SKILLS ADDRESSED: Learning I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS

More information

COURSE LEARNING OUTCOMES AND OBJECTIVES

COURSE LEARNING OUTCOMES AND OBJECTIVES COURSE LEARNING OUTCOMES AND OBJECTIVES A student who successfully fulfills the course requirements will have demonstrated: 1. an ability to analyze and design CMOS logic gates 1-1. convert numbers from

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Function Table of an Odd-Parity Generator Circuit

Function Table of an Odd-Parity Generator Circuit Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as

More information

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3

DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 DIGITAL ELECTRONICS Marking scheme : Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 Aim: This experiment will investigate the function of the

More information

6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form:

6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form: 6.111 Lecture # 19 Controlling Position Servomechanisms are of this form: Some General Features of Servos: They are feedback circuits Natural frequencies are 'zeros' of 1+G(s)H(s) System is unstable if

More information

Digital Electronic Concepts

Digital Electronic Concepts Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course

More information

Logic 0 Logic To provide an output load (or two) 5 Voltage Measurement Point V CC +5 74LS00 GND

Logic 0 Logic To provide an output load (or two) 5 Voltage Measurement Point V CC +5 74LS00 GND Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 1 Logic Analyzers, Digital Oscilloscopes, and

More information

Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of

More information

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N

DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical

More information

EXPERIMENT NO 1 TRUTH TABLE (1)

EXPERIMENT NO 1 TRUTH TABLE (1) EPERIMENT NO AIM: To verify the Demorgan s theorems. APPARATUS REQUIRED: THEORY: Digital logic trainer and Patch cords. The digital signals are discrete in nature and can only assume one of the two values

More information

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF

More information

TABLE 3-2 Truth Table for Code Converter Example

TABLE 3-2 Truth Table for Code Converter Example 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z 2 3 4 5 6 7 8 9 Truth

More information

Module 4: Combinational Logic Glitches and Hazards

Module 4: Combinational Logic Glitches and Hazards Module 4: Combinational Logic Glitches and Hazards Wakerly: Chapter 4 (part 3) : ECEN 3233 r. Keith. Teague Spring 23 23 TIME RESPONSE in Combinational Networks emphasis on timing behavior of circuits

More information

Electronic Circuits EE359A

Electronic Circuits EE359A Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.

More information

(B) The simplest way to measure the light intensity is using a photodiode in the photoconductive mode:

(B) The simplest way to measure the light intensity is using a photodiode in the photoconductive mode: PHY226 Electronics Final Preparation 1. Optoelectronics: LEDs and photodiodes (A) LEDs and photodiodes are essentially semi conductor diodes which can interact with electromagnetic waves. Explain why in

More information

Laboratory Manual CS (P) Digital Systems Lab

Laboratory Manual CS (P) Digital Systems Lab Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification

More information

UC Berkeley CS61C : Machine Structures

UC Berkeley CS61C : Machine Structures CS61C L22 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 22 Representations of Combinatorial Logic Circuits 27-3-9 TA David

More information

CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN. Click the mouse to move to the next page. Use the ESC key to exit this chapter.

CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN. Click the mouse to move to the next page. Use the ESC key to exit this chapter. CHPTER 6 SEQUENTIL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter. Contents 6. Summary of Design Procedure for Sequential Circuits 6.2 Design ExampleCode

More information