Topics. FPGA Design EECE 277. Combinational Logic Blocks. From Last Time. Multiplication. Dr. William H. Robinson February 25, 2005

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1 FPGA Design EECE 277 Combinational Logic Blocks Dr. William H. Robinson Februar5, 25 Topics Computer, compute to the last digit the value o pi. Mr. Spock (Star Trek) Administrative stu Check/veriy your homework/test scores on Blackboard Read Chapter 7 in your tetbook Homework Assignment #4 posted later today (due TBD) Laboratory Assignment #2 (due Monday, Februar8) Raising the bar o epectations or the lab report Multiplication Data representation Functional logic blocks 2 From Last Time Multiplication Addition/subtraction occurs with 2 s complement number system Carry chain is the critical delay path o an adder circuit Calculations with inite precision can lead to overlow errors Multiplicand M Multiplier Q Product P (4) () (54) (a) Multiplication by hand Multiplicand M Multiplier Q Partial product Partial product Partial product 2 Product P (4) () (54) (b) Multiplication or implementation in hardware Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill 3 Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill 4

2 Multiplier Hardware Implementation Representing Real Numbers m 3 m 2 m m m k + m k q q q PP q c out FA c in PP2 q 2 (b) A block in the top row p 7 p 6 p 5 p 4 p 3 p 2 p p q 3 Bit o PPi m k q j Regions 2, 4, and 6 are OK (a) Structure o the circuit c out FA c in Must ind a way to handle regions, 3, 5, and 7 (c) A block in the bottom two rows Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill 5 6 IEEE Floating Point Standard 754 Floating Point Numbers Provided designers with a correct model S E 32 bits M Allowed FP data to be echanged among dierent computer systems Sign denotes + denotes 8-bit ecess-27 eponent (a) Single precision 23 bits o mantissa Deines three ormats Single precision (32 bits) Double precision (64 bits) Etended precision (8 bits) Only occurs within FP units Sign S E -bit ecess-23 eponent 64 bits M 52 bits o mantissa (b) Double precision 7 Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill 8

3 IEEE Numerical Types Binary-Coded Decimal (BCD) Underlow handled graceully Use denormalized numbers instead o jumping to zero Overlow becomes ininity Includes Not a Number (NaN) 9 Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill ASCII Code Logic Circuit Types Combinational Output is a unction o inputs ONLY e.g. briecase lock Sequential Output is a unction o inputs and previous state (memory) e.g. vending machine Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill 2

4 Multipleers Signals 2 n data inputs n control (select) inputs data output Binary code on control lines determines which input is connected (gated/routed) to output LIBRARY ieee ; USE ieee.std_logic_64.all ; VHDL Code or 2: Mu ENTITY mu2to IS PORT ( w, w, s : IN STD_LOGIC ; : OUT STD_LOGIC ) ; END mu2to ; Eample: 2: Mu s w w s w w w s w ARCHITECTURE Behavior OF mu2to IS BEGIN WITH s SELECT <= w WHEN '', w WHEN OTHERS ; END Behavior ; Select statement iners a mu structure (no priority) (a) Graphical symbol (b) Truth table (c) Sum-o-products circuit Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 3 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 4 4: Multipleer 8: Multipleer s s w w w 3 (a) Graphic symbol s s w w w 3 (b) Truth table s w s w w 3 (c) Circuit = s sw + ss w + s sw2 + ss w3 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 5 6

5 s s w w 3 w 4 w 7 6: Multipleer s 2 s 3 Smaller mues can be combined to build larger mues Synthesis o Logic Functions w w (a) Implementation using a 4-to- multipleer w 8 w w w w w 5 (b) Modiied truth table (c) Circuit Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 7 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 8 Programmable Switches in FPGAs Three-Input LUT 2 / / / / / / / / Storage cell / / / / i i 2 i i 2 / / / / / / / SRAM storage cells can be reduced with mues 3 / Commercial FPGAs generally adopt this approach Mues are used to route each bit rom the SRAM storage cells Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 9 Fundamentals o Digital Logic: Chapter 3 Copyright 25 McGraw-Hill 2

6 i Output Selection in an FPGA CLB Actel Corporation Act Logic Block In Flip-lop Select Out i i 2 i 3 i 4 i 5 In 2 LUT D Q i 6 In 3 Clock i 7 i 8 Mu is used to select the combinational output or the stored (clocked) output Possible to implement any logic unction using mues FPGA logic block can be comprised o mues Fundamentals o Digital Logic: Chapter 3 Copyright 25 McGraw-Hill 2 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 22 n inputs Enable Decoder w w n En y n 2 n outputs Takes an n-bit number as an input and selects eactly o 2 n outputs En w w 2:4 Decoder with Enable y y y 3 (a) Truth table w y w y Potential uses: Choosing a memory bank with the decoder as an enable Accessing a register location in the register ile with the decoder as the enable Another use or decoders: The output o the decoders are merely the minterms o the inputs You can make any unction by merely ORing the appropriate minterms w y w y En y 3 (b) Graphical symbol (c) Logic circuit Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 23 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 24 En y 3

7 VHDL Code or 2:4 Binary Decoder LIBRARY ieee ; USE ieee.std_logic_64.all ; 3:8 Decoder ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR( DOWNTO ) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR( TO 3) ) ; END dec2to4 ; w w y y w w y y En y 3 y 3 ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO ) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN OTHERS ; END Behavior ; Fundamentals o Digital Logic: Chapter 6 The & symbol is or concatenation Copyright 25 McGraw-Hill 25 En Fundamentals o Digital Logic: Chapter 6 w y w y En y 3 Larger decoders can be built using smaller decoders y 4 y 5 y 6 y 7 Copyright 25 McGraw-Hill 26 3:8 Decoder Demultipleer Routes an input signal to one o 2 n outputs s y Implementation is similar to decoder with enable s y s s y y y 3 In In In In In y 3 (a) Truth table (b) :4 Demultipleer 27 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 28

8 Encoders 4:2 Encoder w 2 n inputs n Opposite o decoders Encode given inormation into a more compact orm Binary encoders 2 n inputs into n-bit code Eactly one o the input signals should have a value o, and outputs present the binary number that identiies which input is equal to Use: reduce the number o bits (transmitting and storing inormation) y y n n outputs w 3 w w y y (a) Truth table w w (b) Circuit y w 3 y Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 29 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 3 Priority Encoders Each input has a priority level associated with it The encoder outputs indicate the active input that has the highest priority (a) Truth table or a 4-to-2 priority encoder w 3 w w y y d d z VHDL Code or Priority Encoder LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY priority IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; y : OUT STD_LOGIC_VECTOR( DOWNTO ) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; z <= '' WHEN w = "" ELSE '' ; END Behavior ; When-Else structure implies priority Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 3 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 32

9 Code Converter: BCD-to-7-Segment Display w w w 3 a b c d e g (a) Code converter e a g d b c (b) 7-segment display w 3 w w a b c (c) Truth table d e g VHDL Code or BCD-to-7-Segment Decoder LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY seg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO ) ; leds : OUT STD_LOGIC_VECTOR( TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS -- abcdeg WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN "" => leds <= "" ; WHEN OTHERS => leds <= " " ; END CASE ; END PROCESS ; END Behavior ; Process Block or sequential code Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 33 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 34 Comparator 4-Bit Comparator Circuit Determine i two input words are equal Uses the XOR/XNOR gate as the building block A F B F = A B Truth table or XOR unction A B F a 3 b 3 a 2 b 2 a b a b i 3 i 2 i i AeqB AltB AgtB Comparators are not limited to just equality Can be used or other relational operators 35 Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 36

10 Another 4-Bit Comparator Circuit Shiters Let shit is the same as multiplying by powers o 2 Right shit is the same as dividing by powers o 2 Odd numbers lose the last bit Arithmetic shit maintains the sign Logical shit ills empty bits with zeroes Fundamentals o Digital Logic: Chapter 5 Copyright 25 McGraw-Hill Shiter Circuit Using Mues Summary Combinational logic blocks are used to provide useul unctions with limited number o eternal connections Decoders and mues can be used to implement truth tables Which shit operation is this? Fundamentals o Digital Logic: Chapter 6 Copyright 25 McGraw-Hill 39 4