Hybrid Modified Booth Encoded Algorithm-Carry Save Adder Fast Multiplier

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1 Hybrid Modified Booth Encoded Algorithm-Carry Save Adder Fast Multiplier Nik Ghazali Nik Daud, Fakroul Ridzuan Hashim, Muhazam Mustapha & Muhammad Syahir Badruddin. Department of Electrical & Electronics Engineering Universiti Pertahanan Nasional Malaysia Kuala Lumpur, Malaysia Abstract One of the effective ways to speed up multiplication are by reducing the number of partial products and accelerating the accumulation. In this paper, a new architecture of hybrid Modified Booth Encoded Algorithm (MBE) and Carry Save Adder (CSA) is developed as fast multiplier architecture. Altera Quartus II platform is used to run the simulation. The architecture design is programmed into FPGA using Altera DE board to verify the synthesizability on physical hardware. This hybrid fast multiplier delivers good performance in term of higher speed as well as in term of less usage of logic elements. Keywords- Modified Booth Algorithm, Carry Save Adder, Fast Multiplier I. INTRODUCTION Digital signal processing (DSP) is used in a very wide range of applications from high definition television, mobile telephony, digital audio, multimedia, digital cameras, radar, sonar detectors, and more other electronic devices. Developing both programmable DSP chips and dedicated system-on-chip (So-C) solution for this application, has been an active area of research and development over the past three decades []. However, due to rapidly growing So-C industry, not only less power consumption, but the speed of execution and smaller area due to number of component used in circuitry have become major concerns for designing very large scale integration (VLSI). A. Problem Statement of Research Most of DSP applications such as fast Fourier Transform (FFT), discrete cosine transform and Discrete Wavelet Transform (DWT) require additions and multiplications. Since multipliers have a significant impact on the performance of the entire system, many high-performance algorithms and architectures have been proposed to accelerate multiplication. The performance of the multiplier depends upon, how the addition is carried out. The type of addition chosen always determines trade-off between various parameters such as speed and area, power and energy dissipation, and complexity and chip density. A single multiplier cannot be optimized for all these parameters since no design is considered as superior [8]. Therefore, the design of the multiplier depends upon the application of the multiplier. Since multiplication involves two basic operations which are the generation of the partial products and their accumulation, the effective ways to speed up multiplication are by reducing the number of partial products or accelerate their accumulation. Clearly, a smaller number of partial products also reduces the complexity and as the result, reduces the time required to accumulate the partial product. So, research has concentrated on the high-speed multipliers based on the modified Booth encoded algorithm (MBE) and carry save adder (CSA). B. Objectives The modified Booth algorithm reduces the number of partial products to be generated and it is known as the fastest multiplication algorithm [7]. In this project, some realizable objectives need to be achieved by designing a fast multiplier using modified Booth encoded algorithm and CSA. Those objectives are:. To design a multiplier that generates product between multiplicand and multiplier in shorter time execution.. To design a multiplier that uses less number of logic elements in circuitry of field-programmable gate array (FPGA) chip. 3. To design a synthesizable fast multiplier architecture on FPGA chip. In this project, there are a few scopes of works that should be considered. These scopes will determine the result of the multiplier since it is designed for a good performance in term of speed and circuitry complexity. Those scopes are:. The multiplication is based on number of radix- which is in binary digit (bit and ).. The multiplier is compatible with two dimensional multiplications which is involving a bit stream of multiplicand and a bit stream of multiplier. 3. The format of bit streams is two s complement number (signed number).

2 II. ARCHITECTURE OF COMPUTER C MULTIPLICATION There are threee major steps involve in binary multiplication [ 6]. First step is generation of partial products. Next, the reduction of partial product into one row of final sum and one row of carries. Last, the addition of final sum and carries which generates the result. The concepts are explained below. A. Fast Multiplication Methods Performance of processor is significantly affected by the speed of their multiplier []. As mention in von Neumann model, multiplication has been seen as the basic building block for many algorithms in various computing application like DSP. There are several high performance algorithms and architectures have been proposed to improve and to accelerate multiplication process []. ) Modifiedd Booth Algorithm This method employ for the first step of multiplication which is generation of partial product. This is because the ability of MBE is to cut the number of partial products rows in half [6]. It is known as the most efficient Booth encoding and decoding scheme [7]. To multiply and using this approach, we start by grouping the multiplier (here represented as ). This grouping is shown in Fig. and it is based on a window size of 3 bits and a stride of. Figure.(a): MBE encoder Figure.(b): MBE d ecoder By applying this algorithm, the number of partial product rows too be accumulated is reduced from to /. For example, for an 8 8 multiplication, a multiplier without MBE will generate eight partial product rows because there is one partial product row for each bit of the multiplier. However, with MBE, only / (= 4) partial products rows are generated as shown in the example of Fig.3. Figure 3: Generation of partial product using MBE method Figure : MBE grouping The multiplier is segmented into groups of three bits assigned as,, and each such group of bits is associated with its own partial product row. In this grouping,. To generate the encodedd signal of MBE, we shall use scheme shown in Table. As being encoded into MBE scheme, then the signal will be decoded by using decoder in order to generate partial products. The corresponding logic diagram of both encoder and decoder had shown in Fig. (a) and ( (b) respectively. TABLE : MBE TABLE SCHEME ) Carry Lookahead Adder The ripple-carry adder has limiting factor which is the time it takess to propagate the carry is too long. The longest path throughh the adder is from the input of first full adder (FA) to the lastt FA. The carry look-ahead adder (CLA) solves this problem by calculating the carry signals in advance, based on the input signals. Since the interested issue is carry bit, the equation of carry out of FA has been modified so that it can be applied as carry in equation of next FA by only based on the input signal value. From carry out equation of FA, Then, it is rewritten as: Where and and assigned as generate and propagate function respectively. Both functions can be createdd in one logic level since they only depend on different gates whichh are AND and OR gate. Equation of carry out bit for each FA is shown in Fig.4.

3 C C C 3 C 4 G P C G PC G G P C P ( G P G P PG G G3 C3 G3 G P G P PG Figure 4: Carry in i equation in CLA P C ) These expressionss show that,, and do not depend on its previous carry-in. Therefore does not need to wait for to propagate. As is determined, can be reach steady state as other three carries. This is also valid for and 3) Carry Save Adder There are many cases where it is desired to add more than two numbers together. The straightforward way of adding together numbers (all bits wide) is to add the first two, then add that sum to the next, and so on. This requires a total of additions. The idea is to take 3 numbers that we want to addd together,, and convert it into numbers such that. First, the computation of sum and carry is done separately. Sum is computed by adding all three binary digit without take into account the carry bit. Next, for carry computation, it is done on column basis. Here, the carry produced by a column is putted in to the next column. This concept similar to full adder operation where carry out of an adder will be fed into next adder as it s carry in bit. To have final sum of that all three binary number, it will uses CLA. An example of CSA operation is shown in Figure.5. Fig.5: Addition of three digits using CSA To build the logic circuit of CSA, it is just using full adder with different input assignment. The carry in input pin is renamed as the third bit input whereas the carry out output pin is rename as carry. This modification is just renaming these two pin without changes any circuitry connection of full adder. Fig.6 shows how the different between two adders block diagram. Figure 6: Block diagram of FA and CSA G PG P P C P P P C P P P P C 3 III. BASIC MULTIPLIER ARCHITECTURE The basic multiplication of binary digits is constructed based on the fundamental concept of it. This fundamental concept means that the multiplication is using the basic operation of AND gate for partial generation part whereas full adder for the accumulation part. A. Partial Product Generation This part value off partial product generated is only bit whenever the bit of multiplicand and multiplier are. Based on the translation, the generation of partial productt for basic multiplication operation uses AND gate operation only. Thiss is importantt in writing code using VHDL later. An example of multiplication s generated partial products is shown in Table 3. TABLE 3: EXAMPLE OF 8 BITS MULTIPLICATION Thee bolded binary digits are the extensionn sign bits becausee this multiplier is operated for two s complement binary digit. This considerationn is important during accumulation part later. Each row is generated into 6 bit long although the bit stream of both multiplicand and multiplier is 8 bit long becausee of some justification considered below:. Length of final product for multiplication should be where 8 is number of bit of multiplicand and multiplier.. Form of binary number is in two s complement where it should consider the extension sign bit as shown in Table 3. by the bolded bits. B. Accumulation of Partial Products Next step is to accumulate alll the partial products in order too obtain the final sum which is the final product of the basic multiplication. At this stage, the utilization of full adder is required. The inputs of each full adder are the partial product of two rows in one time. Then, the carry will be fed into next full adder as carry in bit. Figure 7 shows the logic circuit of bit full adder.

4 Figure 7: Logic circuit of full adder C. Selected Algorithm for Fast Multiplier Architecture Based on several algorithms and methods for increasing performance of binary multiplier, there are two methods that be employed in designing this fast multiplier. Through this section, all three selected methods which will be used are Modified Booth Algorithm (MBA) and Carry Save Adder (CSA). These methods are selected based on justification as mention below:. MBA is applicable for two s complement binary form.. CSA is the fastest method in adding operation since it considers three bits in one time. [8] ) Partial Product Generation According to the theory for speeding up the multiplication process, the number of partial products row should be less so that the total gates delay during the accumulation part will reduce. Here, MBA is employed in order to achieve this target. Based on Table, it is necessary to build the encoder and decoder for generating the partial product. The logic circuit of both encoder and decoder can be designed as shown in Figure 8(a) and Figure 8(b) respectively. Table 4 shows the partial products that generated by using MBA and the cell of each partial product with respect to the multiplier bit grouping, Z. However, the last signal of will not appear at all. This is because, during the implementation on programming later, there is a subcomponent called s complement where it will convert the s complement inputs bit stream into unsigned number. So, according to MBE table scheme as shown in Table, the last group MBE is only possible for first four rows. This will reduce the number of partial products generated become four ) Accumulation of Partial Products Afterr all partial products have been generated into four rows; the accumulation part will perform adding operation by employing a method that less consumes time which is Carry Save Adder (CSA). Here, the extension sign bit of partial product also be considered because the form of bit stream is still in two ss complement. Based on the number of row of partial products generated, it requires one blockss of CSA. Since CSA can add three bit number, it will add for the first, second and third row. The block of CSA is shown in Fig.8 (a) and 8(b). Figure 8( (a): CSA operation of eight LSB Figure 8(b): CSA operation of eight MSB Then, all sum and carry bit are added by using 6 bit Carry Lookahead Adder (CLA) to obtain sum of the first three rows of partial product. This CLA operates as shown in Fig.9. Hence, the summation of the first threee rows is completed. Then operation is similar for accumulating the presentt sum with thee remaining row of partial product by applying another 6 bit CLA. The sum of second CLA block iss the final sum of the fast multiplier. TABLE 4: PARTIAL PRODUCT GENERATED USING MBA Figure 9: 6 bit CLA block diagram

5 D. Design Simulation The design of entire logic circuit represents of basic multiplier operation and fast multiplier operations are written into Very High Speed Integrated Circuit Hardware Description Language (VHDL). Altera Quartus II was used as a platform. For this project implementation, Cyclone II FPGA chip with number EPC35F67C6 is used. The compilation report in Quartus II provides very useful information in determining the total number of gates used and the time taken to produce the multiplication product. To determine the time of execution of both multiplier, it can be obtained by creating vector waveform file. The number of logic element used can be obtained from the informationn given by the compilation report in Analysis and Synthesis summary. The multiplier is expected to produce an output of product value according to the value of given inputs. This test proceeded by observing the output s waveform which represent the product value of multiplication. E. Implementation on DE Board After completion of simulation part, the fast multiplier architecture then will be programmed into Cyclone II FPGA chip with number EPC35F67C6 which provided on the board. However, some additional components are designed such as binary to BCD unit, seven segment LED unit, toggle switch unit and LCD unit for nterfacing purpose. Fig. shows the interface on the board. ) Display Multiplication Product Six seven segment t LED displayss are utilized because the maximum decimal digit number of the fast multiplier is five. So, based on this consideration, five displays are utilized for five decimal digits and another display is for negative symboll if the product value is negative whereas no lighting if the product value iss positive. IV. SIMULATION RESULT After simulated, summary of several parameters which becomee as point of interest is represented. The summary is dividedd into two partss which are comparison of performance between both multiplier architectures and effect of number of bit one in operands bit stream. The summary of total numberr of logic elements and time execution of both multipliers is summarized in Table 5 and Table 6 respectively. TABLE 5: SUMMARY OF BASIC MULTIPLIER PERFORMANCE PARAMETER BASIC MULTIPLIER GENERATOR ACCUMULATOR TOP ENTITY (TOTAL) TOTAL LOGIC ELEMENTS TIME EXECUTION (ms) TABLE 6: SUMMARY OF FAST MULTIPLIER PERFORMANCE PARAMETER BASIC MULTIPLIER GENERATOR ACCUMULATOR TOP ENTITY (TOTAL) TOTAL LOGIC ELEMENTS TIME EXECUTION (ms) Figure : User interface on the Altera DE board with its display. ) Input Selection The 8 DPDT toggle switches are used to operate as inputs of multiplicand and multiplier. Based on the pin assignment table, signal SW{} until SW{7} are assigned for multiplicand bit inputs whereas SW{} until SW{7} are assigned for multiplicand bit inputs. As indicator, signal LEDR{} until LEDR{7} are assigned as indicator of multiplicand bit inputs value whereas LEDR{} until LEDR{7} are assigned as indicator of multiplier bit inputs value. In term of top entity architecture, number of logic element that employed in fast multiplier architecture is less than employed in basic multiplier architecture as.7% whereas the time execution of fast multiplier architecture is less as.43% compared to the basic multiplier architecture. Effect of number of bit one in operands bit stream is shown in Fig.. Thee comparison of performance between both multiplier architectures can be seen clearly where the fast multiplier architecture performs better rather than basic multiplier.

6 chip. Altera DE board is used since it provides Cyclone II FPGA chip with number EPC35F67C6. Fig 3(a) and 3(b) show the interface of the Altera DE board. Figure 3(b): Seven segment LED of input and output value display Figure : : Graph time execution versus number of bit one To see the maximum time that can be saved by this fast multiplier, calculation is performed based on the shortest time execution that achieved by this multiplier as shown in Figure. V. CONCLUSION In this paper, we have shown the design of a multiplier that generates product between multiplicand and multiplier in shorter time execution by using Hybrid Modified Booth Encoded Algorithm and Carry Safe Adder techniques. The maximum time saving can be achieved is up to 8.9%. We also manage to reduce the number of logic element in field- element programmable gate array (FPGA). Number of logic is reduced to about.7% compared to basic multiplier architecture. REFERENCES Figure : Simulation waveform of fastest time execution of fast multiplier % % 4 % % According to calculation above, the maximum of time saving that probably can be achieved by fast multiplier architecture is up to 8.9 % compared to basic multiplier. Figure 3(a): LCD command display and LED of toggles switch In order to ensure the synthesizability of the constructed fast multiplier, it is necessary to implement by using FPGA [] Miles J. Murdocca (7). Computer Architecture and Organization. Wiley: John Wiley & Sons. [] Roger Wood (8). FPGA-based Implementationn of Signal Processing Systems. Wiley: John Wiley & Sons. [3] Behrooz Parhami (5). Computer Architecture: From Microprocessors to Supercomputers. The Oxford Series in Electrical andd Computer Engineering. OUP, USA. [4] Frank Vahid (7). VHDL for Digital Design. Wiley: John Wiley & Sons. [5] Gong Renxi, Zhangg Shangjun, Zhang Hainan, Meng Xiaobi,Gong Wenying, Xie Lingling & Huang Yang (9). Hardware Implementation of a High Speed Floating Point Multiplier Based on FPGA. Proceedingss of 9 4th International Conference on Computer Science & Education. [6] Soojin Kim & Kyeongsoon (). Design of High-speed Modified Booth Multiplier Operating at GHz Ranges. Proc., World Academy of Science, Engineeringg and Technology, 6 Jan 5. [7] Umer Nisar Misgar, Wasim Ahmad Khan, & Najeeb-ud-din (9). Design of a Floating Point Fast Multiplier with Mode Enabled. Proc., International MultiConference of Engineer and Computer Scientists, Hong Kong. [8] Prof Loh (5). Carry Save Addition, February, 5. Retrieved on October,,, from [9] Moses C.J., Selvathi D., Beena J.P.. & Rani S.S. (). FPGA accelerated partial volume interpolation. International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), pp [] Yajuan He & Chip-Hong Chang (9). A New Redundant Binary Booth Encoding for Fast n -Bit Multiplier Design. IEEEE Transactions on Circuits and Systems I: Regular Papers, vol 56, issue 6, pp 9.

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