Datapath Components. Multipliers, Counters, Timers, Register Files

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1 Datapath Components Multipliers, Counters, Timers, Register Files

2 Multipliers An N x N multiplier Multiplies two N bit binary inputs Generates an NN bit result Creating a multiplier using two-level logic from a truth table results in too complex a design. 8 A reasonably sized circuit can be designed by evaluating how humans do multiplication.

3 Multiplication Process Multiply two 4-bit numbers: 1100 and (multiplicand) x 0101 (multiplier) 1100 (multiply multiplicand by the multiplier LSB) 0000 (shift by one digit and multiply by next multiplier bit) 1100 (repeat) 0000 (repeat) (sum all the partial products) Each intermediary value is known as a partial product. Partial Products can be obtained by ANDing the corresponding multiplier bit with the multiplicand.

4 Multiplication Process Revisited The process we just evaluated can be rewritten in terms of bit positions as: a3 a2 a1 a0 b3 b2 b1 b0 b0a3 b0a2 b0a1 b0a0 b1a3 b1a2 b1a1 b1a0 b2a3 b2a2 b2a1 b2a0 b3a3 b3a2 b3a1 b3a0 p7 p6 p5 p4 p3 p2 p1 p0 (pp1) (pp2) (pp3) (pp4) After generating the partial products, we sum them together

5 Multiplier Circuit a3 a2 a1 a0 b0 b1 pp1 pp2 0 0 b2 (5-bit) b3 pp3 pp (6-bit) A * P B (7-bit) p7..p0 Block symbol 5

6 Arithmetic Logic Unit (ALU) An ALU is a combinational component designed to perform many different mathematical operations. Generally built one of three ways: All mathematical operations are done in parallel and one result is selected using a mux. Based on a single adder with combinational logic that controls the mode. A combination of the previous two methods

7 Parallel Computation ALU Can build using separate components for each operation, and muxes Too many wires, also wastes power computing operations when only use one result at given time Inefficient for large designs DIP switches 8 8 A B 1 AND OR XOR NOT Wasted power 1 0 x s2 y 8-bit 8x1 s1 z s0 clk e Id 8 8-bit register 8 A lot of wires CALC LEDs

8 Single Adder ALU More efficient design uses a single adder ALU design not just separate components multiplexed (same problem as previous slide) Instead, ALU design uses single adder, plus logic in front of adder s A and B inputs Logic in front is called an arithmetic-logic extender Extender modifies A and B inputs so desired operation appears at output of the adder A B a7 b7 a6 b6 a0 b0 x y z AL-extender x y z AL-extender IA IB Adder cin IS ALU S (a) abext abext abext cinext ia7 ib7 ia6 ib6 ia0 ib0 cin (b) a

9 Arithmetic-Logic Extender A B a7 b7 a6 b6 a0 b0 x y z AL-extender x y z AL-extender ALU IA IB Adder cin abext abext abext cinext ia7 ib7 ia6 ib6 ia0 ib0 xyz=000 Want S=AB : just pass a to ia, b to ib, and set cin=0 xyz=001 Want S=A-B : pass a to ia, b to ib and set cin=1 (two s complement) xyz=010 Want S=A1 : pass a to ia, set ib=0, and set cin=1 xyz=011 Want S=A : pass a to ia, set ib=0, and set cin=0 xyz=100 Want S=A AND B : set ia=a*b, b=0, and cin=0 Others: likewise Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and create logic for cin(x,y,z), to complete design of the AL-extender component IS S (a) (b) cin

10 Bit shifter A combinational logic construct to shift bits. Similar to a shift register, but has no storage Associated with the symbols << M (Shift Left M bits) >> M (Shift Right M bits) Simple Shifter Shifts N-bit data by a fixed amount, M May be designed to shift left, right, or not at all. Shift Multiplication Shifting by one bit multiplies or divides by 2

11 Barrel Shifter An N-bit shifter that can shift any number of positions. Left Barrel Shifter Constructed by using multiple simple bit shifters that shift by powers of two, if enabled.

12 Counters Counters are sequential components that maintain an internal count variable that can be incremented or decremented. Types UP only Down only Bidirectional Counters roll over when exceeding their bit resolution i.e. a 4 bit up-counter goes from 0 to 15 and then wraps back around to 0. Think of it as a clock rolling from 12 to 1. Counters generally have a bit that indicates they have reached the extent of their range.

13 N-bit Up Counter The count output (C) counts up from zero to 2 N. Terminal Count (tc) is asserted when the count is equal to 2 N. S[3:0] a[3:0] cnt clr clk D_Reg_PL_Rst_4bit D[3:0] Q[3:0] Load Rst QN[7:0] C[3:0] C[3] C[2] C[1] Incr_4bit AND4 co C tc C[0]

14 N-bit Down Counter To create a down counter from an UP counter Replace the incrementer with a decrementer. Replace the AND with a NOR S[3:0] a[3:0] cnt clr clk D_Reg_PL_Rst_4bit D[3:0] Q[3:0] Load Rst QN[7:0] C[3:0] C[3] C[2] C[1] C[0] Decr_4bit NOR4 co C tc

15 N-bit Bidirectional Counter mux_2_1_4bit Implement the logic of both UP and DOWN counters Select between them using MUXes cnt clr clk I1[3:0] D[3:0] I0[3:0] S D_Reg_PL_Rst_4bit D[3:0] Q[3:0] Load Rst QN[7:0] C[3:0] C[3] C[2] a[3:0] a[3:0] Decr_4bit Incr_4bit S[3:0] co S[3:0] co C C[1] AND4 C[0] mux_2_1 C[3] C[2] I1 I0 S D tc C[1] C[0] NOR4 dir

16 Counter with Load Add a mux to the register input. Select between loading next count of a new value. L[3:0] load cnt clr clk OR mux_2_1_4bit I1[3:0] D[3:0] I0[3:0] S D_Reg_PL_Rst_4bit D[3:0] Q[3:0] Load Rst QN[7:0] C[3:0] C[3] C[2] C[1] C[0] S[3:0] a[3:0] Incr_4bit co AND4 C tc Up counter with load

17 Modulo Counter Some times it is desirable to stop counting before the end of the counter s bit range. This can be done using external logic to reset the counter when the desired upper limit is reached. Example: Design a circuit that counts from 0 to using the given counter. L[4:0] cnt C[3:0] load up_cnt_4bit clr clk Question: Can you design a circuit that starts counting at 2 instead of 0

18 Clock Divider It is often useful to generate a slower clock. For a small duty cycle, you can use the tc output as a clock signal. For a large duty cycle, extra combinational logic is required to generate the clock cycle Example: Create a circuit using a 4-bit counter to create a % 4 clock divider.

19 Measuring Time Counters may also be used to measure time. We know the frequency of the clock signal, so we know how long it takes between counts. Example: If we have a 25 MHz clock (40 ns period), how much time has passed in 15 clock ticks

20 Timers Timers repeatedly assert a signal, Q, after a predetermined time. Can be made in a similar fashion to the modulo counter. When count is reached, reset the circuit and assert Q. Example: Create a timer that asserts Q after 120ns using a 25Mhz clock.

21 Variations on the Basic Timer One-shot Only asserts the output Q once and then must wait to be enabled again. Pulse Width Modulator Has a second register that sets the amount of time Q is held HIGH. Very similar to a clock divider Allows you to control the duty cycle.

22 Register Files Register Files are an array of memory. Provides quick, efficient access to storage. Generally defined as 姐 ϷM x N, where M is the number of registers in the file and N is the bitlength of each register. A particular register is accessed via its address, a unique binary code that represents the register. Generally allows both read & write access.

23 Why Use Register Files Why not just use a lot of registers Theoretically, a gate has infinite input impedance and zero output impedance 裰 Ћ If true, a gate output could drive an unlimited number of gate inputs. Realistically, gates have limited fan-out. It is not possible for a single gate to drive a large number of registers. Register files solve this by ensuring only one gate is read or written at a time.

24 Register File Symbol MxN register file: Efficient design for one-at-atime write/read of many registers 泀 ϵ Called write port a N-bit data to write log 2 (M) -bit address specifies which register to write Enable (load) line: Reg written on next clock N W_data log 2 (M) W_addr W_en register file R_data R_addr R_en N log 2 (M) N-bit data that is read M-bit address to specifies which register to read Enable read read port

25 4.10 Register Files Addresses are inputs to decoders to select the correct register Write decoder sets the load signal. Read multiplexor enables one and only one buffer to drive the read output. Accessing one of several registers is: OK if just a few registers Problematic when many Ex: 16 registers Too much fanout (branching of wire): Weakens signal Many wires: Congestion C 4 load load C 8 d0 d0 4x162 4 d1 a0 i0 i3-i0i1 a1 d2 e 32 d3 d15 e load load reg0 reg0 too much loadfanout reg1 load reg2 load load reg3 reg15 T A I M bit registers tolerable bit registers begins to have fanout and wire problems huge mux i0 i0 32-bit 8-bit 16x1 4 1 i1 d d DD 328 i2 congestion i15i3 s1 s0 s3-s0 x y 25 a 16*32 = 512 wires

26 Register File Internal design uses drivers and bus a d driver d q=d c q Boosts signal three-state driver q W_data 1 W_addr 1 W_en 1 i0 i1 2x4 32 d0 d1 d2 write decoder d3 e Ї 1 load load load load 4x32 register file reg0 reg1 reg2 reg bus driver 32 R_data d0 d1 d2 2x4 i0 i1 read decoder d3 e Internal design of 4x32 RF; 16x32 RF follows similarly a R_addr R_en 1 c=1: q=d d q c=0: q= Z d q like no connection Notice the shared bus. R_data is written to by multiple three state buffers, but only one at a time. Note: Each driver in figure actually represents 32 1-bit drivers 26

27 Register File Timing Diagram clk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle Can write one register and read one register each clock cycle May be same register W_data W_addr W_en R_data R_addr R_en 3 Z X 22 X 1 X X X 2 3 Z Z Z X 3 X W_data W_addr R_data R_addr : 1: 2: 3: 0: 1: 2: 3: 0: 1: 2: 3: 22 0: 1: 2: 3: 22 0: 1: 2: 3: 22 0: 1: 2: 3: : 1: 2: 3: W_en 4x32 register file R_en 27

ECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice

ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit