Cascode Configuration

Transcription

1 EE 330 Lecture 34 Some dditional nalo Circuits The Cascode Confiuration Darlinton Confiuration Other Special Confiurations The Differential mplifier Cascade mplifiers mplifier Biasin Diital Loic

2 Review from Last Lecture Cascode Confiuration Discuss I B m1 m1 VCC β β VXX 0CC 02 β m1 2VF VCC β= Vt 800, 000 VCC This ain is very lare and only requires two transistors! What happens to the ain if a transistor-level current source is used for I B?

3 Cascode Confiuration I B Q 3 VXX VXX

4 Cascode Confiuration Q 3 Q 3 VXX

5 Hih-ain amplifier comparisons Q 3 0CC V 1 πcc VCC V 1 03 It thus follows that 0CC V VCC CC = But 0CC ; 03 /β V VCC 0CC 03 VCC This is a dramatic reduction in ain compared to what the ideal current source biasin provided β

6 Cascode Confiuration Q 3 V VCC But recall Thus VCC V 0CC 03 m1 01 m1 01 VCC ICQ V V t V F 8000 I CQ Vt VF This is still a factor of 2 better than that of the CE amplifier with transistor current source m1 VCE 201 It only requires one additional transistor But its not nearly as ood as the ain the cascode circuit seemed to provide β

7 Cascode Confiuration Comparisons I B V EE V - m 0 V EE V -m1-2 m I B Q 3 VXX V m1 01 β VXX V m1 m Gain limited by output impedance of current scource!! Can we desin a better current source? In particular, one with a hiher output impedance?

8 Better current sources Need a hiher output impedance than o The output impedance of the cascode circuit itself was very lare! 0CC 01 β Can a current source be built with the cascode circuit?

9 Cascode current sources I X I X V XX I X V XX M 2 Discuss I X V XX V XX M 2 I X I X

10 Cascode Confiuration Discuss VXX V ZZ Q 3 Q 4 m1β V= V= ,000 2 This ain is very lare and is a factor of 2 below that obtained with an ideal current source biasin lthouh the factor of 2 is not desired, the performance of this circuit is still very ood This factor of 2 ain reduction is that same as was observed for the CE amplifier when a transistorlevel current source was used

11 Cascode Confiuration Comparisons I B I B Discuss V EE V - m 0 V = -8,000 V EE V - 2 m1 01 V = -4,000 VXX V m1 01 V = -800,000 β V ZZ Q 3 Q 3 Q 4 VXX V m1 01 V = -8,000 VXX m1β V= 01 2 V = -400,000 Can we use more cascodin to further increase the ain?

12 Hih Gain mplifiers Seldom Used Open Loop I B V - m 0 VXX V ZZ Q 3 Q 4 m1β V= 01 2 Discuss V EE V = -8,000 V = -400,000 V V V OUT IN OUTQ If V =-400,000 and increases by 1mV, what would happen at the output? would decrease by 400,000 x 1mV=-400V

13 The Cascode mplifier (consider n-ch MOS version) Discuss I B VXX M 2 VCC - 0CC m1 m m2 Same issues for biasin with current source as for BJT case With cascode current source, ain only drops by a factor of 2

14 The Cascode mplifier (consider n-ch MOS version) Discuss I B V ZZ M 3 M 4 V ZZ M 3 VXX M 2 VXX M 2 VXX M 2 VCC - m1 m VCC - m m1 m2 VCC

15 Current Source Summary (BJT) Basic Cascode I X I X V XX I X V XX I X / CC 01 β

16 Current Source Summary (MOS) Basic Cascode I X I X VXX M 2 V ZZ M 2 I X I X m2

17 Hih Gain mplifier Comparisons ( n-ch MOS) I B I B V ZZ M 2 V XX M 2 V ZZ M 3 V ZZ M 4 M 3 V - m m1 V VCC - m1 m M 2 V XX VCC - m1 01 M 2 VXX 1 m1 m2 VCC

18 Hih Gain mplifier Comparisons (BJT) I B I B VXX V V EE - m 0 V V EE 2 1 m1 01 V m1 01 β VXX Q 3 VXX V ZZ Q 3 Q 4 Sinle-ended hih-ain amplifiers inherently difficult to bias (because of the hih ain) Biasin becomes practical when used in differential applications These structures are widely used but usually with differential inputs V m1 01 m1β V= 01 2

19 The Cascode mplifier Operational amplifiers often built with basic cascode confiuration CMFB used to address the biasin problem Usually confiured as a differential structure when buildin op amps Have hih output impedance (but can be bufferred) Terms telescopic cascode, folded-cascode, and reulated cascode often refer to op amps based upon the cascode confiuration V B1 M 5 M 6 V B2 M 7 M 8 V B3 M 3 M 4 M 2 I T V B5 1 Telescopic Cascode Op mp (CMFB feedback biasin not shown)

20 Cascade Confiurations I B1 I B2 I B1 I B2 M 2 Two-stae CE:CE or CS:CS Cascade? VCB VCM?

21 Cascade Confiurations I B1 I B2 I B1 I B2 M 2 Two-stae CE:CE or CS:CS Cascade VCB - - β + m1 m2 m1 m2 m VCM - - m1 m2 m1 m Sinificant increase in ain Gain is noninvertin Comparable to that obtained with the cascode but noninvertin

22 Cascade Confiurations V XX Q 3 Q 4 V XX M 3 M 4 M 2 VCB - - β m1 m2 m1 m2 m VCM Two-stae CE:CE or CS:CS Cascade m1 m2 m1 m Note factor or 2 and 4 reduction in ain due to actual current source bias

23 Cascade Confiurations I B1 I B2 I B1 I B2 I B3 Q 3 V EE Two-stae CE Cascade Three-stae CE Cascade Lare ains can be obtained by cascadin Gains are multiplicative (when loadin is included) Lare ains used to build Op mps and feedback used to control ain value Some attention is needed for biasin but it is manaeable Minor variant of the two-stae cascade often used to built Op mps Compensation of two-stae cascade needed if feedback is applied to maintain stability For many years three or more staes were seldom cascaded because of challenes in compensation to maintain stability thouh recently some industrial adoptions

24 Differential mplifiers R 1 1 R 2 2 V 1 V 2 I TIL Basic operational amplifier circuit

25 mplifier Biasin mplifier biasin is that part of the desin of a circuit that establishes the desired operatin point (or Q-point) Goal is to invariably minimize the impact the biasin circuit has on the small-sinal performance of a circuit Usually at most 2 dc power supplies are available and these are often fixed in value by system requirements this restriction is cost driven Discrete amplifiers invariable involve addin biasin resistors and use capacitor couplin and bypassin Interated amplifiers often use current sources which can be used in very lare numbers and are very inexpensive

26 Example: V out mplifier Biasin R L V in =- R V m L Desired small-sinal circuit Common Emitter mplifier V in R B1 R C1 C 1 C 2 B C E V out R L V out R B2 R E1 C 3 R L //R C1 Biased circuit V in R B1 //R B2 ctual small-sinal circuit =- R //R V m L C1

27 Example: mplifier Biasin V out R L V in Desired small-sinal circuit Common Emitter mplifier V in R B1 R C1 C 1 C 2 B C E V out R L R B2 R E1 C 3 Biased small-sinal circuit

28 Example: mplifier Biasin V in R L V out Desired small-sinal circuit Common Collector mplifier V in V out I B R L Biased circuit

29 Example: mplifier Biasin R 2 V in R 1 V out Desired small-sinal circuit Invertin Feedback mplifier R 2 V in R 1 V out Biased circuit

30 Other Basic Confiurations C B E Darlinton Confiuration Current ain is approximately β 2 Two diode drop between B eff and E eff

31 Other Basic Confiurations C B E Sziklai Pair Same basic structure as Darlinton Pair Current ain is approximately β n β p Current ain will not be as lare when β p < β n Only one diode drop between B eff and E eff

32 Other Basic Confiurations I B1 I B2 M 2 M 2 R L I B2 I B1 (optional) R L (c) (d) Buffer and Super Buffer I B1 Voltae shift varies with in buffer Current throuh shift transistor is constant for Super Buffer as chanes so voltae shift does not chane with Same nominal voltae shift (a) R L (b) R L

33 Other Basic Confiurations Low offset buffers I B2 I B2 Z L M 2 Z L I B1 I B1 V EE ctually a CC-CC or a CD-CD cascade Sinificant drop in offset between input and output Biasin with DC current sources Can dd Super Buffer to Output

34 Voltae ttenuator Other Basic Confiurations M 2 ttenuation factor is quite accurate (Determined by eometry) Infinite input impedance in triode, M 2 in saturation ctually can be a channel-tapped structure

35 End of Lecture 34

36 Diital Circuit Desin Most of the remainder of the course will be devoted to diital circuit desin 3.5V F C M6 B M5 M4 F C M3 B M2 Verilo module ates (input loic [3:0] a,b, output loic [3:0] y1,y2,y3,y4,y5); assin y1 = a&b; //ND assin y2 = a b; //OR assin y3 = a ^ b; //XOR assin y4 = ~(a & b); //NND assin y5 = ~( a b); //NOR endmodule renderin of a small standard cell with three metal layers (dielectric has been removed). The sand-colored structures are metal interconnect, with the vertical pillars bein contacts, typically plus of tunsten. The reddish structures are polysilicon ates, and the solid at the bottom is the crystalline silicon bulk Standard Cell Library library IEEE; use IEEE.STD_LOGIC_1164.all; entity ates is port(a,b: in STD_LOGIC_VECTOR(3 dowto 0); y1,y2,y3,y4,y5:out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of ates is bein y1 <= a and b; y2 <= a or b; y3 <= a xor b; y4 <= a nand b; y5 <= a nor b; end; VHDL M1

37 Diital Circuit Desin Hierarchical Desin Basic Loic Gates Properties of Loic Families Characterization of CMOS Inverter Static CMOS Loic Gates Ratio Loic Propaation Delay Simple analytical models Elmore Delay Sizin of Gates Propaation Delay with Multiple Levels of Loic Optimal drivin of Lare Capacitive Loads Power Dissipation in Loic Circuits Other Loic Styles rray Loic Rin Oscillators

38 Hierarchical Diital Desin Domains: Behavioral: Top Structural: Physical Bottom Multiple Levels of bstraction

39 Bottom Up Desin Hierarchical Diital Desin Domains: Top Behavioral: Structural: Physical Top Down Desin Bottom

40 Bottom Up Desin Hierarchical Diital Desin Domains: Top Behavioral: Structural: Top Down Desin Physical Multiple Sublevels in Each Major Level Bottom ll Desin Steps may not Fit Naturally in this Description

41 Bottom Up Desin Hierarchical nalo Desin Domains: Top Behavioral: Structural: Physical Top Down Desin Bottom

42 Hierarchical Diital Desin Domains: Behavioral : Describes what a system does or what it should do Structural : Identifies constituent blocks and describes how these blocks are interconnected and how they interact Physical : Describes the constituent blocks to both the transistor and polyon level and their physical placement and interconnection Multiple representations often exist at any level or sublevel