2. (2 pts) What is the major reason static CMOS NAND gates are often preferred over static CMOS NOR gates?

Transcription

1 EE 330 Final Exam Spring 05 Name Instructions: Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 0 questions and 8 problems. There are two points allocated to each question. All problems are worth 0 points. Please solve problems in the space provided on this exam. Attach extra sheets only if you run out of space in solving a specific problem. If references to semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; ncox=00 A/V pcox= ncox/3,vtno=0.5v, VTPO= - 0.5V, COX=fF/, = 0, and If reference to a bipolar process is made, assume this process has key process parameters for an npn transistor of JS=0-5 A/, βn=00 and VAFn = and those for a pnp transistor are JS=0-5 A/, βp=0 and VAFp =. If any other process parameters are needed, use the process parameters associated with the process described in the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Several tables that may be of use are appended at the end of the exam.. ( pts) What is the major reason the CMOS processes replaced NMOS processes as the process technology of choice for most integrated circuits today?. ( pts) What is the major reason static CMOS NAND gates are often preferred over static CMOS NOR gates? 3. ( pts) It was observed in some processes that we considered in class that sizing of a digital inverter to put the trip point at VDD/ resulted in equal rise and fall times. Why did this happen?. ( pts) In a 6-input NAND gate sized for equal worst-case rise and fall times and an overdrive factor of 5, how should the p-channel transistors be sized? Give response relative to Lmin and Wmin in the process. Page of

2 5. ( pts) How does polysilicon differ from substrate silicon in a bulk CMOS process? 6. (pts) Why are current sources often used in biasing amplifiers in integrated circuits instead of resistors and capacitors? 7. ( pts) Give the name of the Iowa native that was the co-inventor of the integrated circuit. 8. ( pts) The actual length of a minimum-sized transistor in a bulk CMOS process is usually somewhat smaller than the length of the transistor drawn during layout. What is the major reason that the length decreases during fabrication? 9. (pts) What would be the voltage gain of the basic common-emitter amplifier if an ideal current source was available for biasing the collector current? V CC I B V out V IN V EE 0. (pts) The gate is self-aligned in bulk CMOS processes. What does it mean to be self-aligned? Page of

3 Problem Two polysilicon interconnects that are 00 µm long are shown. The upper one is µm wide and the lower one is µm wide. Assume the inputs A and B both transition from 0V to VDD=3.5V at t=0. At what time will the Boolean output G of the NAND gate go low? Assume the NAND gate is sized for equal rise/fall times with an of. Assume this interconnect is in the process characterized by the description in the attachment at the end of this exam. A reference inverter in this process is shown below. A μm D G B μm E 0fF Page 3 of

4 Problem Consider a process where the fabrication cost of 8 wafers is $000 and the defect density is.5/cm. What is the largest die area that can be used in the design of an integrated circuit if the cost per good die is to be at much $0.5. Page of

5 Problem 3 Assume VTH for the MOS transistor is 0.5V. a) Draw the small signal equivalent circuit b) Derive an expression for the voltage gain in terms of the small-signal model parameters of the transistor and the resistors in the circuit c) Numerically determine the small-signal voltage gain 5V 500K K C V out V IN C A E =00u K Page 5 of

6 Problem An interface circuit that interfaces between logic circuits with a V supply voltage on the left and a V supply voltage on the right is shown below. It is comprised as a cascade of two inverters, one operating with a V supply voltage and the other with a V supply voltage. Correspondingly the threshold voltages of the V logic circuits and the V logic circuits are different and are as indicated on the figure. The inverter on the left is sized for equal rise and fall times. Size the inverter on the right side of the interface circuit so that it has a trip point at.5v and an HL of relative to that of a reference inverter in the same process that has the n-channel device sized with W=Wmin and L=Lmin. Assume Lmin in both the high and low voltage circuits is 0.5µm. V V M M V A VB M M 3 V Logic V Logic V THn = 0.V V THp = -0.V V THn = 0.8V V THp = -0.8V Interface Circuit Page 6 of

7 Problem 5 A segment of a logic block is shown below. Assume the lengths of all devices are LMIN. Assume the overdrive factors of all gates, relative to that of an equal rise/fall reference inverter, are as indicated. Gates with no overdrive factor shown have an overdrive of. Assume that the process in which these gates are fabricated is characterized by a minimum length reference inverter with tref=0ps, CREF=fF, RPDREF=.5K a) Determine the worst-case propagation delay from A to G b) Repeat part a) if all gates are minimum sized A 6 G 0fF F 6fF C B 6fF H 6 Page 7 of

8 Problem 6 Consider the four-stage pad driver with equal rise and fall times shown below. With this pad driver, the overdrive increases alternately by a factor of 3,,3, instead of,,, or 3,3,3,3. Assume the supply voltage is V and the devices are sized with L=LMIN and the widths are selected to obtain the overdrives indicated. A reference inverter in the process used for the pad driver is shown below. a) Determine the dynamic power dissipation in the third stage if the input is a square wave of frequency 500 MHz b) Determine the propagation delay from A to F. A F ff Page 8 of

9 Problem 7 large. Consider the amplifier block shown below. Assume the capacitor is a) Draw the small-signal equivalent circuit of this amplifier b) Determine the small-signal voltage gain in terms of the model parameters of the transistors and the components in the circuit c) Numerically determine the small signal voltage gain 5V 0K K C A E =00u W=00u L=u V out V IN 5K K 300 Page 9 of

10 Problem 8 Consider the following amplifier where the capacitor C is large. a) Determine the bias current IB that will make the quiescent drain voltage = 0V. b) Draw the small-signal circuit c) Numerically determine the voltage gain if the bias current IB is at the value determined in part a)..5v 0K 0K V out W=5u L=0u V IN I B C -.5V Page 0 of

11 TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS MINIMUM 3.0/0.6 Vth volts SHORT 0.0/0.6 Idss ua/um Vth volts Vpt volts WIDE 0.0/0.6 Ids0 <.5 <.5 pa/um LARGE 50/50 Vth volts Vjbkd. -.7 volts Ijlk <50.0 <50.0 pa Gamma V^0.5 K' (Uo*Cox/) ua/v^ Low-field Mobility cm^/v*s COMMENTS: XL_AMI_C5F FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS Vth Poly >5.0 <-5.0 volts PROCESS PARAMETERS N+ACTV P+ACTV POLY PLY_HR POLY MTL MTL UNITS Sheet Resistance ohms/sq Contact Resistance ohms Gate Oxide Thickness angstrom PROCESS PARAMETERS MTL3 N\PLY N_WELL UNITS Sheet Resistance ohms/sq Contact Resistance 0.78 ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV POLY POLY M M M3 N_WELL UNITS Area (substrate) af/um^ Area (N+active) af/um^ Area (P+active) 308 af/um^ Area (poly) af/um^ Area (poly) 53 af/um^ Area (metal) 3 3 af/um^ Area (metal) 3 af/um^ Fringe (substrate) af/um Fringe (poly) af/um Fringe (metal) 55 3 af/um Fringe (metal) 8 af/um Overlap (N+active) 06 af/um Overlap (P+active) 78 af/um Page of

12 Page of

13 Propagation Delay in Logic Circuits with and Asymetry M HL LH Equal Rise/Fall Equal Rise/Fall (with ) Minimum Sized Asymmetric ( HL, LH ) C IN /C REF Inverter NOR NAND 3k+ 3+k 3k+ 3+k / / / HL +3 LH HL +3k LH k HL +3 LH Overdrive Inverter HL HL LH NOR HL /3 LH HL LH NAND HL /(3k) /k LH HL LH /3 LH t PROP /t REF n k= F n FI(k+) I(k+) k= n n FI(k+) FI(k+) k k= HLk LHk k= HLk LHk Page 3 of

14 Page of