UNIVERSITY OF CINCINNATI

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1 UNIVERSITY OF CINCINNATI Date: September 30,2005 I, Rahul Madhusudanan, hereby submit this work as part of the requirements for the degree of: M.S. in: Electrical Engineering It is entitled: Development of Digital and Mixed Signal Standard Cells CMOS Process This work and its defense approved by: Chair: Dr. Fred.R.Beyette Jr. Dr. Hal Carter Dr. Carla Purdy

2 Development of Digital and Mixed Signal Standard Cells for a 0.25µm CMOS Process A thesis submitted to the Division of Graduate Studies and Research of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Electrical and Computer Engineering and Computer science of the College of Engineering 2005 by Rahul Madhusudanan Committee Chair: Dr. Fred Beyette Jr.

3 Development of Digital and Mixed Signal Standard Cells for a 0.25µm CMOS Process Rahul Madhusudanan Abstract. The competitiveness of the semiconductor market makes the tradeoffs between performance, cost and time to market very crucial. The current scenario is such that the non-recurring expenses involved in the design process, like design and tooling costs, dwarf the actual cost of producing the chip; termed as the recurring expenses. Unfortunately, high non-recurring costs can make it impossible for many smaller companies to remain profitable. The standard cell library used in higher-level synthesis and placement steps is one of the significant cost incurring steps of the design flow. The proposed thesis develops a 32-cell library for the TSMC quarter micron process using a unique and cost effective design flow, where only non-commercial tools available in the open domain are used. The custom design flow used is discussed in detail. An overview of other similar CAD resources available in the open domain is also presented. Such a flow, although time intensive, is a cost effective alternative for smaller ventures.

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5 Acknowledgments First and foremost, I would like to thank and express my deep gratitude to my faculty advisor Dr.Fred. R. Beyette Jr for giving me an opportunity to attain my Master s degree at the University of Cincinnati and for his excellent guidance and support throughout this project. I also want to express my appreciation to Dr Harold Carter and Dr Carla Purdy for serving on my thesis committee. I would like to thank and acknowledge the help and support of Mathew Francis Kottoor who was a part of this project. I am also thankful to the members of the PSDL laboratory at the University of Cincinnati for their support and inspiration throughout my project. A special thanks is to be given to Vijay Sundaresan for the various discussions and suggestions through my project work. I want to express my gratitude to the technical staff, Rob Montjoy and Chris Isbell, for providing the help for the equipment, installation and their upkeep.

6 Table of Contents Chapter 1: Introduction Introduction Design Techniques Custom Design Semi-custom design Standard Cells The monetary aspects: A perspective Chapter 2: Scope and Description of the Thesis Overview Cells included in the library Process Details Design Rules Cell library design techniques Low Power Optimization High Speed Optimization Minimal Area Optimization Design Flow Design Specifications Schematic Capture Symbol Creation Pre-Layout Simulation Layout Design Rule Check Extraction Layout Verses Schematic Check Post-Layout Simulation Characterization Documentation Special features of standard libraries Analog Standard cells CMOS Analog Standard Cell Design Considerations Tools involved in the Design Process Spice Models used..22 Chapter 3: Custom Design Flow Description Introduction Schematic GSchem : An Overview i

7 3.2.2 Schematic of 2 Input NOR Gate Schematic Verification Physical Layout Layout Guidelines Extraction Layout Versus Schematic Netgen: An Overview Post-Layout Simulation Chapter 4: Design and Simulation of cells Chapter Overview Tri-state buffer Circuit Diagram Simulation results Analog Comparator Original Comparator Design Drawback of the design Improved Design Operational Amplifier A 2 stage buffered operational amplifier Operational amplifier parameters Feedback in an operational amplifier Compensation Design of the 2 stage operational amplifier Design of the current mirror Characterization of the operational amplifier Open loop configuration Closed loop configuration Measurement of Offset Voltage Measurement of Output Swing.59 Chapter 5: Conclusion Introduction Possible future developments Conclusion References: Appendix A Documentation Appendix B Alternate CAD Environments Appendix C Spice Models ii

8 Table of Figures Figure 1.1 Semi-custom Design Methods. 4 Figure 2.1. Bottom-up Design Flow. 14 Figure 2.2 Rail Sizes and routing layers Figure Input NOR Gate Circuit Diagram.. 25 Figure Input NOR Gate Schematic Diagram.. 27 Figure 3.3 Spice Simulation of the netlist from the Schematic...29 Figure 3.4 Physical Layout of the 2-Input NOR Gate. 30 Figure 3.5 Transfer characteristics (Input vs Output) of the 2-Input NOR Gate.35 Figure 3.6 Post Layout Simulation Results Figure. 4.1 Tri-State Buffer Circuit Diagram. 38 Figure. 4.2 Tri-State Buffer Simulation Waveforms 40 Figure. 4.3 Analog Comparator Circuit Diagram. 41 Figure. 4.4 Simulation waveforms when V in is close to V ref 43 Figure. 4.5 Modified circuit diagram of the comparator.. 44 Figure. 4.6 Simulated waveforms of the modified comparator when V in is close to V ref.45 Figure. 4.7 Operational Amplifier circuit diagram.. 47 Figure. 4.8 Opamp transfer function with negative feedback Figure. 4.9 Circuit Diagram of a current mirror Figure Opamp in an open loop configuration. 55 Figure Frequency response of output voltage. 56 Figure Frequency response of phase 56 Figure Opamp in a closed loop unity-gain configuration 57 Figure DC Sweep response of output.. 57 Figure Opamp circuit to measure offset voltage.. 58 Figure DC Sweep response of output for measurement of offset voltage.. 58 Figure Opamp circuit to measure output voltage swing. 59 Figure DC Sweep response for measurement of output voltage swing.. 59 iii

9 CHAPTER I Introduction. 1

10 1.1 Introduction. The semiconductor industry is arguably among the most revolutionized sectors in the last two-dozen years. The growth in semiconductor chip complexity and fast reduction in manufacturing costs have meant that technological advances have become important factors in economic, organizational, and social change. In fact, during the last decades a good first approximation for long-range planning has often been that information processing capacity is essentially free and technical possibilities are unlimited. The semiconductor industry has developed in such a flexible fashion that it now accommodates a huge number as well as a wide range of companies and consortiums with varied needs and monetary backings. This ranges from small low capital specialized companies to large multinational corporations with a broad product portfolio and significant investment and infrastructures. 1.2 Design Techniques. The type of design technique used mainly depends on the application that the design is being used for. It is a trade off between factors like performance requirements of the designed system, time-to-market and cost involved in the design process etc. The design process can be broadly classified into 1. Custom design 2. Semi custom design 2

11 1.2.1 Custom Design. Custom design is mainly done for applications in which performance is the most important criteria. The chip is specially designed from the beginning giving a design that is fully customized to a given specification. The design is usually done at the transistor level with little or no usage of pre-defined cells. This process takes a comparatively longer time to finish than semi-custom design, and hence is economic only at high volumes where the cost per unit is usually high because of the large Non-recurring Expenses involved. Custom design is usually a good approach for processor data paths, memories etc Semi custom design. In a semi-custom VLSI design process, the designer typically works with a set of Standard cells which can be connected to produce the desired functionality. In semicustom design, the designer accepts restrictions in order to simplify the design process. There is a wide variety of semi custom design options depending on requirements like performance, unit cost, design time etc. For example PLA s and Gate Arrays are good options to reduce the design time. 3

12 Fig 1.1 Semi-custom Design Methods. 1.3 Standard Cells. Standard cells consists of pre-designed and pre-verified logic blocks that help designers to shorten product development time and manage the complexity of a chip having millions of logic gates or more. In standard-cell design basic gates or building blocks like multiplexers, full adders, flip-flops and basic logic functions are provided by a chip vendor. A Standard cell library consists of cells or macro cells based on unique layouts that designers use to implement the desired functionality in their ASIC. The economic and efficient accomplishment of an ASIC design depends heavily upon the choice of the library. As opposed to the array based methods, this requires the production of a unique full mask set and hence is viable at higher production volumes [1]. 4

13 1.4 The monetary aspects: A perspective. A rough idea of the cost involved in the production of a semiconductor device would be helpful in putting this thesis into perspective. The incurred costs are of two types. 1. Recurring expenses: This involves the cost of the wafer, the processing and fabricating expenses, packaging, testing etc that are to be done on every unit that is produced. 2. Non-Recurring expense. This is the cost that covers the design and pre-production phases of the product including salaries, CAD tool costs, masks etc and the post-production costs like product support. For a 100nm technology node, manufacturing NRE (mask set and probe card) costs are nearing $1 million for a large IC. With an average of just 500 wafers produced from each mask set, rapid growth of manufacturing NRE can throttle the initiation of new IC design projects. However, design NRE costs, which routinely reach tens of millions of dollars, dwarf manufacturing NRE costs [2]. And the increasing complexity of the designs is bound to increase the NRE cost along with the time-to-market for the product. This will make it tougher for smaller companies to successfully introduce products into the market and stay profitable. 5

14 The thesis work can assist in reducing the part of this NRE cost attributed to purchasing industry standard CAD tools and libraries. This, obviously, comes at the expense of some compromises like lack of additional support, time spent in functionality verification etc. But the expense saved in either purchase of a library or custom design and the time reduced in the production cycle make this a viable choice for smaller companies. 6

15 CHAPTER II Scope and Description of the Thesis. 7

16 2.1 Overview. The proposed thesis aims to design a standard cell library to be made available in the public domain after successful verification and characterization. The design is to be made entirely using open domain CAD tools throughout the design process. This is to avoid copyright issues that might be involved. This will then, hopefully, facilitate faster design times to silicon for smaller companies or even individual design efforts, which would otherwise have used a custom design approach. The library is being made for the TSMC 0.25µ sub-micron process. 2.2 Cells included in the library. The designed library is a 32-cell library. The library includes the basic digital cells and some analog standard cells. The list of cells to be included in the library is given in Table The entire design effort is being split between a colleague and me. I have designed the cells highlighted in bold. Further details of my colleague s portion of the work can be found in the thesis titled Development of a standard cell library based on deep submicron SCMOS design rules using open source software. 8

17 Digital Cells Analog Cells NAND (Fan-In 2) NAND (Fan-In 3) NAND (Fan-In 4) NOR (Fan-In 2) NOR (Fan-In 3) NOR (Fan-In 4) Inverter Inverter (Fan-Out 4) Buffer Buffer (Fan-Out 4) Tri-state Buffer D-Flip Flop D-Flip Flop with Clear D-Flip Flop with Preset D-Flip Flop with Preset and Clear Latch Latch with Clear Latch with Preset Latch with Preset and Clear Schmitt Trigger Full Adder Full Compare Comparator Differential Amplifier Common Source N Common Source P Digital-to-Analog Converter Analog-to-Digital Converter Operational Amplifier Analog Multiplier Analog Adder Analog Subtracter Table Standard Cells to be included in the library. 2.3 Process Details. The library is being designed for the Taiwan Semiconductor (TSMC) 0.25 Micron CL025/CM025 Process. The process uses 5 metal layers and 1 poly layer. The CM025 Process is a mixed signal process and is fully compatible with CMOS logic. It features deep N-well devices, devices with multiple V t, precision high poly resistors, mixed signal 9

18 application friendly diodes etc. Further details regarding the process can be obtained from the TSMC website [3]. The spice models for these specific processes can be obtained for simulation purposes from MOSIS [4]. 2.4 Design Rules. Designs can be done using a) Process or Vendor specific design rules. These are specified by the vendor and are usually unique between processes and technologies. These rules allow the designer to fully utilize the capabilities of the process. The drawbacks of vendor specific rules are that it might not be possible to port the designs from one process to another easily. They usually use more layers than the SCMOS rules which will be discussed in the next section. Also as there are more layers, there will be more design rules and hence a higher learning curve in using the process. This could imply that the designs become more complex and the development time is longer [4]. b) Scalable rules Scalable CMOS (SCMOS) is a set of logic layers and design rules that are almost process independent. The designer works with abstract layers and a metric unit ("lambda"). This makes the design process and the learning curve involved in the process simpler. The finished design can then be designed to a foundry which will map the design on to the specific process required and do the fabrication. A design made using SCMOS rules can often be submitted to a variety of fabrication processes and feature sizes. The full 10

19 potential of a process is not usually tapped using these rules because the rules are somewhat over-constrained to make the design flexible and portable between processes and technologies [4]. 2.5 Cell library design techniques. The design is usually done with specific objectives depending on the application for which it is designed. This requires trade-offs to be made by the designer between speed of operation, area of the design and hence cost involved, power dissipated etc. Mainly the optimizations made in design can be classified into three, i.e. to achieve minimal power dissipation, maximum operating speed, or minimal silicon area. These three techniques are detailed below. [5] Low Power Optimization. Capacitance is the major contributing factor in power dissipation. So a library optimized for low power tries to reduce the capacitance as much as possible. This is done by using minimum size devices as much as possible. However the design should meet the noise margin criteria. Any noise from the power supply should not affect the logic levels. The logic thresholds are checked for all devices against temperature, power supply and process variations. Adjustments are made in the transistor sizes if the noise margin requirements are not met and this is iteratively done until the noise margin requirements are met. The output rise and fall times are limited by limiting the maximum capacitance that a gate can drive [5]. 11

20 2.5.2 High Speed Optimization. High speed optimization aims to achieve minimal gate delays without compromising area. Devices can be sized up to increase the speed as more drive current is provided to charge and discharge the transistors. Usually high speed optimization is done by calculating the cell height for minimum sized devices. By minimum sized devices we mean the NMOS devices at minimum allowable size and the PMOS devices at 1.5 to 2 times the minimum size. This is done to ensure similar rise and fall characteristics as the PMOS device is weaker than the NMOS due to smaller mobility for holes. Then this cell height is made to increase nominally to 25% over this minimum and the delay characteristics are noted. Further increase in the height is only done if the increase in speed exceeds the square of the height increase. Iterative SPICE simulations are done to fit the devices accordingly in this increased height in order to obtain minimum gate delays. Finally, a static noise margin check is done to ensure that the noise margin requirements are met [5] Minimal Area Optimization. Minimal area optimization is designed so as to get the fastest possible cells in the minimum area. The minimum standard cell height is fixed and the cells are sized to fill this height. This is subject to further checks to ensure that the noise margins and the gate output rise and fall times are satisfied. If not, iterative SPICE simulations are done to determine the increased sizes of the NMOS and PMOS devices. 12

21 The library that was designed was optimized mainly for area. So most circuits were designed with the NMOS and PMOS set at the minimum widths that maintain correct functionality. The analog cells had specific design requirements, so minimum area was not the main design objective in those cases. They will be discussed later. 2.6 Design Flow. The design flow used was a Bottom-up design flow process. The following flow diagram gives an overview of the involved steps [6] 13

22 Design Specifications Schematic Capture Symbol Creation Pre-Layout Simulation Layout Design Rule Check Extraction Layout Verses Schematic Check Post-Layout Simulation Characterization Documentation Fig 2.1. Bottom-up Design Flow. 14

23 2.6.1 Design Specifications. The specifications typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. The design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. The design specifications given can necessarily determine the optimizations described in section 2.4 that are to be made with the cell sizes Schematic Capture. Generation of a complete circuit schematic is done using a schematic editor. This has the necessary devices, the input and output pins and power rail connections. Sometimes the schematics include further specific details like transistor sizing etc. The schematic is used to generate a netlist that will be used in the further design stages Symbol Creation. If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. 15

24 Pre-Layout Simulation. The netlist obtained from the schematic tool is simulated. The detailed transistor-level simulation will be the first in-depth validation of its operation. The initial simulation phase serves to detect some of the design errors that may have been created during the schematic entry step and to make modifications in the circuit to obtain the desired results. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic during this simulation Layout. Detailed geometries and the relative positioning of each mask layer to be used in actual fabrication is done using a Layout Editor. This can be done either by hand or with the aid of automatic placement tools. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area that is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and timeconsuming design effort Design Rule Check. The mask that has been laid out must confirm to the set of design rules as required by the technology being used, to ensure that the fabricated circuit works to requirements. This is done using a design rule check, which is commonly built into the layout editor. But it can 16

25 be a separate tool also. Any errors in the design rules will show up when the designed mask is checked and is to be corrected Extraction. Circuit extraction is performed after the mask layout design is completed, in order to create a detailed netlist for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Hence this will be more detailed than the one created from the schematic Layout Verses Schematic Check. The design called "Layout-versus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. The LVS is essentially a comparison of the nodes in the schematic and the layout. It just verifies that the nodes match and are connected identically. It does not verify the performance of the circuit Post-Layout Simulation. Once the netlists from the schematic and the layout are verified to be identical, simulation is done on the extracted netlist using simulation tools. This simulation takes into account factors like parasitics, which were not present in the schematic netlist. 17

26 Even a circuit simulated properly with the schematic netlist and verified with LVS, can fail at this stage to meet the requirements due to the parasitics. In that case, the design would have to backtrack to an earlier stage to modify necessary parameters to get the required functionality. This might require just a re-layout to modify the parasitics, or it can be as complicated as re-designing the circuit with a different topology to obtain the requirements. After successful simulation, the characterization and documentation of the designed cells can be done Characterization [7] The cells are verified for their performance characteristics like rise, fall, setup, hold, minimum cycle time, enable and disable times etc. Process specific characteristics like variations due to temperature etc are also considered. The performance of the designs for best and worst case load scenarios are also usually performed. Some libraries even include the characteristics for average load Documentation [7] A developed library is usually documented extensively. All the necessary information required for a person to use these cells effectively is included. Documentation usually summarizes the functionality and timing characteristics. A truth table showing all the possible outcomes is usually included. Some of the other parameters included would be 18

27 the operating temperature range, fan-in and fan-out of the cell, variations in timing due to temperature and voltage, path delays etc. 2.7 Special features of standard libraries. Cell height and power rails: One of the features of standard cell libraries is that the cells have the same height. This makes it convenient to join two cells of different logical capabilities together during a complex design from end to end. This further facilitates ease of routing the signals and the power rails through the design. We have fixed the cell height to be 54 λ. This means that the feature length is 6.48µm. A good rule of the thumb is to make the power rails 10% of the total cell height [8]. This generally provides enough width for the rails to supply the necessary current required by the circuitry. So the power rails were set at 6 λ each. Signal Routing Layers: The process, as explained in a previous section, supports 5 metal layers. During a standard library design, all these layers are rarely used. Some layers are left unused to give the user of the library the added flexibility in routing. The user does not have to worry about unnecessary contacts being made by the routing layers with the same metal in the library beneath. So only two metal layers viz Metal1 and Metal2 are being used throughout the library design. Metal1 is used for horizontal routing and for the power 19

28 rails while Metal2 is used for vertical routing. Contacts between these layers or the additional metal layers can be conveniently made with the use of vias. Well Sizes: Another feature of the designed library is that the cell height is divided evenly for N and P transistors i.e. n-well boundary ends at half the cell height. The transistors are further sized such that the performance of the N and P sections is comparable. Details regarding the sizing will be included in further design sections. The following figure graphically denotes the above. 6λ Vertical routing Metal2 Vdd p-well 54λ Horizontal Metal1 n-well 6λ Gnd Fig 2.2 Rail Sizes and routing layers 2.8 Analog Standard cells. Analog standard cell design methods are more complicated than those methods that are commonly applied in digital circuits because analog cell behavior is sensitive to the electrical environment and the electrical environment into which the analog cells are placed is usually not well defined. So, analog design usually starts with the specific 20

29 requirements for the design being done, to obtain the optimum performance. This means that for many applications common analog topologies must be redesigned to satisfy the new electrical context. The current designs have been made for general purpose use as much as possible by providing as wide a frequency range as allowable for the circuits, making them replicable where possible etc CMOS Analog Standard Cell Design Considerations. [9] Some of the design factors to be considered when developing analog standard cells for a library are listed. 1. Design complexity 2. Dynamic range of analog signals 3. Minimum detectable signal levels 4. Digital resolution of converted analog signals 5. Frequency and temperature range of operation 6. Power supply range and Noise effects due to variations in power supply. 7. Area constraints and power dissipation. 8. Layout considerations like shielding of sensitive nodes, parasitic coupling, electrical and thermal matching, power and signal routing etc. 9. Scalability of the design 10. IC process parameter variation influence on analog performance 21

30 2.9 Tools involved in the Design Process. A good variety of tools are available in the open domain for different parts of the VLSI CAD design process. A list of some such tools is provided in Appendix B. The tools we used in our library design process are outlined below. The development was done on a Debian Linux platform. The layout and simulation tools used where the popular MAGIC and Spice3 tools developed at the Univeristy of California, Berkeley. These tools are forerunners to other industry standard tools and quite sufficient in its capabilities as a design tool. The schematic editor used was Gschem and is a tool provided through the geda project. Comprehensive information and literature regarding this tool can be obtained from LVS (Layout versus Schematic) vertifications was done with Netgen. This is a suite of tools in which netcomp is the LVS tool. Further Information can be obtained from Spice Models used. Spice3 was the simulation tool used. The spice models are obtained from MOSIS runs on specific processes. Details are available at MOSIS has migrated to H- Spice which is a version of spice that is distributed by Cadence for its recent runs. This is not a free tool. So, for the latest spice files to be compatible with SPICE3, modifications 22

31 in the file had to be made. The spice model file used was T43B SPICE BSIM3 Version. The original H-spice model and the modified model made to run with Spice3 can be found in Appendix C. 23

32 CHAPTER III Custom Design Flow Description. 24

33 3.1 Introduction. In this chapter the custom design flow will be illustrated. Each step will be explained in detail. This will help to understand the various steps and the tools functions on these parts of the design. The cells that are designed are optimized for minimum area. Let us consider a 2 input NOR gate for this purpose. It is a basic 4-transistor cell and has a fan in of 2 and one output signal. The standard CMOS implementation of a 2 input NOR Gate is as shown in Fig 3.1. Fig Input NOR Gate Circuit Diagram. 25

34 3.2 Schematic. The first step in developing this would be to generate the schematic. The tool we have been using through this thesis is called Gschem as outlined in chapter GSchem : An Overview. GSchem is a vector-drawing program. Some of the features of this tool are given [10] The awareness of the electrical properties of components, nets, and pins. Hierarchical design (having components represent some abstracted functionality). The ability to associate attributes with nets and components. Generate netlists from the schematic. It also comes with basic drawing functionality to connect nets and bus lines and an inbuilt library which contains a lot of the primitive components like transistors and gates used in design, along with components like power supplies etc. It gives the user the flexibility to assign specific attributes to the nets and devices being used and to label them suitably to make the schematic more readable. An inbuilt function allows the netlist to be generated for the schematic. This helps in verification as will be explained in subsequent sections. 26

35 3.2.2 Schematic of 2 Input NOR Gate. The schematic of the 2 input NOR generated with GSchem is given in in Fig 3.2. Fig Input NOR Gate Schematic Diagram Schematic Verification. The next step is to verify the logical functionality of the schematic. For this a netlist is to be generated from this schematic. A netlist is a listing of devices, nodes and connections between the devices that represents the circuit being designed. Depending on the netlist and the use it is intended for, it can have additional parameters like parasitic values of capacitance, resistance etc that are present between nodes and connections. At the schematic level, we are concerned only with functionality of the circuit from a logic standpoint as we do not have information regarding parasitics involved that will affect the performance and other delays for the circuit. 27

36 The netlist is generated with a tool called gnetlist which is a part of the same geda suite. GSchem supports a variety of netlist formats like Allegro netlist format, BAE netlist format, SPICE netlist format, VHDL-AMS netlist format, Verilog codes, VHDL codes, etc. The generated netlist for the NOR schematic is given below. It can be seen that the netlist recognizes 4 devices in the schematic. * Spice netlister for gnetlist * Spice backend written by Bas Gieltjes vdd 1 0 m1003 output input2 0 0 m1002 output input1 0 0 m input2 output 1 m input1 2 1.END This is simulated in Spice3 to verify the functionality. Spice and its industry variants are among the most popular circuit simulation tools available. It has its roots in UC, Berkeley. The waveforms obtained from Spice3 are given in in Fig 3.3. The functionality for the 2 input NOR can be verified from the waveforms. The Output is 1 if and only if both the input values are 0. Hence it functions as a NOR gate. 28

37 Fig 3.3 Spice Simulation of the netlist from the Schematic. 29

38 3.3 Physical Layout. The next step is the physical layout of the file using any suitable polygon editor. We used MAGIC for the purpose which is one of the more popular layout tools available from University of California, Berkeley. The layout of the file is shown in in Fig 3.4. Fig 3.4 Physical Layout of the 2-Input NOR Gate. 30

39 3.3.1 Layout Guidelines. It can be inferred from the layout that many of the guidelines for a standard library design have been adhered to. The height of the cell and the power rail sizes is as mentioned before. Another feature to note is that metal1 is being used for horizontal routing and metal2 for vertical routing. This has been adhered to throughout the library. It can be seen that substrate connections are given in abundance. This helps collect any injected minority carriers that can show up in the logic as noise or even cause other destructive effects like latch-up. It can also be seen that the cells are extended to the sides with just the wells. There are no active or poly layers or metal contacts in this section. This is to prevent design rules from being violated by an adjacent cell that s placed next to this cell. If the extra spacing is not there, two DRC clean cells, on being placed adjacently might cause DRC violations. This would degrade efficiency a lot, especially in a CAD automatic placement environment. After the layout process, the layout has to be checked against the process rules to make sure that there are no design rule violations. MAGIC has an inbuilt DRC checker, which checks for violations during cell layout. 3.4 Extraction. The resulting layout is then extracted into a SPICE netlist. Now that the placement is done, there is enough information to obtain the parasitics also. This netlist therefore has the capacitance values between the nodes in the layout. The extracted netlist is as shown. 31

40 The commands required to instantiate the spice waveforms for the transient and the dc analysis is also included. *SPICE3 file created from nor2.ext - technology: scmos.include mos_new_1.sp m1000 a_18_27# input1 VDD VDD pmos w=1.44u l=0.24u + ad=0.6912p pd=3.84u as=0.864p ps=4.08u m1001 Out input2 a_18_27# VDD pmos w=1.44u l=0.24u + ad=0.864p pd=4.08u as=0p ps=0u m1002 Out input1 GND GND nmos w=0.36u l=0.24u + ad=0.3168p pd=3.84u as=0.5472p ps=5.76u m1003 GND input2 Out GND nmos w=0.36u l=0.24u + ad=0p pd=0u as=0p ps=0u C0 input1 Out 0.0fF C1 GND input1 0.2fF C2 VDD input2 0.2fF C3 input2 Out 0.2fF C4 GND input2 0.2fF C5 a_18_27# Out 0.0fF C6 input1 input2 0.1fF C7 VDD Out 0.2fF C8 GND Out 0.1fF C9 VDD input1 0.2fF C10 Out GND 0.1fF C11 input2 GND 0.0fF C12 input1 GND 0.0fF C13 GND GND 0.3fF C14 VDD GND 1.1fF C15 Out GND 5ff VGND GND 0 0 VDD Vdd *** for DC analysis *Vin1 input1 0 0 *Vin2 input2 0 0 *.dc Vin ** for Transient analysis VA input1 0 PULSE ( e e e-9 10e-9 40e-9) VB input2 0 PULSE ( e e e-9 15e-9 50e-9).tran 10e-9 120e-9 32

41 3.5 Layout Versus Schematic. Next step is to make sure that the layout corresponds to the schematic that was being designed. This is done using the LVS (Layout versus Schematic) tool Netgen : An Overview. Netgen is a tool for comparing netlists. The one we used for LVS is a standalone tool which is a part of Netgen, called netcomp. The tool is helpful in conversion between netlists also. Very small circuits can bypass this step by manually verifying the circuit operation. Very large digital circuits are usually generated by tools from high-level descriptions and the compilers ensure that the layout generated is correct. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation. LVS also makes finding and correcting an error easier than does simulation. [11] The netgen output is given below after the comparisons between the netlist obtained from the schematic and the layout is done. This shows that the circuits are identical as far as connections are concerned. 33

42 Comparing cells: nor2.spice (circuit 1) and nor2_sch.spice (circuit2). Contents of circuit 1: Cell: 'nor2.spice' Cell nor2.spice contains 4 instances. Class: n instances: 2 Class: p instances: 2 Cell contains 6 nodes. Contents of circuit 2: Cell: 'nor2_sch.spice' Cell nor2_sch.spice contains 4 instances. Class: n instances: 2 Class: p instances: 2 Cell contains 6 nodes. Circuit 1 contains 4 elements, Circuit 2 contains 4 elements. Circuit 1 contains 6 nodes, Circuit 2 contains 6 nodes. Iteration: 0: Element classes = 2 (+2); Node classes = 3 (+3) Iteration: 1: Element classes = 3 (+1); Node classes = 6 (+3) Iteration: 2: Element classes = 4 (+1); Node classes = 6 (+0) Iteration: 3: Element classes = 4 (+0); Node classes = 6 (+0) Iteration: 4: Element classes = 4 (+0); Node classes = 6 (+0) Circuits match correctly. Cells are identical. 3.6 Post-Layout Simulation. Now the netlist from the layout can be simulated in spice to get its performance parameters with the parasitics involved. The waveforms from simulation are shown. On comparison, the difference in simulation results can be seen when considering the effect of parasitics. The transition of the output is instantaneous in the netlist obtained from the schematic, as capacitance is not considered and hence there is not delay. But the netlist from the layout has these parasitics and hence has a delay involved due to the capacitance charging or discharging to the required output level. 34

43 Fig 3.5 Transfer characteristics (Input vs Output) of the 2-Input NOR Gate. The in Fig 3.5 shows the DC characteristics of the NOR gate. Input2 is given as 0 and a sweep voltage is applied at Input1 to determine the switching characteristics. It can be inferred that the Output switches at Vdd/2, which is the value for which the circuit was designed. 35

44 Fig 3.6 Post Layout Simulation Results Fig 3.6 shows the waveforms from the transient analysis. NOR functionality can be observed, where the output is 1 if and only if both the inputs are 0. This is the design flow used for all the cells designed as a part of this thesis. 36

45 CHAPTER IV Design and Simulation of cells. 37

46 4.1 Chapter Overview. The custom design flow for a library has been adequately described in the previous chapter. In this chapter, some of the more complex cells designed as a part of this library will be described. Their design concepts and simulation results will also be discussed in this section. 4.2 Tri-state buffer. Tri-state buffer is a circuit with three possible output states. 0, 1 and Z. Z is a high impedance state. These circuits are used extensively in buses. A number of devices connect to a bus at a time. Only one of these devices can drive the bus at a time so that proper data transfer occurs. This is done by keeping the other devices in high impedance states with the help of tri-state buffers Circuit Diagram. Fig. 4.1 Tri-State Buffer Circuit Diagram. 38

47 The circuit diagram of the tri-state buffer is given in Fig. 4.1.The circuit is activated when the Enable is high. When Enable is high, the circuit is effectively an inverter with the inverse of the input signal coming as the output. When the Enable signal is low, the NAND gate has a 1 as the output and the NOR gate has 0 as the output, irrespective of the value of the input signal. This turns off both the nmos and the pmos transistors, effectively leaving the Out node in a high impedance state Simulation results. The spice waveforms for the designed circuit given in Fig. 4.2 verify this functionality. As can be seen from the waveforms, the output is in the high impedance state when enable is low. The value is susceptible to surrounding signals variations, leakage etc in this state as the node is not being driven at this point by any device. This explains the variations in the signal level during the low state of the enable signal. Another way to implement this would be to have the four transistors in series, one pmos and nmos being driven by the input signal and another pmos and nmos being driven by the Enable and Enable_bar signals. This is relatively easier to implement. But this is not preferred as the performance of this circuit is less than the one presented because the series transistors in the pull up and pull down networks increase the series resistance and thereby impede the performance by reducing the drive capability of the buffer [12]. 39

48 Fig. 4.2 Tri-State Buffer Simulation Waveforms. 40

49 4.3 Analog Comparator. A comparator gives a 1 output if the input value is higher than the reference voltage and a 0 in the reverse case Original Comparator Design. The designed comparator is based on the circuit described by D.Y.Kim et. all [13] Fig. 4.3 Analog Comparator Circuit Diagram. In this circuit, the transistors M 5, M 6, M 7 and M 8 are biased in linear range. The voltage at the nodes 1 and 2 are almost the power supply voltages. A positive input voltage applied at V in, and a negative value at V ref causes M 2 and M 3 to saturate. Therefore node 3 is made negative by the saturated transistor M 2. This effectively causes the drain currents of 41

50 M 5 and M 7 to increase at node 1. The switching current flowing to the output increases to a value much larger than the quiescent bias current. This additional current assists faster switching and hence the comparator exhibits high speed characteristics. The opposite happens for the case when V ref is positive and V in negative. The circuit in Fig 4.3 was initially intended for comparison only at a digital level. The circuit functions very well as a comparator in the digital sense providing very fast transitions at the output. For V in = 1 and V ref = 0 (V in > V ref ) the output switches rapidly to 1. And for V in = 0 and V ref = 1, the output switches to Drawback of the design. In the analog domain, this circuit has a major drawback. When operating in the linear region and the input voltage and the reference voltage are comparable in magnitude, the output takes a very long time to reach a valid state as can be inferred from the figure. 42

51 Fig. 4.4 Simulation waveforms when V in is close to V ref. The Fig 4.4 illustrates the comparator being simulated for reference voltages of V ref = 1 V and V ref = 1.5 V respectively. In the first case, it can be seen that there is a significant delay before the final output level is reached. In the second case the difference between V ref and V in is lesser. The output doesn t even reach the final output value in the 50ns clock cycle. 43

52 This can be explained as follows. When both the signals are comparable, the devices in each path comprised of M 1 -M 2 transistors and M 3 -M 4 have comparable operating points. This causes the currents through these paths to be approximately equal and about half the total available current to be sourced or sunk. This is the worst-case scenario. The speed of the output is dependant on the amount of current available to each path and the transition is faster when the difference is as large as possible. When the difference is slow, the capacitance is charged or discharged by this reduced current Improved Design. This circuit was modified to obtain better performance by adding a pmos and nmos transistor at the output. The circuit diagram for the improved design is given in Fig 4.5. Fig. 4.5 Modified circuit diagram of the comparator. 44

53 When the voltage builds up and goes above the threshold voltage of these transistors, they are turned on and help in pulling up or pulling down the output to the appropriate rail voltages thereby providing a fast compared output. This is illustrated in the figures provided, Fig 4.6. Fig. 4.6 Simulated waveforms of the modified comparator when V in is close to V ref. 45

54 In the designed circuit, it can be seen that fast transitions are provided because of the alternation in the circuit. In the above simulation, V in was kept at 1.5 and V ref pulsed. As can be seen, fast outputs are obtained with V out = 1 for V ref < 1.5V and V out = 0 for V ref > 1.5V One minor disadvantage of this design is that it becomes difficult to match the circuit at the layout level, as it is not symmetrical anymore. This can become important for analog designs in which signal and circuit matching are critical. 4.4 Operational Amplifier. The operational amplifier is one of the most versatile and important circuit components in the analog and mixed signal circuit design. It is also one of the more complex cells to design. Operational amplifiers are amplifiers that have sufficiently high forward gain so that when negative feedback is applied, the closed-loop transfer function is practically independent of the gain of the op-amp. The primary requirement of an op-amp is to have an open-loop gain that is sufficiently large to implement the negative feedback concept A 2 stage buffered operational amplifier. Typically most op-amps have more than one stage to have high open loop gain. The op-amp discussed here is a 2 stage buffered op-amp. The circuit schematic is given in Fig 4.7 [14]. 46

55 Fig. 4.7 Operational Amplifier circuit diagram. The first stage consists of a differential amplifier converting the differential input voltage (V + and V - ) to differential currents (I + and I - ). These differential currents are applied to a current-mirror load, which recovers the differential voltage. In other words the gain stage is nothing but a differential amplifier stage followed by a common source current-sink inverter. This type of configuration is the most common configuration for an op-amp and is also called a classical two stage op-amp. 47

56 Operational amplifier parameters. There are a variety of parameters to be considered when designing an op-amp. [15] Some of them are listed below. 1. Gain 2. Gain bandwidth 3. Settling time 4. Slew rate 5. Input common mode range, ICMR 6. Common mode rejection ratio, CMRR 7. Power Supply Rejection Range, PSRR 8. Output-voltage swing 9. Output resistance 10. Offset 11. Noise 12. Layout Area Feedback in an operational amplifier. Op-amps are generally used in a negative feedback configuration. In this way, the relatively high, inaccurate forward gain can be used with feedback to achieve a very accurate transfer function that is a function of the feedback elements only. 48

57 F(s) V in (s) A(s) V out (s) Fig. 4.8 Opamp transfer function with negative feedback. A(s) is the amplifier gain and will normally be the open-loop, differential voltage gain and F(s) is the transfer function for external feedback from the output of the op-amp back to the input. The loop gain of this is defined as Loop gain = -A(s).F(s) V out (s)/ V in (s) = A(s) / (1+A(s).F(s)) With negative feedback, with a very high open loop gain, the forward transfer function V out (s)/ V in (s) can be accurately controlled by the feedback. This is because, as the value of A(s) increases, the ratio becomes more and more dependent on only F(s) and F(s) is usually comprised of passive elements, so is relatively stable to variations. This is the principle of the operational amplifier Compensation. It is important that the signal fed back to the input is of such an amplitude and phase that it does not continue to regenerate itself around the loop. If this occurs the result will be either 49

58 (i) the clamping of the output of the amplifier at one of the supply potentials (regenerations of dc) or (ii) oscillation (regeneration of some frequency other than dc) The conditions for stability are obtained by equating the denominator of the closed loop equation to 0.It can be inferred that the denominator reaches 0 when the loop gain = 1 and the phase is 180. Phase margin is defined as the phase of the signal when the loop gain reaches unity, i.e. 0 db. For a stable design, we try to target a phase margin of at least 45, with 60 preferable in most situations. This is done by passive compensation means. So it can be inferred that compensation is vital for the stability of an op-amp in a closed loop configuration Design of the 2 stage operational amplifier. The design of the op-amp was a very iterative procedure requiring many re-designs to satisfy all the circuit requirements. The design procedure is narrated below. We start with the following specifications Gain Bandwidth, GB = 5 Mhz DC gain, A v = 1000 Supply voltage = +/- 2.5V Load Capacitance, C L = 10 pf Slew Rate, SR > 8 V/µs ICMR = -1.7V to 1.7V Output swing = -1.5V to 1.5V Power Dissipation < 2mW 50