Adder Design and Analysis

Transcription

1 Adder Design and Analysis University of Washington EE 477 Zach Pritchett and Cody Hogan Winter 2012 Total Area 8.69 µm 2 Worst Case Delay ns FOM x 10 -

2 Table of Contents 1 Introduction Design Design Approach... 2 Critical Path... 8 Final Layout Simulation results Adder Functionality Worst Case Delay Conclusion References: TABLE OF FIGURES Figure 1 Mirror cell schematic... 2 Figure 2 Adder performances by topology... 3 Figure 3 Bit groupings for n carry-select adder... 3 Figure 4 Multiplexer... 4 Figure 5 2 bit group... 4 Figure 6 3 bit group... 5 Figure 7 4 bit group... 5 Figure 8 5 bit group... 6 Figure 9 6 bit group... 6 Figure 10 Final circuit schematic... 7 Figure 11 Circuit test bench... 7 Figure 12 Stick layout for mirror cell... 8 Figure 13 Layout of 1 bit full adder... 9 Figure 14 LVS completion Figure 15 DRC completion Figure Figure P a g e

3 1 INTRODUCTION This project enveloped the design and analysis of a 20 bit adder. Specifically, a carry select adder was implemented using the appropriate bit groups as discussed below in the design approach section. Once the circuit schematic was realized in Cadence, the corresponding netlist was used to simulate the circuit to verify functionality. This included creating a vector file to iterate through 10 unique input pairs and then confirming the appropriate output. The one bit full adder cell used to build the entire circuit was laid out in Cadence and then compared to the corresponding schematic using LVS verification. To obtain a concrete understanding of the performance of the circuit, energy calculations were embedded in the netlist simulation and then analyzed. 2 DESIGN 2.1 Design Approach There were two main design choices to consider when implementing the 20 bit adder. First, the decision of using a Mirror adder topology was made due to the benefits available in its carrygeneration circuitry. Specifically, there is a maximum of two transistors in series found in the carry-generation path. This is quite beneficial as the carry-generation path in the initial group of bits constitutes part of the overall adder s critical path. Figure 1 below shows the final circuit schematic for the one bit Mirror cell. 2 P a g e Figure 1 Mirror cell schematic

4 t_p (unit delays) The second design choice involved deciding what topology to use for the overall circuit. Some of the choices considered included a ripple-carry adder, a carry-bypass adder and a carry-select adder. The decision to use a carry-select adder was made based on the fact that it ideally provides a much smaller worst-case propagation delay than the other topologies. The relationship between the various adders can be seen below in figure General Adder Performances Ripple Carry-Bypass Carry-Select (Linear) Carry-Select ( n ) # of Bits Figure 2 Adder performances by topology The 20 bit adder allowed for a simple grouping of bits as shown in the high level block diagram below. Figure 3 Bit groupings for n carry-select adder Using the above design, the critical path of the circuit is much shorter than what would be found in a ripple-carry or carry-bypass adder. The following sequence of schematics depicts the various bit groups needed to implement the full adder. Also shown are the schematics of the multiplexer, final circuit and circuit test bench. 3 P a g e

5 Figure 4 Multiplexer Figure 5 2 bit group 4 P a g e

6 Figure 6 3 bit group Figure 7 4 bit group 5 P a g e

7 Figure 8 5 bit group Figure 9 6 bit group 6 P a g e

8 Figure 10 Final circuit schematic Figure 11 Circuit test bench 7 P a g e

9 2.2 Cody 2.3 Critical Path Final Layout Another reason the mirror cell topology was chosen was due to the simplicity of its layout. Because of its symmetry, the PMOS pull up network was designed and then mirrored across the horizontal axis to facilitate the creation of the NMOS pull down network. At this point it was merely a matter of changing the diffusion types and resizing the active areas to ensure the proper cell ratios. Figure 12 below provides the stick layout that was used to help create what would become the final layout in Cadence. The figure also gives the individual transistors as taken from the schematic to ensure the appropriate interfaces were translated into layout. vdd! A(M1) B(M0) Ci(M3) A(M4) B(M2) A(M10) B(M11) Ci(M12)~Co(M13) Ci(M20) B(M19) A(M18) ~Co(M27) ~S(M24) ~S ~Cout Cout S A(M6) B(M7) Ci(M5) A(M8) B(M9) A(M16) B(M15) Ci(M17)~C0(M14) Ci(M21) A(M22) B(M23) ~Co(M26) ~S(M25) gnd! Figure 12 Stick layout for mirror cell After verifying the correct design of the above layout, in was produced in Cadence. The result of this is shown below in figure P a g e

10 Figure 13 Layout of 1 bit full adder Once the layout was completed, it was checked for proper design against the schematic. The results of the DRC and LVS verifications are provided in the following figures. 9 P a g e

11 Figure 14 LVS completion Figure 15 DRC completion 10 P a g e

12 3 SIMULATION RESULTS 3.1 Adder Functionality Cody - Proof adder works time decimal time Hex Equivilant input ns a b out ns a b out E E AF C E ED 03E D DE EF EFD5D A2B22 004EA A300C C DD D4 966F8 BD0CC B9 Figure P a g e

13 3.2 Worst Case Delay CODY Delay results Figure 17 CODY 4 CONCLUSION 5 REFERENCES: 12 P a g e