Analysis and Comparison on Full Adder Block in Submicron Technology By: Massimo Alioto and Gaetano Palumbo. Krystina Tabangcura 7/25/11

Transcription

1 Analysis and Comparison on Full Adder Block in Submicron Technology By: Massimo Alioto and Gaetano Palumbo Krystina Tabangcura 7/25/11

2 Outline Single-bit Full Adder Different Topologies Simulation Setup Test 1: Minimum Power Dissipation Test 2: Minimum Power-Delay Product Test 3: n-bit Adder Conclusion

3 Single Bit Full Adder Fig 2. Block diagram of 1-bit Full Adder S A B Ci ABCi ABCi ABCi ABCi Co AB ( A B) Ci If If A B, then Co A A! B, then Co Ci B (Propagate Mode) Fig 1. Truth Table for 1-bit Full Adder

4 CMOS Full Adder Fig 3. CMOS Full Adder Topology S ABCi Co( A B Ci) Co AB ( A B) Ci Fig 4. Layout optimized for minimum Power (left) and minimum PDP (right)

5 Mirror Adder Fig 5. Mirror Adder Topology Fig 6. Layout optimized for minimum Power (left) and minimum PDP (right)

6 CPL Full Adder Fig 5. CPL Full Adder Topology Fig 6. Layout optimized for minimum Power (left) and minimum PDP (right)

7 LEAP Adder Fig 7. LEAP Adder Topology Fig 8. Layout optimized for minimum Power (left) and minimum PDP (right)

8 LP Full Adder Fig 9. LP Full Adder Topology Fig 10. Layout optimized for both minimum Power and minimum PDP

9 TG Full Adder Fig 11. TG Full Adder Topology Fig 12. Layout optimized for minimum Power (top) and minimum PDP (bottom)

10 Tgdrivcap Full Adder Fig 13. Tgdrivcap Full Adder Topology Fig 14. Layout optimized for minimum Power (top) and minimum PDP (bottom)

11 Dual-Rail Domino Full Adder Fig 15. Dual-Rail Domino Full Adder Topology Fig 16. Layout

12 Topology Summary Table I: Transistor Count and Layout Area Summary

13 Simulation Environment Cadence 0.35um CMOS Technology Power Supply: 1.2V, 1.8V, 2.5V, 3.3V Realistic Inputs S loaded with min-sized inv Cout loaded with carry input of full adder Switching Freq: 50 MHz Table II: Simulation Parameters

14 Properties Analyzed Functional Verification t PROP = delay from Cin to Cout in propagate mode P = averaging power flowing into full adder PDP = t PROP * P

15 Test 1: Minimum Power Minimum-sized transistors Dual-Rail Domino not considered due to high power consumption (being a dynamic circuit)

16 Delay Propagation, t PROP Table III: Values of t PROP for varying VDD Fig 17. (a) t PROP vs. VDD, (b) t PROP normalized to value at VDD = 3V

17 Average Power, P Table IV: Values of P for varying VDD Fig 18. P vs. Vdd

18 Power-Delay Product, PDP Table V: Values of PDP for varying VDD Fig 19. (a) PDP vs. VDD, (b) PDP normalized to value at VDD = 3V

19 Test 2: Minimum PDP Transistors optimized to reduce delay without significantly increasing power consumption

20 Propagation Delay, t PROP (a) Fig 21. t PROP reduction vs. VDD Table VI: Values of t PROP for varying VDD (b) Fig 20. (a) t PROP vs. VDD, (b) t PROP normalized to value at VDD = 3V

21 Average Power, P Fig 22. P vs. VDD Fig 23. P increase vs. VDD Table VII: Values of P for varying VDD

22 Power-Delay Product, PDP Fig 25. PDP reduction vs. VDD Table VIII: Values of PDP for varying VDD Fig 24. (a) PDP vs. VDD, (b) PDP normalized to value at VDD = 3V

23 Test 3: n-bit Full Adder Chains PD, w PD, wo nt PROP, w 0.69 n( n 1) R eq C eq Fig 26. Linear representation of a transmission gate chain

24 Simulation Setup Chain of n 1-bit full adders cascaded together and t prop measured from Cin to Cout Power consumption not evaluated, only delay Treat circuit with/without driving capability differently Sim at varying VDD vs. n

25 Delay vs. n V DD = 1.2V V DD = 1.8V V DD = 2.5V V DD = 3.3V Fig 27. Delay vs. Number of Stages, n for varying VDD

26 tspeed Novel parameter to evaluate full adder speed t t t t t SPEED R, w R, wo 1.6t SPEED, wo SPEED, wo PD tr 2 PROP, w n( n 1) t 1.3n( n 1) n 0.8 t PROP, wo PROP, wo t PROP, w

27 Conclusions Full adder simulated as single circuit and chain Parasitics extracted from layout considered Circuits optimized for min P and min PDP For circuits without driving capability, TG and LP are fastest and have low P For circuits with driving capability, Dual Rail Domino has shortest delay (close to TG and LP), but highest P, only good for high performance circuits CPL power dissipation penalty greater than speed improvements make it a good candidate for High Performance circuits (not low power) LEAP and Tgdrivcap don t offer any great advantage in terms of power/speed, both not good choices for low power or high performance design Advantage of circuits w/o driving capabilities lost when cascading adders, only good for short chains of blocks CMOS and Mirror among the better solutions for circuits with drivcap