Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function.

Transcription

1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor Logic Teaser! What does this do? 4 Identify Function! What function is this?! What is Vout if A=1, B=1?

2 ! What is Vout if A=1, B=1?! What is Vout if A=0, B=1? ! What is Vout if A=0, B=1?! What is Vout if A=0, B=0? if A=1, B=0? Area! What is Vout if A=0, B=0? if A=1, B=0?! Compare PT with CMOS circuit?

3 ! Is this a regenerating/restoring gate? ! What does output look like (DC transfer)? " (B=1, notb=0, sweep A, nota=cmos inv(a)) Pass TR transfer (B=1) CMOS Inverter Transfer Sweep A Reasonable Input to CMOS Inverter? Pass Transistor xor2 with inv restore

4 Compare CMOS Required to use?! Is this a fair comparison?! What should we add to make substitutable with CMOS? Restore Restore! Area? (compare to CMOS) Chain Together Focus on Pass Transistor! Vgs?! Operation mode?! Current flow direction? V dd =1V V thn =-V thp =0.3V

5 At t=0 (after Vin transition 1#0) At t=4τ (after Vin transition 1#0)! What is Vmid? Vout? " Vgs of A? Vgs of B? V dd =1V V thn =-V thp =0.3V! What is mode of operation of A and B? V dd =1V V thn =-V thp =0.3V At t= (after Vin transition 1#0) Voltage of Chain! What is Va? Vmid? Vout? V dd =1V V thn =-V thp =0.3V! What is voltage at output? V dd =1V V thn =-V thp =0.3V How compare DC Analysis chain of 3! Compare

6 DC Analysis chain of 6 Conclude! Can chain any number of pass transistors and only drop a single V th Transient Transient: Zoomed Closeup Gate Cascade? Chain Together! What are voltages?

7 Cascaded Pass Gates Delay A=1, B=0, C DB =C diff =C d? Penn ESE 570 Spring 2017 Khanna Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d?! What s the equivalent RC circuit?! What s the equivalent RC circuit? Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d?! What s the equivalent RC circuit?! What s the equivalent RC circuit? " What is the total delay? " From A to Y 3C d 2C d + 3C d 2C d

8 Delay A=1, B=1, C DB =C diff =C d? Delay A=1, B=1, C DB =C diff =C d?! What s the equivalent RC circuit? Bonus! What does this do? B Transmission Gates A 45 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD

9 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 49 - V Tp 50 CMOS Transmission Gates CMOS Transmission Gates Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 51 - V Tp 52 Transmission Gate, R eq Transmission Gate, R eq k p (- V DD - V Tp ) 2 k p [2(- V DD - V tp ) (V out V DD ) - (V out V DD ) 2 ] k p [2(- V DD - V tp ) - (V out V DD )] k p [2(- V DD - V tp ) - (V out V DD )]

10 Transmission Gate, R eq Transmission Gate Layouts Logic Types Idea! CMOS Gates " Dual pull-down and pull-up networks, only one enabled at a time " Performance of gate is strong function of the fanin of gate " Techniques to improve performance include sizing, input reordering, and buffering (staging)! Ratioed Gates " Have active pull-down (-up) network connected to load device " Reduced gate complexity at expense of static power asymmetric transfer function " Techniques to improve performance include sizing to improve noise margins and reduce static power! Pass Gates " Implement logic gate as switch network for reduced area and load capacitance " Long cascades of switches result in quadratic increase in delay " Also suffer from reduced noise margins (V T drop) " Use level-restoring buffers to improve noise margins! CMOS " Design for worst case input switching case and delay! There are other logic disciplines " Ratioed logic " Can use pass transistors for logic " Transmission gates " Will see in use in dynamic logic! Dynamic logic coming up soon Midterm Exam Midterm Topics List! Midterm 3/14 " During class; starts at exactly 1:30pm, ends at exactly 2:50pm (80 minutes) " Location: LRSM Auditorium " Old exams posted on old course websites " Covers Lec 1-13 " Closed book, no notes or cheat sheets " Calculators allowed and recommended, no smart phones " Review Session by TA TBD " Watch piazza for time and location " Office Hours " cancelled during spring break, use Piazza for questions " Tania: Monday (3/12) 2-4:30pm! Identify CMOS/non- CMOS! Any logic function $# CMOS gate! Noise Margins! Circuit first order switching rise/fall times " equivalent resistance " Load capacitance! Transistor " Regions of operation " Parasitic Capacitance Model! Layout and stick diagrams! Sizing! 1 st order delay " Worst case " Elmore delay! Ratioed logic