Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Previously: Two XOR Gates. Pass Transistor Logic. Cascaded Pass Gates

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Lawrence Webb
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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 2, 2017 Combination Logic: Pass Transistor Logic, and Performance 2 Previously: Two XOR Gates Pass Transistor Logic 4 Cascaded Pass Gates Focus on Pass Transistor! Vgs?! Operation mode?! Current flow direction? 5 6 1

2 At t=0 (after Vin transition 1"0) At t=4τ (after Vin transition 1"0)! What is Vmid? Vout? # Vgs of A? Vgs of B?! What is mode of operation of A and B? 7 8 At t= (after Vin transition 1"0) Voltage of Chain! What is Va? Vmid? Vout?! What is voltage at output? 9 10 How compare DC Analysis chain of 3! Compare

3 DC Analysis chain of 6 Conclude! Can chain any number of pass transistors and only drop a single V th Transient Transient: Zoomed Closeup Gate Cascade? Output! What are voltages?! What is Vout if A=0, B=0? if A=1, B=0? A B Y

4 Area! Compare PT with CMOS circuit? Output! Is this a regenerating/restoring gate? A B Y Output Pass TR transfer (B=1)! What does output look like (DC transfer)? # (B=1, notb=0, sweep A, nota=cmos inv(a)) 21 Sweep A 22 CMOS Inverter Transfer Reasonable Input to CMOS Inverter?

5 Pass Transistor xor2 with inv restore Compare CMOS! Is this a fair comparison? Restore Output Chain Together! Area? (compare to CMOS) Analyze Stage Delay A=1, B=0, C DB =C diff =C d?

6 Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d? Delay A=1, B=0, C DB =C diff =C d? # What is the total delay? # From A to Y 3C d 2C d + 3C d 2C d Delay A=1, B=1, C DB =C diff =C d? Delay A=1, B=1, C DB =C diff =C d?

7 Bonus! What does this do? B A B Y Transmission Gates A 37 Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 41 - V Tp 42 7

8 Note at t = 0 - : V in = 0, V out = 0 at t = 0 + : V in = 0 -> V DD - V Tp 43 - V Tp 44 Transmission Gate, R eq Transmission Gate, R eq k p (- V DD - V Tp ) 2 k p [2(- V DD - V tp ) (V out V DD ) - (V out V DD ) 2 ] k p [2(- V DD - V tp ) - (V out V DD )] k p [2(- V DD - V tp ) - (V out V DD )] Transmission Gate, R eq Transmission Gate Layouts

9 Logic Types! CMOS Gates # Dual pull-down and pull-up networks, only one enabled at a time # Performance of gate is strong function of the fanin of gate # Techniques to improve performance include sizing, input reordering, and buffering (staging)! Ratioed Gates # Have active pull-down (-up) network connected to load device # Reduced gate complexity at expense of static power asymmetric transfer function # Techniques to improve performance include sizing to improve noise margins and reduce static power! Pass Gates # Implement logic gate as switch network for reduced area and load capacitance # Long cascades of switches result in quadratic increase in delay # Also suffer from reduced noise margins (V T drop) # Use level-restoring buffers to improve noise margins Idea! CMOS # Design for worst case input switching case and delay! There are other logic disciplines # Ratioed logic # Can use pass transistors for logic # Transmission gates # Will see in use in dynamic logic! Dynamic logic coming up soon Midterm Exam Midterm Topics List! Midterm 3/14 # In class in Towne 321 # Starts at exactly 1:30pm, ends at exactly 2:50pm (80 minutes) # Covers Lec 1-13 # Closed book, no notes or cheat sheets # Calculators allowed and recommended # Old exams posted online with and without solutions # Review Session by TA on Sunday 3/12 # Watch piazza for time and location # Office Hours # cancelled during spring break, use Piazza for questions # Tania: Monday (3/13) 5-7pm # Ryan: Monday (3/13) 3:30-5pm! Identify CMOS/non- CMOS! Any logic function $" CMOS gate! Noise Margins! Circuit first order switching rise/fall times # Output equivalent resistance # Load capacitance! Transistor # Regions of operation # Parasitic Capacitance Model! Layout and stick diagrams! Sizing! Lumped 1 st order delay # Worst case estimation! Elmore-delay # Worst case estimation

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Teaser. Pass Transistor Logic. Identify Function. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lecture Outline! Pass Transistor Logic! Performance Lec 15: March 1, 2018 Combination Logic: Pass Transistor Logic, and Performance 2 Pass Transistor