s(t) s(t-dt) s(t-2dt) s(t-3dt) s(t-ndt) s(t)

Transcription

1 Programmable Filter: Your Design Project Description Design a programmable filter bank: Your chip receives one or more external input signals (x), and outputs several signal outputs (y). Include programming (e.g. download/upload) memory taps (w). Options: Follow the (sample) project design for a filter-bank: use 16 (or more) input-output filter-bank (i.e., processing array) with (at least) 5-bit storage of the taps It is a vector matrix multiplier. The matrix is a 17x16 array (one input for bias!). A transversal filter-bank: includes simple delay lines (e.g. RC delay-line) to convert 1d signal to several delayed versions. s(t) s(t-dt) s(t-2dt) s(t-3dt) s(t-ndt) s(t) Design Project P1

2 Option: Your Design Project Description Teams may use an RC-delay line design that converts a 1d digital signal to several delayed versions. Teams will add control circuitry that selects either a direct parallel (vector) input or a single input passing thru the RC-delay line as the input to the filter array. X 0 = s(t) X 1 = s(t-dt) X 2 = s(t-2dt) s(t-3dt) Xn= s(t-ndt) s(t) Design Project P2

3 . Notation: 0 0 Filter-Bank: Equations/Formula Signal Input Vector: x= [ x,..., x ] Signal Output Vector: n T y= [ y,..., y ] m T Matrix of "weights, parameters, or taps:" W = [ w ], i= 0,1,... n; j= 0,1,..., m. ij x Multiplier(s) W y y=wx y i j= n = j= 0 wx ij j Design Project P3

4 Non-adaptive Filter-Bank Processor Processor. is to compute a vector-matrix multiplication. y=wx; or y = wx : = y y : = wx i j= n j= n (analog) Multiplier cell ij j ij ij ij j j= 0 j= 0 Local computation of analog multipliers For speech/music signal s(t), one gets: y = wx : = wst ( jdt) i j= n j= n ij j j= 0 j= 0 ij Design Project P4

5 . Cross-bar (array) layout y 1 x 1 x j y i Design Project P5

6 Basic Cell y i Static memory x j c MDAC Floating-gate w ij MUX Dynamic memory You may use one of these 3 Tap Memory options Design Project P6

7 . Architectural Design The chip design is comprised of three stages High Level ( system specifications, block definitions) Component Level (Architectural/topology, simulations) Layout Level (Cadence LVS, DRC,..) Design Project P7

8 User friendly design: think as the end-user. Your chip should operate in (easy) operational modes, e.g.: i. Program read/write (taps) ii. Process analog filter processing Design Project P8

9 Current Mirrors. For the nmos mirror, I D1 = β1 (VGS 1 Vth1 ) 2 / 2 I D 2 = β1 (VGS 2 Vth 2 ) 2 / 2 VGS 1 = VGS 2 ± I D1 β1 + Vth1 = ± ID2 β2 + Vth 2 If transistors are matched, then I D2 W2 L1 β2 = I D1 = I D1 β1 W1 L2 Thus, for a given M1, M2 can be sized to produce any multiples of I D1 Design Project P9

10 . Differential Pairs Iss = ID 1+ ID2 I I = I ( I I ) = 2I I D1 D2 D1 ss D1 D1 ss I tanh( α( V V )) ss d d Design Project P10

11 . Basic Transconductance Amplifier The chip design is comprised of three stages High Level ( system specifications, block definitions) Component Level (Architectural/topology, simulations) Layout Level (Cadence LVS, DRC,..) Design Project P11

12 . Wide Transconductance Amplifier Use the transistor number to identify the I_ds thru the transistor Design Project P12

13 . Wide Transconductance Amplifier I = I I out 7 9 = I I 1 2 = I tanh( α( V V )) (approximately) tanh(.) is the hyperbolic tangent funtion. (Typically, α = 25 mv. ) Use the transistor number to identify the I_ds thru the transistor in the schematic. Current mirrors act as (current) buffers and copiers/reflectors. Dependening on tx sizing, they may scale the input current. Design Project P13

14 EXTRAS: Multiplier. Use the transistor number to identify the I_ds thru the transistor Design Project P14

15 . Multiplier I = I I = ( I ) ( I ) = ( I + I ) ( I + I ) out = ( I I ) + ( I I ) = ( I tanh( V V )) + ( I tanh( V V )) = ( I I ) tanh( V V )) = ( I I ) tanh( V V )) = ( I ) tanh( V V ) tanh( V V )) Use the transistor number to identify the I_ds thru the transistor Set V2=V4=Vdd/2. 0<V1<Vdd, 0<V3<Vdd Design Project P15

16 Current Mirrors. For the nmos mirror, I D1 = β1 (VGS 1 Vth1 ) 2 / 2 I D 2 = β1 (VGS 2 Vth 2 ) 2 / 2 VGS 1 = VGS 2 ± I D1 β1 + Vth1 = ± ID2 β2 + Vth 2 If transistors are matched, then I D2 W2 L1 β2 = I D1 = I D1 β1 W1 L2 Thus, for a given M1, M2 can be sized to produce any multiples of I D1 Design Project P16

17 Multipying Digital-Analog Converter (MDAC) MDAC:. Digital word ddddd k= 4 k= 4 k k Iout = 2 dk I = I 2 dk k= 0 k= 0 I I d 0 By tx sizing design, I dk W k L = I : = 2 k dk I W Lk Design Project P17