Assignment 1 SOLUTIONS

Transcription

1 ELEC5509 Assignment 1 SOLUTIONS September 2013 The nmos technology used in ELEC4609 provides enhancement MOSFETs with VT = 0.7V and depletion MOSFETs with VTd = -3.0V. The gate oxide thickness t ox = 50nm and the substrate doping NA = 4x1015 cm-3. The source and drain regions are formed by a predeposition type diffusion at 1000EC, giving an electrically active surface concentration of around 3x1020cm-3 and a junction depth of about 0.5 ìm. The minimum usable gate LG is approximately 2.5 ìm corresponding to a channel length L of about 2 ìm. a) The enhancement MOSFET uses no VT adjust implant. Compute VT for the case in which no backgate bias VSB is applied. Is this a useful VT value for circuit design? Calculate the backgate bias VSB required to give VT = 0.7 V (your answer should be around 1 V). b) The same VSB is applied to the depletion device. Calculate the V T adjust implant dose required to give VTd = -3V. What element should be implanted?

2 c) For this part and all subsequent parts, use MINIMOS. An example MINIMOS input file for the enhancement transistor is provided on the course website. The source/drain diffusion parameters have been adjusted arbitrarily to approximate the actual doping profile. Run MINIMOS and then Postmini to plot the doping profile for the device. Confirm that the source/drain junction depth is close to 0.5 ìm. Black dashed line shows metallurgical junction (depth a bit more than 0.5 ìm) d) Determine V T for a long channel device (L = 10 ìm). Next find the value of L for which V T drops 100mV below the long channel value. Use OPTION MODEL=THRESH for this part. Input file to determine V for L = 10 ìm: T Carleton nmos DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=10.0E-4 PROFILE NS=3E20 TEMP=1080 TIME=600 NB=4E15 OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7 BIAS UD=0.1 UG=0 UB=-1 OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N END ERR=0.001 BIN=Y Setting UB=-1 gives V T = 816 mv (note this doesn t agree very well with calculation in (b), but ELEC4609 students may recall it is actually very close to the experimental value) Use this value of UB in subsequent simulations Reducing L to 6 ìm drops V T to 706 mv (onset of short channel effects)

3 e) Determine S for L = 10 ìm. Set V DS = 100mV. Easy way: use the Minimos program above to find V T, but run for CU=1E-9 and CU=1E-10 For I D = 10 na VGS= 574 mv For I = 1 na VGS= 477mV D So S is 97 mv/decade (fairly typical of bulk CMOS) f) Determine the value of L for which V DIBL = 200mV. Compute V DIBL between V DS = 0.1V and V DS = 5V. A quick way to do this is to use MODEL=THRESH, but set the value of I D defining threshold to a very low value (e.g. 1 na/ìm). Use the find V T input file above, with CU=1E-9. Run for V D = 0.1V and V D = 5V and take the difference in V. This is V. Start with L = 10 ìm then reduce L; V gets bigger. GS DIBL DIBL L = 10 ìm V DIBL = 12 mv L = 2.5 ìm V DIBL = 115 mv L = 2 ìm V = 240 mv DIBL So the answer is around L = 2 ìm

4 g) For L = 1.5 ìm, plot the subthreshold log(i D) vs V GS characteristic for V DS = 0.1V and V DS = 5V. Is the device showing signs of punchthrough for V DS = 5V? Using POSTMINI make a 2-dimensional plot of the electron concentration in the device for V DS = 5V. Look for the path taken by electrons below the channel. This is typical of punchthrough. Also make a 1-dimensional plot of potential at a depth of 0.1 ìm below the surface, and compare to the same plot for a device with L = 10 ìm. Look for a drain-induced lowering of the energy barrier holding electrons in the source in the short channel device. MINIMOS input file: Carleton nmos DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=1.5E-4 PROFILE NS=3E20 TEMP=1080 TIME=600 NB=4E15 OPTION MODEL=2D PHYSCHK=NO BIAS UD=5 UG=-0.5 UB=-1 STEPS DG=0.1 NG=10 OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N END ERR=0.001 BIN=Y I-V Plot:

5 Electron plot: Energy barrier plot:

6 h) Run a simulation in saturation (V DS = 5V, V GS -= 2V) for a device with L = 2 ìm. Use MODEL=AVAL. Using Postmini make 2-dimensional plots of the electron concentration and electron current. Identify the pinch off point, the point in the depletion region near the drain where the electron concentration drops below the dopant ion concentration. Observe how the electron current breaks away from the surface at the pinch-off point, entering the drain below the surface. MINIMOS input file: Carleton nmos DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=2.0E-4 PROFILE NS=3E20 TEMP=1080 TIME=600 NB=4E15 OPTION MODEL=AVAL PHYSCHK=NO BIAS UD=5 UG=2.0 UB=-1 OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N END ERR=0.001 BIN=Y Electron concentration plot:

7 i) For L = 2 ìm, fix V DS at 5V and find the value of V GS giving peak substrate current. Again use MODEL=AVAL. For this value of V GS, use Postmini to make 2-dimensional plots of the lateral electric field and the generation rate. Where is the generation rate highest? Peak substrate current found at VG = 1.5 V: VG: IB: 1.2 V 4.6e-10 A/ìm e e e e e-10 Lateral Electric Field: Avalanche Generation Rate:

8 j) Write a MINIMOS input file for the depletion transistor. Implant phosphorus at 60 kev to set V. Adjust the dose so that V = -3V for the value of V found in (a). Td Td SB Carleton nmos DEVICE CHANNEL=N GATE=NPOLY TOX=50E-7 W=1.0E-4 L=5.0E-4 PROFILE NS=3E20 TEMP=1080 TIME=600 NB=4E15 IMPLANT ELEM=P DOSE=1.5E12 AKEV=60 TEMP=1080 TIME=600 OPTION MODEL=THRESH PHYSCHK=NO CU=1E-7 BIAS UD=0.1 UG=0 UB=-1 OUTPUT PSI=N ETRAN=N ELAT=N MIN=N DC=N AVAL=N END ERR=0.001 BIN=Y This gives V Td = -2.9 V k) Using MINIMOS, compare short channel effects in the enhancement and depletion transistors for L = 2 ìm. Why does the depletion transistor show stronger short channel effects? Subthreshold I-V for enhancement and depletion transistors:

9 Depletion transistor is a buried channel device, which gives worse short channel effects For VG=-3V (onset of threshold), note how potential well where electrons gather forms below surface; also note electron concentration peak below surface