Texas Instruments BQ29330 Battery Protection AFE from BQ20Z95DBT

Transcription

1 Texas Instruments BQ29330 Battery Protection AFE from BQ20Z95DBT Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR DYPJ Revision 1.0 Published: August 3, 2010

3 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Device Summary 1.5 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Polysilicon 3.7 DMOS Transistors 3.8 Bipolar Transistors 3.9 Capacitors 3.10 Resistors 3.11 Fuses 3.12 Wells and Substrate 4 Critical Dimensions 4.1 Horizontal Dimensions 4.2 Vertical Dimensions 5 References 6 Statement of Measurement Uncertainty and Scope Variation About Chipworks

4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom BQ20Z95DBT Top-View X-Ray Image BQ29330 Die Photograph Die Markings Die Markings BQ29330 Die Delayered to M Die Corner A Die Corner B Die Corner C Die Corner D Bond Pad 3 Process Analysis Die General Structure Die Edge Cross Section Die Seal Cross Section Minimum Pitch Bond Pads Bond Pad Cross Section Bond Pad Edge Cross Section Passivation Layer IMD IMD Pre-Metal Dielectric Field Oxide Minimum Pitch M Minimum Pitch M Minimum Pitch M M1 and M2 Layers TEM Via 2s Via 1s Contacts to Silicon Contact to Polysilicon Contact Bottom Silicide Layer TEM Contact Bottom Corner TEM CMOS Logic NMOS Transistor NMOS Transistor Gate NMOS Transistor S/D Depth and Contacted Gate Pitch SCM PMOS Transistor

5 Overview Minimum Size MOS Transistor TEM nm Thick Gate Oxide nm Thick Gate Oxide Thick Gate Oxide MOS Transistor Gate Edge TEM High Voltage PMOS Transistor High Voltage PMOS Transistor SCM Depletion Mode PMOS Transistor Depletion Mode PMOS Transistor SCM N-Channel DMOS Transistor N-Channel DMOS Transistor SCM NPN Transistor SCM PNP Transistor PNP Transistor SCM MOS Capacitor MOS Capacitor SCM Polysilicon Resistor Plan View Polysilicon Resistor Cross-Sectional View Polysilicon Fuse Blown Polysilicon Fuse P-Type Epi on P + Substrate SCM N + Buried Layer SCM General View with N + Buried Layer SRP N + BL Carrier Concentration Profile SRP Epitaxial Layer Carrier Concentration Profile

6 Overview List of Tables 1 Overview Device Summary Major Findings 2 Device Overview Package and Die Critical Dimensions 3 Process Analysis Dielectric Layers Composition and Thicknesses Metal Layers Composition and Thicknesses Metal Layers Minimum Horizontal Dimensions Minimum Via and Contact Horizontal Dimensions Substrate Well/Layer Depths and Carrier Concentrations 4 Critical Dimensions Metal Layers Minimum Horizontal Dimensions Minimum Via and Contact Horizontal Dimensions Minimum Transistor Horizontal Dimensions Dielectric Layers Composition and Thicknesses Metal Layers Composition and Thicknesses Silicon Layer Thicknesses