BCD Technology. Sense & Power and Automotive Technology R&D. January 2017
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1 BCD Technology Sense & Power and Automotive Technology R&D January 2017
2 Content 2 BCD in ST Technology platform details
3 Content 3 BCD in ST Technology platform details
![December 10, 1984 [2] C. Cini, C. Contiero, C. Diazzi, P. Galbiati, D.](/docs-images/81/83331472/images/4-1.jpg "Rossi, \"A New Bipolar, CMOS, DMOS Mixed Technology for Intelligent Power Applications\", ESSDERC '85 Proceedings, Aachen (Germany), September 1985")
4 What is BCD? 4 A concept invented by ST in the mid-80s [1][2][3] widely used today in the industry [1] Single Chip Carries Three technologies, Electronics Week, December 10, 1984 [2] C. Cini, C. Contiero, C. Diazzi, P. Galbiati, D. Rossi, "A New Bipolar, CMOS, DMOS Mixed Technology for Intelligent Power Applications", ESSDERC '85 Proceedings, Aachen (Germany), September 1985 [3] A. Andreini, C. Contiero, P. Galbiati, "A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS Logic and DMOS Power Parts", IEEE Transactions on Electron Devices, Vol. ED-33 No.12, December 1986
5 Analog + Digital + Power & HV on one chip 5 HV & Power High Voltage or Power section (DMOS) to drive external loads Analog Analog blocks to interface the external world to the digital systems Digital Digital core (CMOS) for signal processing
6 BCD Roadmap Driving Factors
7 BCD Evolution in the More than Moore arena 7 Driven more by Process Customization for Application Requirements than by Reduction of Lithography Node Trend towards Advanced Technology Nodes compatible with availability of Depreciated Advanced Manufacturing Plants Long Lifetime of Products and Process Generations Always present demand for Cost Reduction
8 BCD in ST Overview 8 Solid know-how developed over three decades Processes from 4.0 µm to 0.11 µm developed and produced Unique voltage range offering Large voltage range spanning multiple application fields Advanced process nodes differentiated by application Offers best in class HV devices with large CMOS integration capability 30 Years 5 V to 800 V 0.16 µm 0.11µm Process customization by application Strong synergy between technology, design and application
9 BCD Technology Segmentation 9 SEGMENT TECHNOLOGY PLATFORM APPLICATION FIELDS High Voltage BCD 0.32µm BCD6s Offline 3.3V / 5V CMOS 25V/800V/1200V BCD6s HV Transformer 3.3V CMOS - Galvanic Isolation 4-6KV Lighting Motors Electrical Car SOI BCD SOI-BCD6s 3.3V CMOS - 20V/50V/100V/190V SOI-BCD8s 1.8V CMOS - 70V/100V/140V/200V Full digital amplifier Echography AMOLED Pico-projector 0.16µm BCD8sP µm 1.8V CMOS - 10V/18V/27V/42V/60V Advanced BCD 0.11µm BCD8sAUTO µm 3.3V CMOS - 20V/40V/65V/100V BCD9s µm 1.8V CMOS - 10V/40V/60V BCD9sL µm 3.3V CMOS - 20V/40V/65V/100V HDD Printers Airbag ESP Audio amplifier Power Line modems BCD9sE µm e-pcm 1.8V CMOS - 10V/40V/60V 90nm BCD10-90nm 8V to 65V Power Supply Automotive Power Management for Mobile
10 Content 10 BCD in ST Technology platform details
11 SOI-BCD8s Overview 11 SOI-BCD8s is a 0.16µm Technology Platform dedicated to High Voltage applications on SOI substrates with the following main features: Baseline 3.3V CMOS Medium Voltage Module including 6V / 20V / 40V N-ch and P-ch MOS High Voltage Module including 70V/100V/140V/200V N-ch and P-ch MOS Optional 2 nd gate oxide for 1.8V CMOS Dielectric Isolation on SOI 4 Metal Levels with last AlCu Thick Power metal Available memory: OTP Application examples: 3D MEMS scanning, Pico-projector (MEMS µ-mirror driver) Consumer and Automotive Audio Amplifier Automotive Sensor Interface ICs 3D Ultrasound (echography)
12 SOIBCD8s device portfolio 12 Device Portfolio Low Voltage 1.8V CMOS (3.5mn oxide) 3.3V CMOS (7nm oxide) Diodes 5V Zener p+/nwell, p+/nwell3v3 n+/pwell, n+/pwell3v3 HV Fast Diodes 100V/200V Medium Voltage N-DRIFT on GOX=7nm 6V, 20V, 40V P-DRIFT on GOX=7nm 6V, 40V Capacitors 1.8V/3.3V poly P+ on pwell 1.8V/3.3V poly N+ on cpcimp (pwell) 5V poly-poly HL 100/200V MOM 30V MOM interdigitated High Voltage N-DRIFT on GOX=7nm 70V, 100V, 140V, 200V P-DRIFT on GOX=7nm 70V, 100V, 140V, 200V Resistors Poly resistors, including HIPO resistor (1kOhm and 6kOhm/sq) Diffused resistors Thin film resistor Bipolar 5V NPN 5V NPN w/ CPCIMP 3.3V PNP Trimming OTP Antifuse on 7nm GOX
13 SOI Isolation versus Junction Isolation SOI-BCD Highlights Advantages Parasitic bipolars elimination Reduced isolation distance Below Ground capability EMI robustness Drawbacks High cost of substrate Parasitic capacitance Thermal effect Fully isolated HV MOS section SOI BCD is convenient or even mandatory in case of: Ultrasound Probe ASIC µ-mirror driver High Voltage Amoled Power Supply Noise Immunity Below Ground pins Low Consumption Automotive Sensor ASIC Airbag Car Radio Full digital amplifier
14 3.3V CMOS 14 Nominal operating voltage = 3.3V Maximum operating voltage = 3.6V Absolute maximum rating = 4.6V Nominal Gate-to-Source voltage = 3.3V Maximum Gate-to-Source voltage = 3.6V Transistor density (4 metal levels) =50000gate/mm 2 Device Gate length [µm] Vth (mv) Intercept with Vgs axis at Gm peak Min Typ Max Vth (T.C.) (mv/ o C) Ioff/W sh T=150ºC Idsat/W sh A/ 3.3V NMOS W=10µm 3.3V PMOS W=10µm Device MATCHING ( Vth) = a 0 * (W sh *L sh ) -0.5 ( / ) = b 0 * (W sh *L sh ) V NMOS a 0 = 7.4mV* m b 0 = 2.01%* m 3.3V PMOS a 0 =5.47mV* m b 0 = 1.27%* m
15 1.8V CMOS 15 Nominal operating voltage = 1.8V Maximum operating voltage = 2.0V Absolute maximum rating = 2.5V Nominal Gate-to-Source voltage = 1.8V Maximum Gate-to-Source voltage = 2.0V Transistor density (4 metal levels) =90000gate/mm 2 Device Gate length [µm] Vth (mv) Intercept with Vgs axis at Gm peak Min Typ Max Vth (T.C.) (mv/ o C) Ioff/W sh T=150ºC Idsat/W sh A/ 1.8V NMOS W=10um 1.8V PMOS W=10um Device MATCHING ( Vth) = a 0 * (W sh *L sh ) -0.5 ( / ) = b 0 * (W sh *L sh ) V NMOS a 0 = 4.79mV* m b 0 = 1.1%* m 1.8V PMOS a 0 =3.44mV* m b 0 = 0.86%* m
16 HV MOS and Bipolar electrical parameters 16 Maximum operating voltage [V] N-CH R ON xarea [mω mm 2 ] V GS =3.3V Maximum operating voltage [V] P-CH R ON xarea [mω mm 2 ] V GS =-3.3V Device Gain typical BV CEO [V] typical V Early [V] NPN 5V NPN 5V Cpc-impl PNP 3.3V
17 Resistors electrical parameters Resistor type Rsheet [Ω/sq] Non Linearity factor (W=5μm) Temperature coefficient Mismatc h σ( R/R) [% µm] Nwell %/V TC1=4.15e-3 C TC2=9.97e-6 C -2 Nminus %/V TC1=-0.94e-3 C TC2=12.4e-6 C -2 Unsilic. P+ poly e-6/V TC1=-0.14e-3 C TC2=0.79e-6 C -2 Unsilic. N+ poly e-6/V TC1=-2.46e-3 C TC2=5.73e-6 C -2 Unsilic. N+ poly with predoping e-6/V TC1=0.19e-3 C -1 TC2=0.38e-6 C Hipo e-6/V TC1=-3.14e-3 C TC2=8.30e-6 C -2 Poly-poly shielded e-6/V TC1=-3.32e-3 C TC2=8.70e-6 C -2 Thin Film resistor 576 0e-6/V TC1=-0.019e-3 C TC2=0 e-6 C -2 17
18 Capacitors electrical parameters 18 Capacitor type Intrinsic capacitance [nf/mm 2 ] Capacitance modulation ( C/C) [%] 1.8V poly on silicon -1.8V 29.5 (-1.8V, 0) 1.8V poly on silicon with Capacitor impl. 1.8V 10.1 (0, 1.8V) 49.7 (-1.8V, 1.8V) 3.3V poly on silicon -3.3V 23.0 (-3.3V, 0) 3.3V poly on silicon with Capacitor impl 3.3V (0, 3.3V) 16.9 (-3.3V, 3.3V) 5V poly-poly 0V -1.2 (-5V, 5V) Interdigitated metal 646 pf/mm 2 100V metal 123 pf/mm 2 200V metal 22.4 pf/mm 2
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