A 100V, 3 Phase Gate Driver with integrated digital PWM Generation and Current Sampling

Transcription

1 A 100V, 3 Phase Gate Driver with integrated digital PWM Generation and Current Sampling Daryl Prince, Hong Xiao Agile Systems Inc. 575 Kumpf Drive, Waterloo ON Canada N2V 1K3 DPrince@agile-systems.com web page: Dr. Wai Tung Ng University of Toronto Electrical & Computer Engineering, Toronto ON Canada M5S 3G4 Abstract: The use of a merged CMOS LDMOS fabrication process allows the integration of some common components for a 3 phase motor drive onto an single IC chip. This fabrication process provides the capability to implement digital, analog and mixed signal control circuits as well as multiple power devices with breakdowns in excess of 100V and currents of up to 200mA. The Agile DPC line of products combines PWM Generation for 3 phases, High and Low Side Drive outputs for 3 phases, digitized current sampling of 2 phases with thermal, over/undervoltage detection. This paper will discuss the technology necessary to integrate these devices. A discussion of design parameters and simulation results will be included as well as the application demands to do so. A brief discussion on the future direction and capabilities of this technology will also be included. Background: Smart power ICs (PICs) are increasingly important in modern power electronic applications [1, 2], because they offer many benefits such as improved cost effectiveness, size reduction, better reliability and performance. In many previous designs [2-5], the smart PICs offered only limited analog sensing and gate drive functions. The protections are usually provided by ways of simple alarm-triggering circuits such as over current, over temperature, etc. The smart PIC would usually shut down if the sensed signal exceeds the preset level. This is usually the amount of signal processing and control algorithm that is available on chip. Brushless motor applications across multiple market segments such as automotive, pumps, motion control and home appliances have been demanding smaller and simpler drive and control configurations. A number integrated products exist that solve a specific aspect, but solutions that provide flexibility for multiple applications, motor types and performance are generally designed with a combination of programmable devices combined with gate drivers, and power transistors. The end-user is often left with the responsibility to determine the best method of interfacing the PICs to the low voltage signal processing chips. Integrating the digital CMOS with power MOSFETs allows provides the flexibility for multiple application solution. In order to successfully develop a fully integrated digital power solution, it is apparent that both a suitable high voltage fabrication process and high performance mixed signal processing circuit designs are critical.

2 In this report, the approach that Agile Systems Inc. has taken to design an integrated 3-phase motor drive controller will be described. The DPC smart PIC chip contains 6 high voltage LDMOS (Lateral Double diffused MOSFET) transistors that are capable of delivering an average current of up to 200mA each at more than 100V. A block diagram of this smart PIC motor controller is as show in Figure 1. This smart PIC demonstrated the integration of real time monitoring circuits and signal processing circuits to keep track and act on continuously changing operating conditions. The design consisted of an ADC for real-time monitoring of the smart PIC operating conditions such as supply voltage, load status, load current and temperature. The digital output from the ADC is then interfaced to an external controller that performs thorough analysis and takes immediate action to control/protect the smart PIC. An on board PWM generator can be used to convert an 8 bit single phase PWM digital to 3-phase analog PWM signals. Figure 1: Driver IC Block Diagram User inputs to the Driver IC are 12 bit serial PWM values. The Driver IC converts the PWM values into PWM complementary signals, provides dead time and then converts to the high side and low side signals for each of the 3 phases. The control logic circuit generates sample pulse and ADC conversion signals to allow the sampling of two current values, based on external analog inputs. The outputs from the Driver IC to the user are provided in serial form for the 2 current measurements, load status (open/short), high voltage reference signal and chip temperature. Figure 2 shows the Driver IC layout, highlighting the power, digital and analog sections. Over 60% of the die size is the power section, with isolation between the digital and analog sections in order to prevent cross talk from the high switching voltages on the power circuit to the low voltage digital and analog circuits.

3 Analog PowerIC Process: Digital Power Figure 2: Driver IC Layout Intense research on solid-state devices and integrated circuits in the past 20 years not only opened new frontier for high performance transistors and digital IC s, but also generated spin-off new opportunities for the use of power semiconductor devices. The emergence of microprocessor and rapid growth of VLSI technology has spurred power electronics engineer to focus more on system integration. This leads to cost reduction, performance improvement and product miniaturization. To produce good PowerICs (PICs), certain basic requirements have to be met: the availability of fabrication technologies suitable for the integration of high-voltage/current and low-voltage devices; the availability of power packages capable of dissipating the heat generated; and the ability to design innovative circuits and systems. The complexity of designing PICs and the cost of fabrication processes make the development of PICs much slower when compared to conventional VLSIs. There are two popular approaches to develop PICs. One is to start with an optimized high voltage fabrication process, and then try to integrate low voltage device with it. This would usually results in the best HV devices but at the expense of a very complex and expensive process. At the same time, the performance of the LV CMOS circuits is not optimized. The second alternative starts with a low voltage CMOS technology. Minor process modifications are then made to incorporate the high-voltage devices [6]. This approach is more favorable, especially for smart PIC chips that have a high percentage of LV CMOS circuits (since they are already optimized). The performance of the HV devices would suffer slightly (usually with a higher specific on-resistance). However, since a CMOS compatible fabrication process allow the re-use of large amount of existing LV CMOS circuit designs, the design cycle time can be greatly reduced using this approach.

4 incorporate the high voltage devices [2]. The second approach presents more economic potential and is compatible with modern CMOS processes. The fabrication process used in this research work is based on a CMOS compatible smart PIC process. The objective is to explore an innovative current sensing circuit for the output stages in PICs for motion control applications. In the early nineties, IC engineers had already succeeded in integrating power DMOS (double diffused signal components, MOSFET) transistors, dense CMOS small logic signal and components, also non-volatile dense memories CMOS logic into and a monolithic also non- In the early nineties, IC engineers had already succeeded in integrating power DMOS transistors, small chip. volatile An memories example process into a monolithic that can be chip. used An to implement example process the above that devices can be used and circuits to implement based on the 1µm twin-well CMOS technology as shown in Figure 3. Additional process modules for optional device above devices structures and can circuits, be added is based to the on basic 1.2μm CMOS twin-well process CMOS without technology. creating any Additional disturbance process to the modules normal for CMOS optional process device flow. structures This kind were of added CMOS to compatible the basic CMOS process process was further without developed creating for new generation 0.6µm lithography in the mid 90s, increasing the current density of power devices any disturbance and packing to the density normal in CMOS low voltage process control flow. circuits. Fig.1.1 illustrates an example of a typical PIC (a) PIC Process Architecture Power DMOS Option Gate 1 P body Metal 3 (b) PIC Process Cross-Section Standard Process CMOS Flow P Substrate P/N wells Locos Isolation Gate 2 LDD N+ S/D P+ S/D Metal 1&2 Passivation Tunnel oxide Bipolars Option N/P buried layer N epitaxial layer N+ deep collector EEPROM Option S G D D G S Body Body S G D C E B p+ p-body n-epi buried p+ p-well P-Substrate p-base Fig.1.1 Typical Modern PIC Technology Figure 3: A typical CMOS compatible PIC Technology The CMOS compatible approach presents more economic potential and is used in this 2 development of Agile Systems DPC line of products. The fabrication process used in this implementation a 2µm CMOS process that is modified to provide both grounded source and floating source n-channel LDMOS transistors. Both of these high voltage transistors were integrated with minimum processing changes to the original CMOS process. They are designed to withstand a minimum breakdown voltage of 120V and with a maximum current handling capability of 200mA per transistor. The specific on-resistance of these devices is rated at 10mΩ cm 2, higher than an equivalent transistor from a modified HV fabrication process, but provides and adequate basis for a platform of integrated gate drive. Power Circuits: n-epi buried p+ n-well p+ n-epi buried HV-LDMOS NMOS PMOS NPN Traditional motor drive utilize matched NMOS high and low side MOSFETs for the half bridge stage in order to take advantage of the lower ON Resistance of the NMOS devices. In order to

5 drive the gates of the high side MOSFET the ground reference for this high side gate drive is the source of the high side MOSFET, as indicated in Figure 4 as point VA. Figure 4: Bootstrap Schematic A bootstrap circuit is implemented on the Agile DPC products with external diode and capacitor required. Charging of the external capacitor C0 to VCC occurs at time t1 when LOA is on, HOA is off, and VA falls to GND, indicated in Figure 5. As HOA is turned on at t2, the voltage VBA is boosted to VHV + VCC. HOA LOA ON OFF 150ns t0 t1 t2 t3 t4 Analog Design: Figure 5: Bootstrap Timing Diagram Agile chose to implement a successive approximation ADC as this approach is a reasonable compromise on size and speed and simplicity for the motor drive application. The 8 bit ADC requires 416 ns for conversion. Extending this to 10 bits would require a total of 520ns. For the motor control application with 20kHz PWM available conversion time is 6.4µs. Implemented with 2µm process the size can be reduced with smaller lithography, however performance improvements would not be significant. Figure 6 highlights the successive approximation simulation across the 6.4µs.

6 Conclusions and Future Directions: Figure 6: ADC Output Pending test results, this Gate Drive IC will provide the core of a complete single chip programmable brushless motor drive. Selection of the major process and circuit components have been selected provide the least complex solution possible. The existing device will simplify drive design by reducing the user interface requirements. Ongoing activities in the development of the Power IC devices and process have been identified to increase the current density of the device and increase capability in the digital processing. Using the core Driver IC it will be possible to either increase the current ratings, add additional processing or both in order to achieve a programmable drive in a single IC. References: [1] T.M. Jahns, Designing Intelligent Muscle into Industrial Motion Control, Trans. Industrial Electronics, vol. 37, no.5, IEEE, Oct. 1990, pp [2] K. Buss, L. Latham, M. Manternach, B. Shear, D. Mosher, D. Agiman, S. Kwan, D. Cotton, A 10A Automotive High-Side Switch, ISSCC, IEEE 1990, pp [3] A. Marshall, F. Carvajal, Power and logic methodology applied to a six output power driver, Proc. Bipolar/BiCMOS Circuits and Technology Meeting, IEEE Oct. 1993, pp [4] A. Marshall, J. Devore, W. Grose, Design Techniques for an Intelligent Fuel Injector IC, Proc. ISCAS, vol. 2, IEEE, May 1992, pp [5] Texas Instruments, 4-channel serial and parallel low-side pre-fet driver - TPIC44L01, TPIC44L02, TPIC44L03 Data Sheet, Sept [6] B.Murari, F.Bertotti, G.A.Vignola Smart Power ICs Technologies and Applications, Springer-Verlag, Berlin, 1996.