CMOS Logic Technology IEEE EDS DL

Transcription

1 IIT-bombay, Tutorial CMOS Logic Technology IEEE EDS DL January 24, 2013 IIT-Bombay, Mumbai, India Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology 1

2 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

3 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

4 More Moore to More More Moore Technology node 65nm 45nm 32nm Now 22nm Future 15nm, 11nm, 8nm, 5nm, 3nm L g 35nm L g 30nm Si Planar Tri-Gate Si channel Main stream (Fin,Tri, Nanowire) Si is still main stream for future!! Alternative (ETSOI) ET: Extremely Thin M. Bohr, pp.1, IEDM2011 (Intel) P. Packan, pp.659, IEDM2009 (Intel) C. Auth et al., pp.131, VLSI2012 (Intel) T. B. Hook, pp.115, IEDM2011 (IBM) S. Bangsaruntip et al., pp.297, IEDM2009 (IBM) Others Alternative (III-V/Ge) Channel FinFET Emerging Devices 4

5 45nm EOT:1nm Hf-based oxides EOT=0.9nm HfO 2 /SiO 2 (IBM) 32nm EOT:0.95nm Continued research and development High-k k gate dielectrics SiO 2 IL (Interfacial Layer) is used at Si interface to realize good mobility TiN HfO 2 SiO 2 K. Mistry, et al., p.247, IEDM 2007, (Intel) T.C. Chen, et al., p.8, VLSI 2009, (IBM) T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.) K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.) Si 22nm EOT:0.9nm 15nm, 11nm, 8nm, 5nm, 3nm, Technology for direct contact of high-k and Si is necessary MG La-silicate Si EOT=0.52 nm Remote SiO 2 -IL scavenging HfO 2 (IBM) EOT=0.37nm EOT=0.40nm EOT=0.48nm nm Increase of I d at 30% Direct contact with La-silicate (Tokyo.Tech)

6 I ON and ON I benchmark OFF I OFF [na/µm] IBM [5] GAA NW V DD =1V 1 NMOS Intel [1] Bulk 32nm V DD =0.8V Samsung [3] Bulk 20nm V DD =0.9V IBM [10] ETSOI V DD =0.9V I eff Toshiba [4] Tri-Gate NW V DD =1V Intel [1] Tri-Gate 22nm V DD =0.8V IBM [6] FinFET 25nm V DD =1V STMicro. [8] GAA NW V DD =0.9V IBM [7] ETSOI V DD =0.9V Intel [2] Bulk 45nm V DD =1V Tokyo Tech. [9] Ω-gate NW V DD =1V IBM [7] ETSOI V DD =1V STMicro. [8] GAA NW V DD =1.1V I ON [ma/µm] I OFF [na/µm] PMOS IBM [10] ETSOI V DD =0.9V I eff Intel [1] Bulk 32nm V DD =0.8V Samsung [3] Bulk 20nm V DD =0.9V IBM [7] ETSOI V DD =0.9V Intel [2] Bulk 45nm V DD =1V IBM [6] FinFET 25nm V DD =1V IBM [5] GAA NW V DD =1V Intel [1] Tri-Gate 22nm V DD =0.8V IBM [7] ETSOI V DD =1V STMicro. [8] GAA NW V DD =1.1V I ON [ma/µm] [1] C. Auth et al., pp.131, VLSI2012 (Intel). [6] T. Yamashita et al., pp.14, VLSI2011 (IBM). [2] K. Mistry et al., pp.247, IEDM2007 (Intel). [7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM). [3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). [4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) [5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [10] K. Cheng et al., pp.419, IEDM2012 (IBM)

7 Comparison with ITRS Intel ITRS2007~ nm32nm 22nm V DD ITRS2007~ L g (nm) L 1.6 g ITRS2007 ITRS2009~ nm 45nm 32nm Intel EOT Year Bulk Planar Multi-Gate EOT (nm) L g and EOT are larger than ITRS requirements Implementation of Tri-gate and lower V th /V dd since 22nm V DD (V) nm 32nm Intel 22nm 45nm Intel Bulk Planar Multi-Gate 32nm V th 22nm Year Vth (V) K. Mistry et al., pp.247, IEDM2007 (Intel). P. Packan et al., pp.659, IEDM2009 (Intel). C. Auth et al., pp.131, VLSI2012 (Intel).

8 Benchmark of device characteristics Intel (IEDM2007, 2009) Intel (VLSI2012) Toshiba (VLSI2012) IBM (IEDM2012) Samsung (IEDM2012) IBM (IEDM2009) STMicro. (VLSI2008) Tokyo Tech (ESSDERC2010) Structure Bulk Planar 45nm 32nm Tri-Gate 22nm Tri-Gate NW ETSOI Bulk Planar GAA NW GAA NW Ω-gate NW 35/25 22/30 L g (nm) (nfet/pfet) (nfet/pfet) Gate Dielectrics Hf-based Hf-based SiO 2 HfO 2 HfO 2? Hf-based HfZrO 2 SiO 2 EOT (nm) ~ V th (V) ~0.4 ~0.3 ~ (nfet) 0.3~0.4 ~ ~0.4 ~ (nfet) V DD (V) I ON (ma/um) nfet/pfet DIBL (mv/v) nfet/pfet SS (mv/dec) 1.36/ / / (nfet) 0.59/0.62 (I eff ) 1.2/ / / (nfet) ~150 ~200 46/50 <50-104/115 65/105 56/ ~100 ~70 < <80 70

9 Short-channel effect T. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)

10 Drain-induced induced barrier lowering T. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

11 Sub-threshold Slope T. Skotnicki, IEDM 2010 Short Course (STMicroelectronics) 95 mv/dec 110 mv/dec 85 mv/dec 75 mv/dec 65 mv/dec

12 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

13 Tri-gate implementation for transistors C. Auth et al., pp.131, VLSI2012 (Intel) HP MP SP T OX,E (nm) L GATE (nm) Tri-gate has been implemented since 22nm node, enabling further scaling I OFF (na/um)

14 Tri-gate width/height optimization C. Auth et al., pp.131, VLSI2012 (Intel) PMOS channel under the gate S/D region showing the SiGe epitaxy A fin width of 8nm to balance SCE and R ext A fin height of 34nm to balance drive current vs. capacitance

15 Tri-gate I d -V g characteristics and V th C.-H. Jan et al., pp.44, IEDM2012 (Intel) SS of 71 and 72 mv/dec for HP NMOS and PMOS, respectively DIBL of 30 and 35 mv/v for NMOS and PMOS, respectively V th of 22 nm is about 0.1 ~0.2 V lower than that of 32nm

16 Tri-gate I and ON I characteristics OFF C.-H. Jan et al., pp.44, IEDM2012 (Intel) NMOS PMOS I ON (ma/um) NMOS/PMOS HP SP LP ULP 1.08/ / / /0.33 V dd = 0.75 V I OFF 100nA/um 1 na/um 30 pa/um 15 pa/um I ON /I OFF > 10 5 I ON /I OFF ~10 5 ~10 6 ~10 8 ~10 8

17 S. Saitoh et al., pp.11, VLSI2012 (Toshiba) Tri-Gate Nanowire L g = 14nm Tri-Gate NW High SCE immunity at L g of 14nm V th tuning by applying V sub with thin BOX of 20nm V sub

18 H.-J. Cho et al., pp.350, IEDM2011 (Samsung) Bulk Planar L g = 20nm bulk planar CMOS Gate last integration In-situ doped S/D for better SCE

19 Extremely Thin SOI (ETSOI) K. Cheng et al., pp.419, IEDM2012 (IBM) Hybrid CMOS Si Channel nfet Strained SiGe Channel pfet RO delay improvement over FinFET with FO = 2

20 Gate All Around Nanowire (GAA NW) S. Bangsaruntip et al., pp.297, IEDM2009 (IBM) L g = 25~35nm GAA NW Hydrogen anneal provide smooth channel surface Competitive with conventional CMOS technologies Scaling the dimensions of NW leads to suppressed SCE

21 Gate All Around Nanowire (GAA NW) G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics) NiPtSi SiN HM Top Gate Channel Bottom Gate Gate all around structure L g of 22~30nm Bulk wafer-based integration High drive currents by special stress and channel orientation design

22 S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) SiO 2 SiN NW SiO 2 L g =65nm Ω-gate Si Nanowire Poly-Si SiN I ON (ma/µm) 12 nm 19 nm 1.E-03 1.E E E E E E E E Drain Current (A) 1.E L g =65nm V d =-1V V d =-50mV pfet V d =1V V d =50mV nfet Gate Voltage (V) Conventional CMOS process High drive current (1.32 I OFF =117 na/µm) DIBL of 62mV/V and SS of 70mV/dec for nfet

23 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

24 Problems in Multi-gate S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI) Decreasing the diameter of NW Improved short-channel control Severe mobility degradation

25 K. Uchida et al., pp.47, IEDM2002 (Toshiba) Problems in SOI Mobility is also decreased with decreasing the Si thickness of SOI transistor similar to the NW transistor.

26 Impact of Si thickness in FinFET J. B. Chang et al., pp.12, VLSI2012 (IBM) Replacement Gate process TaN/HfO 2 gate stack Reduced g m and higher V th with decreasing Fin width

27 J. B. Chang et al., pp.12, VLSI2012 (IBM) V variability th nfets pfets Significant increase in V th variability with decreasing Fin width

28 EOT Scaling Trends K. Kim, pp.1, IEDM2010 (Samsung) EOT [nm] ITRS2011 Fin width Planar Trend 1 Trend 3? Multi- Gate Trend Body Thickness [nm] Year Smaller wire/fin width is necessary for SCE suppression 0 But mobility and I ON severely degrade with wire/fin width reduction Therefore even in multi-gate structures EOT scaling could be accelerated to provide SCE immunity

29 Metal S/D Advantages of metal S/D - atomically abrupt junction - low parasitic resistance S - reduced channel dopant concentration Issues in metal S/D - two different φ B for p/n-ch FETs - underlap/overlap to the gate - narrow process temperature window BOX Si D Dopant Segregation layer L. Hutin, pp.45, IEDM2009 (CEA-LETI) Metal S/D is considered for alternative channel material such as InGaAs and Ge Ni is used both on InGaAs and Ge to form alloy. S.-H. Kim, IEDM (2010) 596 K. Ikeda, VLSI (2012) 165

30 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

31 Ge,III-V V bulk properties S. Takagi., IEDM2011, Short course (Tokyo Uni)

32 Multi-gate III-V V and Si benchmark I OFF (A/µm) InGaAs GAA L ch =50nm, Dielectric: 10nm Al 2 O 3 V DS =0.5V (Purdue Uni.) [1] Si FinFET 32nm Intel V DD =0.8V [10] InGaAs FinFET L ch =130nm EOT 3.8nm V DS =0.5V (NUS)[3] nmos InGaAs Tri gate L g =60 nm,eot 12A V DS =0.5V (Intel) [2] InGaAs Nanowire Lg= 200nm, T ox 14.8nm V DS =0.5V(Hokkaido Uni.)[4] Si FinFET 22nm Intel V DD =0.8V [10] Si bulk 45nm Intel V DD =1V[11] Metal S/D InGaAs OI L ch = 55nm, EOT 3.5nm V DS =0.5V(Tokyo Uni.)[5] GOI Tri gate L g : 65nm. EOT 3.0nm V D = 1V (AIST Tsukuba)[6] Ge FinFET L g =4.5 mm, Dielectric: SiON, V DS = 1V (Stanford Uni.)[7] Ge GAA L g = 300nm, dielectric: GeO 2 (7nm)-HfO 2 (10nm) V D = -0.8V (ASTAR Singapore)[8] Ge Tri gate L g =183nm, EOT 5.5nm V D = 1V (NNDL Taiwan)[9] pmos Si FinFET 22nm Intel V DD =0.8V [10] Si FinFET 32nm Intel V DD =0.8V [10] Si bulk 45nm Intel V DD =1V I ON (ma/µm) [1] J. J. Gu et al., pp.769, IEDM2011 (Purdue). [6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba). [2] M. Radosavljevic et al., pp.765, IEDM201(Intel). [7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni) [3] H. C. Chin et al., EDL 32, 2 (2011) (NUS) [8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore) [4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni). [9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan) [5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) [10] C. Auth et al., pp.131, VLSI2012 (Intel). I ON (ma/µm) [11] K. Mistry et al., pp.247, IEDM2007 (Intel).

33 I ON /I OFF Benchmark of Ge pmosfet

34 III-V/Ge benchmark for various structures Planar (metal S/D, Strain, Buffer ) FinFET Tri gate Gate all around MOSFET Nanowire material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs (multishell) Ge Dieletric /EOT Al 2 O 3 / 3.5 nm 7.6 A o HfO 2 + Al 2 O 3 +GeO 2 5nm ALD Al 2 O 3 5nm ALD Al 2 O 3 SiON 1.2 nm 5.5 nm (Al 2 O 3 + GeO 2 ) 10nm ALD Al 2 O 3 HfO 2 : 11nm HfAlO 14.8 nm 3.0 nm (ALD Al 2 O 3 ) Mobility ~600 (cm 2 /Vs) N s : 5e12 e: 200 h: 400 (cm 2 /Vs) ~700 (µs/µm ) 701 (µs/µm) ~500 (µs/µm) ~850 (cm 2 /Vs) L ch (nm) 55 W/L= 30/5 µm 50 µm µm DIBL (mv/v) ~ SS (mv/dec) K 61pMOS 33nMOS 120K I ON (µa/µm) 278 (V D =0.5V) 3 (V D = 0.2V) 4 (n,p) (V D =0.5V) 10 (V D =0.5V) 400 (V D =0.5V) 235 (V D = 1V) 180 (V D =0.5V) 604 (V D = 0.5V) 100 (V D =0.5V) 731 (V D = 1V) Research Group Tokyo Uni VLSI 2012 Tokyo Uni VLSI 2012 Stanford Uni VLSI 2012 Purdue Uni IEDM 2009 Stanford Uni ELD 2007 Intel IEDM 2011 NNDL Taiwan IEDM 2011 Purdue Uni IEDM 2011 ASTAR Singapore IEDM 2009 Hokkaido Uni, IEDM 2011 AIST Tsukuba VLSI 2012

35 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

36 InGaSb as channel material (stanford) Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni) Hole Mobility Si InGaSb Electron Mobility InGaSb Si AlGaSb creates barrier for both electrons and holes Achieving both N and P type MOSFET on a single channel is possible In content of 20 40% improves perfomance electron/hole mobility > 4000/900cm 2 /Vs was gained in a single channel material I ON at L G = 50 µm pmos: 4 µa/µm nmos: 3.8 µa/µm

37 Metal S/D InGaAs MOSFET (Tokyo Uni) Metal S/D and InAs buffer layer are used as performance boosters. DIBL=84 mv/v and SS=105 mv/v was shown for L ch = 55 nm when In content was higher. S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)

38 Common InGaAs GeSn gate stack (NUS) X. Gong, et al. (National Uni of Singapore), VLSI2012, p.99. V GS -V TH = 0 2.0V L G = 5µm Common gate stack (gate metal and dielectric) were used for both p and n type Si 2 H 6 plasma passivation is employed which creates Si layer at interface. SS: nmos: 90 (mv/decade) pmos: 190 (mv/decade) High intrinsic peak G M,Sat =of ~465 S/ m at V DS =-1.1 V was achieved for L G =250 nm.

39 InGaAs nanowire transistor(hokkaido Uni) T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773. Core-multishell InGaAs nanowires grown without buffer layer on Si substrate (bottom up approach) At V d = 1 V peak transconductance of 500 ms/mm is achieved (roughly x3 InGaAs nanowire)

40 Tri-gate InGaAs QW-FET(Intel) M. Radosavljevic, et al.(intel), IEDM2011, p.765. Tri-gate structure has superiority electrostatic controllability compared to ultra-thin body planar structure Steepest SS and smallest DIBL ever reported (W fin = 30nm)

41 Gate all around InGaAs MOSFET(Purdue) P. D. Ye, et al (Purdue Univ)., IEDM2011, p.769. W fin = 50nm W fin = 30nm Inversion mode In 0.53 Ga 0.47 As MOSFET with ALD Al 2 O 3 /WN with well electrostatic properties DIBL was suppressed down to L ch = 50nm and G m,max =701mS/mm at V ds = 1V

42 InGaAs FinFET (NSU) H.C. Chin, et al. (National Uni of Singapore)., EDL2011,Vol.32 p.146. L CH = 130nm DIBL =135 mv/v and drive current over 840 µa/µm at L ch = 130nm and V ds = 1.5V was achieved

43 Ge-nanowire pmosfet (AIST,Tsukuba) K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165. L g = 65nm W wire = 20nm V D = -1V V D = -0.5V V D = -0.05V V g -V th = -2V Using Ni-Ge alloy as metal S/D Significantly reduces contact resistance High saturation current and high mobility eff = 855 cm 2 /Vs at Ns =5x10 12 cm -2 and saturation drain current of 731 A/ m at V d = -1V

44 Ge triangular pmosfet (NNDL,Taiwan) S-H. Hsu, et al. (NNDL,Taiwan), IEDM2011, p L g >2W fin L g <2W fin Ge Rectangular Ge Triangular Selective etching of high defect Ge near Ge/Si interface is used which improves gate controllability. I ON /I OFF = 10 5 and SS= 130 mv/dec And I ON = 235 µm/µm at V D = -1V

45 Implementing high-k k material to III-V,Ge III-V (InGaAs, InAs,InGaSb, ) ALD-Al 2 O 3 is most commonly used as gate dielectric in planar or Multi-gate HfO 2 -only stacks have high D it (combination of Al 2 O 3 or Al or Si is used) Al 2 O 3 Si-HfO 2 Al 2 O 3 +HfO 2 HfAlO x TaSiOx 3.4 nm 1.2 nm In 0.7 Ga 0.3 As In 0.53 Ga 0.47 As E. Kim, et al., APL96, Ge By controlling the formation of GeOx at the interface, HfO 2 and Al 2 O 3 show good results. NUS, VLSI 2012 L. Chu, et al.,apl99, Hokkaido Uni, IEDM 2011 Intel, IEDM 2010 R. Zhang et al., VLSI2012,p161

46 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

47 Emerging devices(future scaling trends) Carbon based FET Carbon nanotube Graphene J. P. Colinge et al., Nature Nano. 5(2010)225 Junctionless Transistor A. D. Franklin et al., pp.525, IEDM2011 (IBM) Cut off frequency ( GHz) GaAs mhemt (20nm) F. Schwlerz, Nature Nano,Vol.5 p Gate length (nm) L. Liao, et al., Nature,Vol.467 p.305. SiMOSFET (29nm) GaAs phemt (100nm) CNT Graphene M. Lemme, Nanotech workshop,2012 All spin logic device J. P. Colinge et al., Nature Nano. 5(2010)266 Input and output related via Spin-coherent channel

48 Tunnel FET A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame) Band to band tunneling Low I OFF, Low V DD, SS<60mV/decade

49 TFET vs. MOSFET at low V DD A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame) V DD 0.3~0.35V TFET 8x faster at the same power parameter variation is not a significant factor for differentiation between MOSFET and TFET

50 Tunnel FET (Si) A. Villalon, pp.49, VLSI 2012 (CEA-LETI) X in Si 1-x Ge x is optimized to allow for efficient BTBT L G = 200nm I ON /I OFF ~10 5 Reducing SiGe Body thickness improves Subthreshold swing. 130mV/dec Gate Voltage (V) 190mV/dec

51 K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University) SS=110mV/dec SS=21mV/dec V DS =1V Tunnel FET (III-V) HfAlO x Gate Conventional FET limit SS= 60 mv/dec V DS = 1V NW Diameter= 30nm SS of TFET is function of V G due to Zener tunnel current Minimum SS= 21 mv/dec is reached due to optimized series resistance of contact, undoped InAs and InAs/Si I ON /I OFF ~10 6 at V DS = 1.0V (I ON = 1Aµ/µm)

52 Device structure A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame) K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)

53 Tunnel FET performance comparison A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame) measured III-V channel TFETs S MIN : S EFF : Most common SS which is the inverse of I D -V GS slope at the steepest part Is the average swing when V TH =V DD /2 V OFF =0 I th I D I OFF V off V TH V GS Average SS: V OFF =0 V TH =V DD /2 Effective SS:

54 I ON and ON I of OFF TFETs [1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame) I OFF [na/µm] TFET V DS =0.75V TFET V DS =1.05V TFET V DS =1V Intel Bulk 32nm V DD =0.8V Si MOSFET Intel Bulk 45nm V DD =1V Intel Tri-Gate 22nm V DD =0.8V I ON [ma/µm] C. Auth et al., pp.131, VLSI2012 (Intel). K. Mistry et al., pp.247, IEDM2007 (Intel).

55 MEMS relay ON-state resistance [Ohm] Number of Operation Cycles Frequency of 1, 5, 25kHz under operation I ON /I OFF of ~10 10 Ultra-low-power digital logic applications. T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley)

56 Si Junctionless Transistor (Intel) R. Rios et al., EDL. 32(2011)1170 (Intel) L g (nm) L g (nm) L g (nm) IM : Conventional Inversion Mode JAM LD : Janctionless Accumulation Mode with low dope JAM HD : Janctionless Accumulation Mode with high dope JAM devices have reduced gate control and degraded shortchannel characteristics relative to IM Not suitable for high-performance logic (high I on and moderate I off )

57 Nanowire Junctionless Transistor J. P. Colinge et al., Nature Nano. 5(2010)225 Lg= 1µm Lg= 1µm W wire = 30nm 10nm 30.5nm Silicon nanowire is uniformly doped Gate material is opposite polarity polysilicon Near-ideal subthreshold slope, close to 60 mv/dec at room temperature, and extremely low leakage currents I ON /I OFF ~1x10 6 I OFF is smaller than A (-1<V g <1)

58 Carbon nanotube and Graphene K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030 SWCNT : single wall carbon nanotube GNR : graphene nano ribbon Carbon materials for FET applications an ultra-thin body for aggressive channel length scaling excellent intrinsic transport properties similar to carbon nanotubes pattern the desired device structures

59 Sub-10nm carbon nanotube transistor A. D. Franklin et al., pp.525, IEDM2011 (IBM) Transistor operation with L ch of 9nm

60 Graphene Field-effect effect Transistor Z. Chen et al., pp.509, IEDM2008 (IBM) J. B. Oostinga et al., Nature Materials 7 (2008) 151 Ambipolar Characteristics Bi-layer graphene and double gates can open the gap

61 2D material : single layer MoS 2 H. Wang et al., pp.88, IEDM2012 (MIT) Mobility of 190 cm 2 /Vsec I on of 1 µa/µm at V DD = 1V Candidate : MoS 2, MoSe 2, WS 2, WSe 2, MoTe 2, WTe 2

62 Spin transfer Torque Switching MOSFET T. Marukame et al., pp.215, IEDM2009 (Toshiba) Magnetic tunnel junction on S/D L g = 1µm Read/write are enabled by using ferromagnetic electrodes and Spin-polarized current

63 Summary of Emerging Technology pro/cons Advantage Issues TFET CNT FET Graphene FET MEMS Junctionless FET Spin FET Lower V dd Lower I OFF Higher transport velocity L g scaling RF application Large area manufacturing Extremely low leakage Ultra-low digital logic CMOS process compatibility Low power, suitable for memory (nonvolatile info storage) Integration higher I ON High density and alignment, reproducibility, integration NOT a direct replacement for Silicon logic Endurance Slow speed, scalability Worse gate control in short-channel Low efficiency of spin injection

64 More Moore approach Technology benchmark Advance Si-based CMOS devices and technologies Challenges Alternative channel material devices Technology benchmark III-V, Ge-based devices Emerging technologies (Tunnel FET, Junctionless FET, Carbon-based FET, MEMS, Spin-based Logic) Conclusions Outline

65 Conclusions New device structures (FinFET, Tri-gate) are replacing conventional Planar CMOS Same performance at lower supply voltage HKMG: Continuous innovation has enabled EOT scaling to 9 A o, however, new material could be needed for further EOT scaling. La-based high-k material Recent advances in new channel material shows promising device performances comparable to state of the art Si-based MOSFETs. The combination of III-V channel materials with a multigate structure appears to be a promising direction. (Higher performance in lower operating voltage) Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET..) is increasing, But more time is needed for implementation of these technologies in future generation devices as mature technologies.