Future of Nano CMOS Technology

Transcription

1 July 4, 2014, MQ, Dalian, China Future of Nano CMOS Technology Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology 1

2 Back ground for nano-electronics 2

3 Feature Size / Technology Node (1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm 0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012) 14 nm (2014) From 1970 to 2013 (Last year) 43 years 1 generation 18 generations 2.5 years Line width: 1/450 Line width: 1/1.43 = 0.70 Area: 1/200,000 Area: 1/2 = 0.5 3

4 Importance of nano-cmos 4

5 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament dreamed of replacing vacuum tube with solid-state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 5

6 1960: First MOSFET by D. Kahng and M. Atalla Top View Al SiO 2 Si Si/SiO2 Interface is extraordinarily good 6

7 1970,71: 1st generation of LSIs DRAM Intel 1103 MPU Intel

8 In 2012 Most Recent SD Card 128GB (Bite) = 128G X 8bit = 1T(Tera)bit 1T = = 1Trillion World Population:7 Billion Brain Cell:10~100 Billion Stars in Galaxy:100 Billion 8

9 128 GB = 1Tbit 2.4cm X 3.2cm X 0.21cm Volume:1. 6cm³ Weight:2g Voltage: V Old Vacuum Tube: 5cm X 5cm X 10cm, 100g, 50W What are volume, weight, power consumption for 1Tbit 9

10 Old Vacuum Tube: 5cm X 5cm X 10cm 1Tbit = 10,000 X 10,000 X 10,000 bit Volume = (5cm X 10,000) X (5cm X 10,000) X (10cm X 10,000) = 0.5km X 0.5km X 1km Pingan Intenational Indian Tower Finance Center Mumbai, India Shanghai, China (Year 2016) (Year 2016) Burji Khalifa Dubai, UAE (Year 2010) 500 m 700 m 700 m 828 m 1Tbit 1,000 m 10

11 Old Vacuum Tube: 50W 1Tbit = bit Power = 0.05kWX10 12 =50 TW Nuclear Power Generator 1MkW=1BW We need 50,000 Nuclear Power Plant for just one 128 GB memory In Japan we have only 54 Nuclear Power Generator Last summer Tokyo Electric Power Company (TEPCO) can supply only 55BW. We need 1000 TEPCO just one 128 GB memory Imagine how many memories are used in the world! 11

12 So progress of integrated circuits is extremely important for power saving. 12

13 Brain: Integrated Circuits Ear, Eye:Sensor Mouth:RF/Opto device Stomach:PV device Hands, Legs:Power device 13

14 Near future smart-society has to treat huge data. Demand to high-performance and low power CMOS become much more stronger. 14

15 Semiconductor Device Market will grow 5 times in 12 years, even though, it is very matured market!! B USD 1,500B USD Gartner: By K. Kim, CSTIC

16 Recent situation for nano-cmos 16

17 Ballistic conduction will not happen even decreasing channel lengh. L source drain :Mean free path L Diffusive transport L ~ Quasi-Ballistic transport L Ballistic transport Ballistic transport will never happen for MOSFET because of back scattering at drain Mobility Theory With decreasing channel length, Drain current increase continue. Real nanoscale MOSFETs Back scattering from drain 一次元バリスティック伝導 Also, 1D quantum conduction, or ballistic conduction will not happen. (1D quantum conduction: 77.8mS regardless of the length and material). 17

18 Then, now!. Noticed that the technology is difficult. Development of EUV (Extreme Ultra Violet) lithography delayed significantly. %253A%3B6JNTCrv867Tq0M%3Bhttp%253A%252F%252Ftechon.nikkeibp.co.jp%252Farticle%252FNEWS%252F %252F122347%252FEUV.jpg%3Bhttp%253A%252F%252 Ftechon.nikkeibp.co.jp%252Farticle%252FNEWS%252F %252F122347%252F%253FSS%253Dimgview_scr%2526FD%253D %3B750%3B562 18

19 Noticed that the technology is difficult. In addition with the significant delay in EUV (Extreme Ultra Violet) lithography delayed significantly, - Reduction of the thickness of High-k gate oxide becomes very difficult. - Decreasing supply voltage becomes difficult because of subtreshold leakage and variability of thereshold voltage. 19

20 Now Technology development delayed. Shrink rate of gate length will become from 07 to 0.8 or Number of the semiconductor companies which can develop state of the art technology decreasing. In the past, technologies come with the purchase of equipment's But now, every companies are facing threat of dropping off, unless they concentrated on the development of technologies. Thus, technology development is becoming much important. 20

21 21 Question What is the problem for downsizing?

22 The problem for downsizing S and D distance small Ion & Ioff increase Ioff increase: Transistor cannot be turned-off. Ioff (Off-leakage current) between S and D 1. Punch-through between S and D 2. Direct-tunneling between S and D 3. Subthreshold current between S and D 22

23 1. Punch-through between S and D 23

24 Region governed by gate bias 0V Problem for downsizing Region governed By drain bias DL touch with S Region (DL) 0V 0V Source Channel Substrate 0V Gate metal Gate oxide 0V 1V Drain 0V < V dep <1V Depletion Region (DL) by Drain Bias No t ox. V dd thinning Large I OFF 0V Large I OFF 0V 1V 0V < V dep <1V (Electron current) 0V 0V V dd 0V V dd 0.5V t ox and V dd have to be decreased for better channel potential control I OFF Suppression 24

25 1. Punch-through between S and D There are 3 solutions to suppress the depletion layer A. Decrease supply voltage Very difficult as explained later B. Decrease tox to enhance the channel potential controllability by gate bias C. Gate/channel configuration change to enhance the channel potential controllability by gate bias Fin-FET, ET-SOI, etc. 25

26 t ox ( B.Decrease tox A. Toriumi (Tokyo Univ), IEDM 2006, Short Course ( 26

27 C. Configuration change for channel and gate structures for better control of channel potential. Fin-FET, ET-SOI, etc. 27

28 Extremely Thin (or Fully-Depleted) SOI - Make Si layer thin - Control channel potential also from the bottom 0V S 0V G 1V 0V S G 0V 0V 1V D Planar 0V <V<1V 0V SiO 2 Drain bias induced depletion Extremely thin Si Si G 0V ET (or FD) SOI 28

29 Surrounding gate structure (Multiple gates) - Make Si layer thin - Control channel potential also by multiple gates not only from top & bottom but maybe also from side 0V S 0V G 1V 0V S 0V G 0V Drain bias induced depletion 1V D Si fin or nanowire Planar 0V <V<1V 0V G 0V Multi gate 29

30 G New structures! Multi-gate structures G G G G G Fin Tri-gate Tri-gate (Variation) W-gate All-around 30

31 Our work at TIT: W-gate Si Nanowire S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) SiO 2 SiN NW SiO 2 L g =65nm Poly-Si SiN I ON (ma/mm) 12 nm 19 nm 1.E E E E E E E E E Drain Current (A) 1.E L g =65nm V d =-1V V d =-50mV pfet V d =1V V d =50mV nfet Gate Voltage (V) Conventional CMOS process High drive current (1.32 I OFF =117 na/mm) DIBL of 62mV/V and SS of 70mV/dec 31 for nfet

32 2. Direct-tunneling between S and D Wave function of electron penetrates the channel potential barriers by quantum mechanical physics, when the channel length is around 3 nm. 32

33 Energy or Potential for Electron Built-in potential between Source and Channel pn junction < 0.7 V When transistor is at off state 3 nm Tunneling distance Direct-tunnel current There is no solutions! Source Channel Drain Downsizing limit Lg = 3 nm. 33

34 3. Subthreshold current between S and D 34

35 Subtheshold leakage current of MOSFET Id Ion Subthreshould Leakage Current OFF ON Vg=0V Subthreshold region Vth (Threshold Voltage) Vg 35

36 Subthreshold leakage current I d (A/mm) I on Electron Energy Boltzmann statics 10-5 V d Exp (qv/kt) I off V th 0.15 V 0.5 V 1.0 V 0.3 V V g (V) Lg 1/2 Vd, Vg 1/2 Vth 1/2 However Ioff 10 3 in this example Because of log-linear dependence 36

37 Subtheshold leakage current of MOSFET Id Ion Subthreshold Current Is OK at Single Tr. level Subthreshould Leakage Current OFF ON But not OK For Billions of Trs. Vg=0V Subthreshold region Vth (Threshold Voltage) Vg 37

38 3. Subthreshold current between S and D Solution: however very difficult Keep Vth as high as possible - Do not decrease supply voltage, Vd However, punchthough enhanced - Suppress variability in Vth Thus, subthreshold current will limit the downsizing, especially for mobile devices 38

39 Operation Frequency (a.u.) The limit is deferent depending on application 100 e) 10 1 Subthreshold Leakage (A/mm) Source: 2007 ITRS Winter Public Conf. 39

40 How far can we go for production? Past 0.7 times per 2.5 years 10mm 8mm 6mm 4mm 3mm 2mm 1.2mm 0.8mm 0.5mm 0.35mm 0.25mm 180nm 130nm 90nm 65nm 45nm 32nm Now Future Limit depending on applications Subthreshold punchthrough Fundamental limit Direct-tunnel (28nm) 22nm 14nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? Intermediate node At least 4,5 generations to 8 ~ 5 nm 40

41 However, careful about the name of technology! Recently, Gate length (Lg) is much larger than the Technology name 22 nm Technology by Intel Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP) IEDM 2012, VLSI nm Technology by Global Lg (Gate length) = 25 nm Euro SOI nm Technology by Leti (FD-SOI) Lg (Gate length) = 15 nm

42 ITRS 2013 (Just published in April 2014) Year Commercial name (nm) Metal half pitch (nm) L g (nm) (L g for ITRS 2007) L g for low stand by power (nm) V dd (V) (V dd (V) for ITRS 2007) EOT (nm) (EOT (nm) for ITRS 2007) T Si (nm) (T Si (nm) for ITRS 2007) 20.2 (13) (0.90) 0.80 (0.60) 7.4 (6.0) (10) (8) (6) (5) (4.5 in 2022) (0.80) (0.70) (0.70) (0.65)(0.65 in 2022) (0.60) (0.55) (0.50) (0.50)(0.50 in 2022) (6.0) (4.5) (3.8) (3.2) (3.0 in 2022)

43 The rate for the shrinkage for the gate length and line pitch will be larger than 0.7 in near future, because of the subthreshold leakage, and also because of the delay in EUV lithography. As a result, we will have more technology generations until reaching the downsizing limit, and the time to reach the limit will be delayed.

44 How far can we go for production? Thus, we may go down to 1.5 nm technology node by choosing whatever gate length we want for the application. 44

45 More Moore to More More Moore Technology node Now Future 65nm 45nm 32nm 22nm 15nm, 11nm, 8nm, 5nm, 3nm L g 35nm L g 30nm (Fin,Tri, Nanowire) Si Planar Tri-Gate Si channel (ETSOI) 28nm Si is still main stream for future!! ET: Extremely Thin M. Bohr, pp.1, IEDM2011 (Intel) P. Packan, pp.659, IEDM2009 (Intel) C. Auth et al., pp.131, VLSI2012 (Intel) T. B. Hook, pp.115, IEDM2011 (IBM) S. Bangsaruntip et al., pp.297, IEDM2009 (IBM) Others Alternative (III-V/Ge) Channel FinFET Emerging Devices

46 45nm EOT:1nm Hf-based oxides EOT=0.9nm HfO 2 /SiO 2 (IBM) 32nm EOT:0.95nm Continued research and development High-k gate dielectrics SiO 2 IL (Interfacial Layer) is used at Si interface to realize good mobility TiN HfO 2 SiO 2 K. Mistry, et al., p.247, IEDM 2007, (Intel) T.C. Chen, et al., p.8, VLSI 2009, (IBM) T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.) K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.) Si 22nm EOT:0.9nm 15nm, 11nm, 8nm, 5nm, 3nm, Technology for direct contact of high-k and Si is necessary MG La-silicate Si EOT=0.52 nm Remote SiO 2 -IL scavenging HfO 2 (IBM) EOT=0.37nm EOT=0.40nm EOT=0.48nm nm Increase of I d at 30% Direct contact with La-silicate (Tokyo.Tech) 46

47 High-k is very important, however very difficult. Thickness (EOT) decreased only 0.05 nm (or 0.5 Å, or 1 atom layer) for every generation. 47

48 How far can we go for production? Rather than Ioff value, Ion/Ioff ratio is important. Now, Ion/Ioff ratio is typically However, it degrades significantly with decrease in Vsupply. 48

49 I OFF [na/mm] I ON and I OFF benchmark I OFF [na/mm] IBM [5] GAA NW V DD =1V 1 NMOS IBM [j] ETSOI V DD =0.9V I eff Toshiba [d] Tri-Gate NW V DD =1V Intel [a] Bulk 32nm V DD =0.8V Samsung [c] Bulk 20nm V DD =0.9V Intel [a] Tri-Gate 22nm V DD =0.8V IBM [g] ETSOI V DD =0.9V IBM [g] FinFET 25nm V DD =1V STMicro. [h] GAA NW V DD =0.9V Intel [b] Bulk 45nm V DD =1V Tokyo Tech. [i] W-gate NW V DD =1V IBM [g] ETSOI V DD =1V STMicro. [h] GAA NW V DD =1.1V I ON [ma/mm] IBM [j] ETSOI V DD =0.9V I eff Intel [a] Bulk 32nm V DD =0.8V Samsung [c] Bulk 20nm V DD =0.9V IBM [g] ETSOI V DD =0.9V Intel [b] Bulk 45nm V DD =1V IBM [f] FinFET 25nm V DD =1V IBM [e] GAA NW V DD =1V PMOS Intel [a] Tri-Gate 22nm V DD =0.8V IBM [g] ETSOI V DD =1V STMicro. [h] GAA NW V DD =1.1V I ON [ma/mm] [a] C. Auth et al., pp.131, VLSI2012 (Intel). [f] T. Yamashita et al., pp.14, VLSI2011 (IBM). [b] K. Mistry et al., pp.247, IEDM2007 (Intel). [g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM). [c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung). [h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics). [d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba). [i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.) [e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM). [j] K. Cheng et al., pp.419, IEDM2012 (IBM)

50 Nanowire/Tri gate MOSFETs have advantage not only suppressing Ioff, but also for increasing Ion over planer MOSFETs 1. Because of higher mobility due to lower vertical electric field 2. Because of higher carrier density at the round corner 50

51 51

52 Electron Density 電子濃度 (x10 19 cm -3 ) 6 6.E E E E E E E+00 角の部分 Edge portion Flat portion 平らな部分 Distance from SiNW Surface (nm) 52

53 3. Now Problems for downsizing! We have to decrease Si layer thickness to better control of channel potential by gate bias when we decrease the gate length. Significant decrease in conduction or Ion. 53

54 ITRS 2013 Year Commercial name (nm) T Si (nm) (T Si (nm) for ITRS 2007) (6.0) (6.0) (4.5) (3.8) (3.2) (3.0 in 2022) EOT (nm) (EOT (nm) for ITRS 2007) (0.60) (0.60) (0.55) (0.50) (0.50)(0.50 in 2022)

55 Short-channel effect T. Skotnicki, IEDM 2009 Short Course (STMicroelectronics) 55

56 Mobility degradation for small diameter nanowire FETs, because channel carriers become too close to all surrounding nanowire surface, and scattered strongly. 56

57 Problems in Multi-gate S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI) Need to decrease diameter for SCH Significant m degradation at diameter < 10 nm Decreasing the diameter of NW Improved short-channel control Severe mobility degradation 57

58 Problems in SOI K. Uchida et al., pp.47, IEDM2002 (Toshiba) Mobility is also decreased with decreasing the Si thickness of SOI transistor similar to the NW transistor. 58

59 Problem for nanowire When wire diameter becomes less than 10 nm, sudden drop of Id < 10 nm 1. Mobility degradation Extremely small distance between the electron and all around Si surface. Strong scattering of electrons by interaction with all around Si surface. Id Diameter 2. Electron density decrease Decrease of DOS in extremely narrow wire. 10 nm If diameter cannot be scaled, SCE cannot be suppressed. Then, again aggressive EOT scaling of high-k is necessary. 59

60 Carrier density degradation for small diameter nanowire FET, because of the decrease in density of states. 60

61 Number of quantum channels By Prof. Shiraishi of Tsukuba univ. 4 channels can be used Eg Eg Energy band of Bulk Si Energy band of 3 x 3 Si wire 61

62 Diameter dependence 1 nm 2 nm 3 nm 4 nm 6 nm By Profs. Oshiyama and Iwata, U. of Tokyo 62

63 Body Thickness [nm] EOT Scaling Trends K. Kim, pp.1, IEDM2010 (Samsung) ITRS2011 Fin width EOT [nm] Planar Multi- Gate Year Smaller wire/fin width is necessary for SCE suppression 0 But mobility and I ON severely degrade with wire/fin width reduction Therefore even in multi-gate structures, EOT scaling should be accelerated to provide SCE immunity 63

64 New Materials! High-k beyond 0.5 nm 64

65 Solution To use high-k dielectrics Thin SiO 2 K: Dielectric Constant Thick high-k dielectrics K=4 SiO 2 High-k Almost the same electric characteristics K=20 5 times thicker Small leakage Current 65 However, very difficult and big challenge!

66 H 1 Li Be 2 1 Gas or liquid at 1000 K Radio active He B C N O F Ne Na Mg Al Si P S Cl Ar 1 Ca K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra Rf Ha Sg Ns Hs Mt Candidates Unstable at Si interface 3 Choice of High-k elements for oxide Si + MO X M + SiO 2 Si + MO X MSi X + SiO 2 Si + MO X M + MSi X O Y La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res (1996) HfO 2 based dielectrics are selected as the first generation materials, because of their merit in 1) band-offset, 2) dielectric constant 3) thermal stability La 2 O 3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer 66

67 Conduction band offset vs. Dielectric Constant Leakage Current by Tunneling Band offset Si Oxide SiO 2 Band Discontinuity [ev] Dielectric Constant XPS measurement by Prof. T. Hattori, INFOS

68 Direct high-k/si by silicate reaction HfO 2 case La 2 O 3 case Our approach Low P O2 High P O2 Low P O2 High P O2 V O HfSi x V O I O I O V O HfO 2 V O Si substrate I O I O SiO 2 -IL (k~4) V O V O LaSi x V O I I La O I O 2 O 3 O silicate La-rich Si substrate Si-rich SiO 2 -IL (k~4) Direct contact can be achieved with La 2 O 3 by forming silicate at interface Control of oxygen partial pressure is the key for processing. P O2 : Partial pressure of O 2 during high temperature annealing K. Kakushima, et al., VLSI2010, p.69

69 SiO x -IL growth at HfO 2 /Si Interface TEM image500 o C 30min Intensity (a.u) o C Hf Silicate SiO 2 Si sub Binding energy (ev) Phase separator XPS Si1s spectrum nm W HfO 2 SiO x -IL k=16 k=4 HfO 2 + Si + O 2 HfO 2 + Si + 2O* HfO 2 +SiO 2 H. Shimizu, JJAP, 44, pp Oxygen supplied from W gate electrode D.J.Lichtenwalner, Tans. ECS 11, 319 SiO x -IL is formed after annealing Oxygen control is required for optimizing the reaction

70 La-Silicate Reaction at La 2 O 3 /Si Direct contact high-k/si is possible Intensity (a.u) XPS Si1s spectra TEM image 500 o C, 30 min as depo. La-silicate Si sub. 300 o C W La 2 O 3 La-silicate k=23 k=8~ o C 1 nm Binding energy (ev) 1837 La 2 O 3 + Si + no 2 La 2 SiO 5, La 2 Si 2 O 7, La 9.33 Si 6 O 26, La 10 (SiO 4 ) 6 O 3, etc. La 2 O 3 can achieve direct contact of high-k/si

71 Physical mechanisms for small Dit 1 silicate-reaction-formed fresh interface 2 stress relaxation at interface by glass type structure of La silicate. metal La 2 O 3 Si Si sub. Si metal La-silicate Si sub. La atom La-O-Si bonding Si sub. SiO 4 tetrahedron network Fresh interface with silicate reaction FGA800 o C is necessary to reduce the interfacial stress J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p S. D. Kosowsky, et al., Appl. Phys. 71Lett., Vol. 70, No. 23, (1997) pp. 3119

72 Capacitance [mf/cm 2 ] However, high-temperature anneal is necessary for the good interfacial property FGA500 o C 30min FGA700 o C 30min FGA800 o C 30min x 20mm kHz 100kHz 1MHz Capacitance [mf/cm 2 ] x 20mm 2 10kHz 100kHz 1MHz Capacitance [mf/cm 2 ] x 20mm 2 10kHz 100kHz 1MHz Gate Voltage [V] Gate Voltage [V] Gate Voltage [V] A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800 o C) 72

73 5m Cluster tool for HKMG Stack EB Deposition for HK Flash Lamp Sputter for MG Robot Entrance 5m RTA ALD 73

74 Cluster Chambers for HKMG Gate Stack Sputter: MG EB Deposition: HK Flash Lamp Anneal ALD: HK Entrance Robot RTA 74

75 Precursor (ligand) La C 3 H 7 ALD of La2O3 K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16 th Workshop on Gate Stack Technology and Physics., 2011, p La N N C 3 H 7 C C 3 H 7 H La(iPrCp)3 La(FAMD)3 La ligand O H 1 cycle substrate substrate substrate substrate 75 1La gas feed 2Ar purge 3H 2 O feed 4Ar purge ALD is indispensable from the manufacturing viewpoint - precise control of film thickness and good uniformity

76 ~ EOT (nm) As depo TiN(45nm)/W(6nm) Annealed for 2 s La 2 O 3 (3.5 nm) W(60 nm) TiN/W(6 nm) TiN/W(12 nm) Annealing temperature ( o C) Cg (uf/cm 2 ) Experiment Theory Cvc fitting TaN/(45nm)/W(3nm) 900 o C, 30min EOT=0.55nm EOT=0.55nm Vg (V) 76

77 Flat-band voltage(v) TaN(45nm)/W(3nm) Q fix = cm o C, 30min EOT(nm) Fixed Charge density: cm -2 77

78 Drain Current (ma) Our Work at TIT: High-k Electron Mobility [cm 2 /Vsec] Our result at TIT EOT=0.40nm 140 L/W = 5/20mm T = 300K N sub = cm -3 Vg= 1.0V Vg= 0.8V Vg= 0.6V Vg= 0.4V Vg= 0.2V Vg= 0 V Drain Voltage (V) EOT = 0.40nm L/W = 5/20mm T = 300K N sub = cm E eff [MV/cm] 78

79 J g at 1 V (A/cm 2 ) Benchmark of La-silicate dielectrics Mobility (cm 2 /Vsec) Gate Leakage current Effective Mobility 1.E+04 1.E+03 ITRS requirement at 1 MV/cm Solid circle: Our data 1.E La-silicate gate oxide 1.E E E-01 Our data: La-silicate gate oxide 50 Open square : Hf-based oxides 1.E EOT (nm) T. Ando, et al., (IBM) IEDM 2009, p EOT (nm) L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp ,

80 Issues in high-k/metal gate stack Oxygen concentration control for prevention of EOT increase and oxygen vacancy formation in high-k Flat metal/high-k interface for better mobility Suppression of metal diffusion Suppression of oxygen vacancy formation Small interfacial state density at high-k/si Control of interface reaction and Si diffusion to high-k 80 Suppression of gate leakage current Endurance for high temperature process Metal High-k Si-sub. O SiO 2 -IL Reliability: PBTI, NBTI, TDDB Oxygen diffusion control for prevention of EOT increase and oxygen vacancy formation in high-k Workfunction engineering for V th control Suppression of FLP Interface dipole control for V th tuning Remove contamination introduced by CVD Thinning or removal of SiO 2 -IL for small EOT

81 Thank you very much for your attention. 81

82 Appendix 82

83 What is Next Revolution for Device Technology? 1900: Electronics 83

84 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics 84

85 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics When?: What? 85

86 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics?: Nano Electronics 86

87 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics?: Nano Electronics Maybe Not a Revolution But Great Innovention 87

88 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics When?: What? 88

89 What is Next Revolution for Device Technology? 1900: Electronics 1970: Micro Electronics? years When?: What? 89

90 What is Next Revolution for Device Technology? 1900: Electronics 70 years 1970: Micro Electronics? years When?: What? 90

91 What is Next Revolution for Device Technology? 1900: Electronics 70 years 1970: Micro Electronics 70 years When?: What? 91

92 What is Next Revolution for Device Technology? 1900: Electronics 70 years 1970: Micro Electronics 70 years 2040: Braintronics 92

93 Braintronics We do know system and algorithms are important! But do not know how it can be by us for use of bio? 93

94 Long term roadmap for development Source: H. Iwai, IPFA 2006 New Materials, New Process, New Structure Hybrid integration of different functional Chip Increase of SOC functionality ize 3D integration of memory cell 3D integration of logic devices Saturation of Downsizing Miniaturization of Interconnects on PCB (Printed Circuit Board) Low cost for LSI process Revolution for CR, Equipment Introduction of algorithm of biosystem Brain of insects, human Braintronics We do not know how? Some time in After 2040? 94

95 Braintronics for 2040 s It s a task for you, For young generations! 95