FAN108M6X. Offline Primary-Side-Regulation (PSR) Quasi-Resonant Valley Switch Controller PXXAX

Transcription

1 FAN08M6X Offline Primary-Side-Regulaion (PSR) Quasi-Resonan Valley Swich Conroller FAN08 is offline Primary Side Regulaion (PSR) PWM conroller wih Quasi Resonan (QR) mode conroller o achieved consan volage (CV) and consan curren (CC) conrol for Travel Adapor (TA) requiremen and provide cos effecive, simplified circui for energy efficien power supplies. FAN08 is designed o have good energy efficiency echnology ha offers opions o users o mee differen power consumpion arges using differen sarup componens. FAN08 can be used in Travel Adaper design by sand alone or co work wih secondary side SR conroller FAN6250/FAN625. While pairing wih FAN6292C, FAN08 can be used o design a high densiy Type C ravel adaper in compac sysem BOM. Feaures Ulra Low Sandby Power Consumpion Feasible: < 30 mw hrough HV FET and < 75 mw hrough HV Resisor Consan Curren (CC) and Consan Volage(CV) wih Primary Side Regulaion Eliminaes Secondary Side Feedback Componen Valley Swich Operaion for Highes Average Efficiency Dynamic Response Enhancemen (DRE) Funcion for Excellen Dynamic Response wihou he Need of OPTO Low EMI Emissions and Common Mode Noise Programmable Brown In and Brown Ou Proecion Oupu Over Volage Proecion (OVP) Oupu Under Volage Proecion (UVP) Capure Secondary Side Shu Down Signal from he Proprieary Channel beween FAN08 and FAN6250 o Perform Real Sysem Proecion Secondary Side Recifier Shor Deecion via Curren Sense Proecion(CSP) Cycle by Cycle Curren Limiing Typical Applicaions Travel Adaper for Smar Phones, Feaure Phones, and Table PCs AC DC Adapers for Porable Devices or Baery Chargers ha Require CV/CC Conrol. PXX AX CS GND SOT23 CASE 527AJ MARKING DIAGRAM PXXAX = Year Code = 08 : FAN08M6X = Die Run Code = Week Code PIN CONNECTIONS AUX VDD ORDERING INFORMATION See deailed ordering and shipping informaion on page 8 of his daa shee. Semiconducor Componens Indusries, LLC, 208 Sepember, 208 Rev. Publicaion Order Number: FAN08M6X/D

2 FAN08M6X L F TX Fuse Bridge Choke C BLK C BLK2 C SNP R SNP N P R N SNS S C SNS C OUT V O AC IN XC R HV R SNP R D SNP GND R D DRAIN VIN VDD SD FAN6250 R U D AUX C VDD VDD AUX GND R GR R GF D G NTC R SD R L C CS FAN08 C CSF R CS_COMP R CS Figure. FAN08 Typical Applicaion Schemaic L F TX Fuse Bridge Choke C BLK C BLK2 C SNP R SNP N P R N SNS S C SNS C OUT V O AC IN XC R SNP R D SNP GND R HV DRAIN VIN VDD SD FAN6250 R U D AUX C VDD VDD AUX GND R GR R GF D G NTC R SD R L C CS FAN08 C CSF R CS_COMP R CS Figure 2. FAN08 Typical Applicaion Schemaic 2

3 FAN08M6X AUX 6 Brown IN/OUT V N VDD UVLO 7.5V/6.5V VDD UVLO DRE Deecion Auo Resar Proecion V DD OVP Faul V S UVP Faul V S OVP Faul OTP Faul V CS Faul VDD 4 V VDD OVP Debounce VDD OVP Faul Maximum On Time VDD 5 Valley Deecion V D V N DIS Frequency Hopping FB CV OSC D Q CLK C Q Driver Conrol 3 S/H S/H = Sampling and Hold V CS Peak Curren FB CV Hi Z Mode Conrol V S SH 2.5V COMV Compensaor FB CV AV CV V CS Faul CS Proecion V CS LIM 5V 2 GND Cable Drop Compensaion Proecion V S OVP Faul V S UVP Faul AV CC V CS FB CC IO Esimaor V CS DIS LEB I COMP CS Figure 3. FAN08 Block Diagram PIN FUNCTION DESCRIPTION Pin No. Name Descripion CS Curren Sense. This pin connecs o a curren sense resisor o deec he MOSFET curren for Peak Curren Mode conrol for oupu regulaion. The curren sense informaion is also used o esimae he oupu curren for CC regulaion 2 GND Ground. 3 PWM Signal Oupu. This pin has an inernal oem pole oupu driver o drive he power MOS- FET. The gae driving volage is inernally clamped a 7.5 V 4 VDD Power Supply. IC operaing curren and MOSFET driving curren are supplied hrough his pin. This pin is ypically conneced o an exernal VDD capacior 5 Volage Sense. The volage is used o deec resonan valleys for quasi resonan swiching. This pin deecs he oupu volage informaion and diode curren discharge ime based on he auxiliary winding volage. I also senses inpu volage for Brown IN/OUT proecion 6 AUX Auxiliary Funcion. The pin is used for sarup wih exernal depleion HV FET 3

4 FAN08M6X MAXIMUM RATINGS Parameer Symbol Value Uni DC Supply Volage V VDD 30 V Maximum Volage on Pin V GETE 0.3 o 30 V Maximum Volage on Low Power Pins (Excep Pin 3, Pin 4, Pin 6) V max 0.3 o 6 V Power Dissipaion (T A = 25 C) P D mw Thermal Resisance (Juncion o Ambien) JA 28.5 C/W Thermal Resisance (Juncion o Top) JT 33. C/W Operaing Juncion Temperaure T J 40 o +25 C Sorage Temperaure Range T STG 40 o +25 C Elecrosaic Discharge Capabiliy Human Body Model, JEDEC:JESD22_A4 Charged Device Model, JEDEC:JESD22_C0 Sresses exceeding hose lised in he Maximum Raings able may damage he device. If any of hese limis are exceeded, device funcionaliy should no be assumed, damage may occur and reliabiliy may be affeced.. All volage values, excep differenial volages, are given wih respec o GND pin. 2. Sresses beyond hose lised under Maximum Raings may cause permanen damage o he device. 3. Mees JEDEC sandards JS and JESD 22 C0. ESD kv RECOMMENDED OPERATING RANGES Parameer Symbol Min Max Uni VDD Pin Supply Volage V VDD 6 25 V Pin Supply Volage V V CS Pin Supply Volage V CS V AUX Pin Supply Volage V AUX 0 V DD 5V V Operaing Temperaure T A C 4. The Recommended Operaing Condiions able defines he condiions for acual device operaion. Recommended operaing condiions are specified o ensure opimal performance. ON Semiconducor does no recommend exceeding hem or designing o Maximum Raings. ELECTRICAL CHARACTERISTICS For ypical values T J = 25 C, for min/max values T J = 40 C o 25 C, V DD = 2 V; unless oherwise noed. Parameer Tes Condiions Symbol Min Typ Max Uni VDD SECTION Turn On Threshold Volage V DD Rising V DD ON V Turn Off Threshold Volage V DD Falling V DD OFF V Sarup Curren V DD = V DD ON 0.6 V I DD ST 20 A Operaing Supply Curren I DD OP.2 ma Deep Green Mode Operaing Supply Curren I DD DPGN 460 A V DD Over Volage Proecion Level V VDD OVP V V DD Over Volage Proecion Debounce Time D VDDOVP s OSCILLATOR SECTION Maximum Blanking Frequency f BNK MAX khz Minimum Blanking Frequency f BNK MIN khz Maximum DCM Operaion Frequency f OSC DCM MAX khz 4

5 FAN08M6X ELECTRICAL CHARACTERISTICS For ypical values T J = 25 C, for min/max values T J = 40 C o 25 C, V DD = 2 V; unless oherwise noed. Parameer Tes Condiions Symbol Min Typ Max Uni OSCILLATOR SECTION Minimum DCM Operaion Frequency f OSC DCM MIN khz Minimum Frequency for CCM Prevenion f OSC CCM khz Frequency Hopping Range f Hopping khz Frequency Hopping Period Hopping ms AUX SECTION Clamping Volage beween VDD and AUX pin V DD = V DD ON V CLAMP 5 V CURRENT SENSE SECTION Curren Limi Threshold Volage V CS LIM V High Threshold Volage of Curren Sense V CS IMIN V Oupu Turn Off Delay (Noe 5) PD 00 ns Leading Edge Blanking Time LEB ns CONSTANT CURRENT ESTIMATOR SECTION Reference Volage of Consan Curren V VR CC V Peak Value Amplifying Gain (Noe 5) A PK 3.6 V/V CONSTANT CURRENT CORRECTION SECTION High Line Compensaion Curren V IN = 264 V rms I COMP H A Low Line Compensaion Curren V IN = 90 V rms I COMP L A Inernal Line Volage Compensaion Resisance (Noe 5) R COMP LINE 575 CABLE DROP COMPENSATION SECTION Cable Drop Compensaion Volage V CDC mv OVER TEMPERATURE PROTECTION SECTION Threshold Temperaure for Over Temperaure Proecion (Noe 5) T OTP H 30 C Threshold Temperaure for Over Temperaure Proecion (Noe 5) T OTP L 0 C VOLTAGE SENSE SECTION Reference Volage of Consan Volage V VR CV V Sampling Blanking Time L T J = 25 C BNK L..3.5 s Sampling Blanking Time H T J = 25 C BNK H s Source Curren Threshold o Enable Brown OUT Se V IN = 264 VAC (373 VDC) N P :N S :N A = 54:8:4, R U = 27.4 k I Brown OUT A Brown OUT Debounce Time D Brown OUT ms Source Curren Threshold o Enable Brown IN Se V IN = 264 VAC (373 VDC) N P :N S :N A =54:8:4, R U = 27.4 k I Brown IN A Brown IN Debounce Time N Brown IN 4 Pulse Oupu Over Volage Proecion wih Vs Sampling Volage V OVP V Oupu Over Volage Proecion Debounce Pulse Couns Oupu Under Volage Proecion wih Vs Sampling Volage N OVP 4 Pulse V UVP L V 5

6 FAN08M6X ELECTRICAL CHARACTERISTICS For ypical values T J = 25 C, for min/max values T J = 40 C o 25 C, V DD = 2 V; unless oherwise noed. Parameer Tes Condiions Symbol Min Typ Max Uni VOLTAGE SENSE SECTION Oupu Under Volage Proecion Debounce Pulse Couns Oupu Under Volage Proecion Blanking Time a sar up N UVP 4 Pulse UVP BLANK ms DYNAMIC RESPONSE ENHANCEMENT Dynamic Even Enable Threshold Volage T J = 25 C V EAV DYN EN V Dynamic Even Disable Threshold Volage V EAV DYN DIS V Hi Z Mode Enable Time HIZ EN s Hi Z Mode Clamping Volage V CLMP HIZ V SECTION Gae Oupu Volage Low V L 0.5 V Inernal Gae PMOS Driver ON V DD PMOS ON V Inernal Gae PMOS Driver OFF V DD PMOS OFF V Rising Time r ns Falling Time f ns Gae Oupu Clamping Volage V CLAMP V Maximum On Time ON MAX 5 22 s 5. Design guaraneed. 6

7 FAN08M6X TYPICAL CHARACTERISTICS Figure 4. Turn On Threshold Volage (V DD ON ) vs. Temperaure Figure 5. Turn Off Threshold Volage (V DD OFF ) vs. Temperaure Figure 6. Source Curren Threshold o Enabled Brown IN (I Brown IN ) vs. Temperaure Figure 7. Source Curren Threshold o Enabled Brown OUT (I Brown OUT ) vs. Temperaure Figure 8. Maximum Blanking Frequency (f BNK MAX ) vs. Temperaure Figure 9. Minimum Blanking Frequency (f BNK MIN ) vs. Temperaure 7

8 FAN08M6X TYPICAL CHARACTERISTICS (coninued) Figure 0. Reference Volage of Consan Volage (V VR CV ) vs. Temperaure Figure. Reference Volage of Consan Curren (V VR CC ) vs. Temperaure Figure 2. Sampling Blanking Time L ( -BNK L ) vs. Temperaure Figure 3. Figure 4 Sampling Blanking Time H ( BNK H ) vs. Temperaure Figure 5. Oupu Over Volage-Proecion (V OVP ) vs. Temperaure Figure 6. Oupu Under-Volage Proecion (V UVP ) vs. Temperaure 8

9 FAN08M6X TYPICAL CHARACTERISTICS (coninued) Figure 7. Curren Limi Threshold Volage (V CS-LIM ) vs. Temperaure Figure 8. Figure 9 High Threshold Volage of Curren Sense (V CS-IMIN ) vs. Temperaure Figure 20. V DD Over Volage Proecion Level (V VDD OVP ) vs. Temperaure Figure 2. Cable Drop Compensaion Volage ( V CDC ) vs. Temperaure Figure 22. Leading Edge Blanking Time ( LEB ) vs. Temperaure Figure 23. Maximum On Time ( ON MAX ) vs. Temperaure 9

10 FAN08M6X APPLICATIONS INFORMATION FAN08 is a flyback power supply conroller providing a means o implemen primary side consan volage (CV) and consan curren (CC) regulaion. This echnique can simplify feedback circui and secondary side circui compare o radiional flyback converer. FAN08 implemens a curren mode archiecure operaion in quasi resonan mode. The quasi resonan mode operaion is able o minimize he swiching loss o opimize he power supply efficiency and ge beer EMI performance. FAN08 quasi resonance operaion in peak curren mode conrol is monior he auxiliary winding volage on primary side via he resisor divider o volage sense pin () and curren sense pin (CS). Exremely accuraely consan volage (CV) mode and consan curren (CC) mode could mee sric requiremen from marke. V O NOM V O CV Mode 0 I O CC NOM Figure 24. CV and CC Mode CC Mode I O FAN08 implemens deep green mode (DPGN) wih lowes swiching frequency, limis IC curren consumpion (460 A) for excellen sysem sandby power performance. Furhermore, he sysem design allows wo kinds of sarup circui one is wih sarup resisor he oher is wih high volage FET. Proecions such as over volage proecion ( OVP), under volage proecion ( UVP), inernal over emperaure proecion (OTP), brown in and brown ou proecion, cycle by cycle curren limi, curren sense resisor shor proecion and secondary recifier shor proecion. Sarup Operaion FAN08 suppors high volage sar up wih depleion FET ha can make beer sandby power and shorer sar up ime. Figure 23 shows sarup sequence wih AUX conrolling. The iniial AUX pin saus should be defined by resisor of R D. A sysem power on momen, he iniial V DD volage is zero, inernal swich S is urn on and exernal depleion FET also is urn on, he C VDD is charged hrough depleion FET ill V DD reach V DD ON. While inernal swich Sis urn off and V GS of depleion FET will close o inernal clamping volage (V CLAMP ) which less han depleion FET V GS urn on hreshold. Meanwhile V DD energy supplemen is urn o auxiliary winding. The volage gap beween V DD and V AUX is kep a V CLAMP ill conroller shu down by proecion or V DD ouching V DD OFF. Bridge AC IN C BLK R HV Depleion NMOS (Normal ON) V DD ON R D V DD FAN08 V CLAMP V AUX V DD OFF D AUX VDD 4 S 6 AUX V DD V AUX = V CLAMP = 5V R U C VDD UVLO V DD ON / V DD OFF R L Figure 25. Sarup Sequence wih AUX Conrolling 0

11 FAN08M6X Primary Side Regulaion: Consan Volage Operaion As illusraed by Figure 26, he volage of auxiliary winding (V WAUX ) is refleced o oupu volage scaled by he auxiliary and secondary urns raio minus he drain volage of synchronous recifier (SR) FET. To reach an accurae primary side consan volage regulaion, he conroller deecs he end of he demagneizaion ime and precisely sample oupu volage level seen on he auxiliary winding. Therefore, when he secondary curren I SEC reaches zero ampere, he volage of auxiliary winding is sensed as V WAUX V O N s (eq. ) where and N S are respecively he urns of secondary and auxiliary. Figure 27 shows how he consan volage feedback has been buil. The auxiliary winding volage mus be scaled down via he resisor divider o V VR CV level before building he consan volage feedback error. R L V VR CV V R U R WAUX (eq. 2) L By insering Equaion ino Equaion 2 we obain he following equaion: R L V VR CV V R U R O L N (eq. 3) s A blanking ime ( BNK ) sar from primary swich urned off. Mos of TA design has oscillaion afer primary swich urned off ha is caused by he resonance of leakage inducance and parasiic capaciance a ransformer. In order o avoid sampling procedure ge impaced by ha ringing, afer BNK he oscillaion should be seled down. Figure 27 shows feedback signal sampling iming, afer he blanking ime, he conroller samples he pin volage as V SD. Once is lower han he hreshold volage of V TDIS ( 200 mv), he V SD signal will be held as V S SH. N p N S V O V WAUX() V WAUX () [V o I SEC () r DS(ON) N S C SNP R SNP I PRI I SEC C OUT SR FET V O 0V ime V Drain R SNP D SNP I SEC V Drain I PRI() V WAUX V O R U SR FET ON I SEC() ime R L C R CS on demag SW ime Figure 26. Typical Idealized Waveforms of a Flyback Transformer in DCM V SD V S SH V TDIS = V S 200mV C R U R L Low Pass Filer S/H V S SH V VR CV G M CV COMV TBNKB ime ime Compensaor SP ime HOLD BNK ime Figure 27. Consan Volage Feedback Circui and signal Sampling Timing

12 FAN08M6X Primary Side Regulaion: Consan Curren Operaion Figure 28 shows he key waveforms of a flyback converer operaion in DCM. The oupu curren (I O ) is esimaed by calculaing he average of secondary curren (I SEC ) in one swiching cycle. The oupu curren (I O ) can be calculaed as I O V CS PK T DIS N p V VR CC N p (eq. 4) 2 R CS T SW N S 2 R CS A PK N S When he secondary curren reaches zero, he ransformer winding volage begins o drop sharply, and pin volage drops as well. When pin volage drops below he V S by more han 200 mv, zero curren poin of secondary curren is obained. The oupu curren can be programmed by seing he curren sensing resisor as: R CS 2 V VR CC N P (eq. 5) I O A PK N S where V VR-CC is he inernal volage for consan curren conrol, η is efficiency of flyback and A PK is he IC design parameer, 3.6 for FAN08. BNK VTDIS = 200mV Defined he Zero Curren VCS S/H Averaging Circui VCS PK VCS PKAPK IO_ESTM APK VVR CC GM CC COMI ime Compensaor VCS PK ISEC VCS PK VCS PKAPK ime VVR CC IO_ESTM TDIS TQR TON ime TSW Figure 28. Consan Curren Feedback Circui and Conrol Sequence Line Volage Compensaion The oupu curren esimaion is also affeced by he urn off delay of he power FET as shown in Figure 29. The acual power FET s urn off ime is delayed due o he FET gae charge and gae driver s capabiliy, resuling in peak curren deecion error as I PK DS V BLK L m OFF,FLY (eq. 6) where L m is he ransformer s primary side magneizing inducance and V BLK is bulk volage. Since he oupu curren error is proporional o he line volage, he FAN08 incorporaes line volage compensaion o improve oupu curren esimaion accuracy. I DSR CS OFF.DLY I Lm R CS I PK DS R CS Acual secondary curren Esimaed secondary curren Line informaion is obained hrough he line volage deecor as shown in Figure 3. I COMP is an inernal curren source which is proporional o line volage. The line compensaion gain is programmed by using CS pin series resisor, R CS_COMP, depending on he power FET urn off delay ( OFF.DLY ). I COMP creaes a volage drop (V OFFSET ) across R CS_COMP. This line compensaion offse is proporional o he DC link capacior volage (V BLK ) and urn off delay ( OFF.DLY ). Figure 30 demonsraes he effec of he line compensaion. I DSR CS I COMP CS CCSF < 20pF V CS OFF.DLY V OFFSET + R CS_COMP I DS R CS V GS I DSR CS I DS R CS OFF.DLY I DSR CS ime COMI V GS T DIS Figure 29. MOSFET Turn-off Delay V GS V CS V CS V OFFSET H V OFFSET L ime Low Line High Line ime Figure 30. Line Volage Compensaion 2

13 FAN08M6X CV / CC PWM Conrol Principle Figure 3 shows a simplified CV / CC PWM conrol circui of he FAN08. The Consan Volage (CV) regulaion is implemened inernally wih primary side conrol. The oupu signal of compensaion (COMV) is scaled down by aenuaor A V CV o generae a V FB CV signal. This V FB CV signal is applied o he PWM comparaor o deermine he duy cycle. The Consan Curren (CC) regulaion is implemened inernally wih primary side conrol. The oupu curren esimaor calculaes he oupu curren using he ransformer primary side curren and secondary curren discharge ime (T DIS ). By comparing he esimaed oupu curren wih inernal reference signal, a COMI signal is generaed. The COMI signal is scaled down by aenuaor A V CC o generae a V FB CC signal. This V FB CC signal is applied o he PWM comparaor o deermine he duy cycle. These wo conrol signals, V FB CV and V FB CC are compared wih a volage of curren sense (V CS ) by wo PWM comparaors o deermine he duy cycle. Figure 3 illusraes he oupus of wo comparaors combined wih an OR gae, o deermine he power FET urn off insan. Eiher of V FB CV or V FB CC, he lower signal deermines he duy cycle. During CV regulaion, V FB CV deermines he duy cycle while V FB CC is sauraed o HIGH level. During CC regulaion, V FB CC deermines he duy cycle while V FB CV is sauraed o HIGH level. Blanking Time ON TRIG V FB CV PWM Conrol Logic Block OFF TRIG V BLK N P N S V o V FB CC V FB CV CV CC V CS V CS V FB CC I COMP CS A V CV A V CC COMV COMI Line Volage Deecor V WAUX 0V CV CC V WAUX V WAUX = V BLK (/N P) Sampling Valley Deecor Zero Curren Deecor I R U R L Figure 3. Simplified PSR Flyback Converer Circui Valley Deecion and Frequency Fold back The quasi resonan (QR) swiching is a mehod o reduce primary side swiching losses. To perform QR urn on of he power FET, he valley of he resonance occurring beween ransformer magneizing inducance (L m ) and effecive oupu capaciance (C oss eff ) mus be deeced. The resonan period is deeced by monioring he ime of /4 resonan period from end of secondary curren discharge ime (T DIS ) o signal reaches zero. FAN08 will urn on he power FET a /2 resonan period afer he blanking frequency as shown in Figure 32. For heavy load condiion, he blanking ime for he valley deecion is fixed and primary side peak curren will be modulaed by volage level of feedback (V FB CV ). For he medium load condiion, he blanking ime is modulaed as a funcion of load curren such ha he upper limi of he blanking frequency varies from f BNK MAX as load decreases where he blanking frequency reducion sop poin is f BNK MIN. For he ligh load condiion, he peak of V CS is fixed by V CS IMIN (0.75 V) and he energy will be modulaed by he funcion of Pulse Frequency Modulaion (PFM), as shown in Figure 3. 0V I SEC V WAUX QR /4 T ON T DIS Figure 32. Valley Deecion Zero Crossing Deec QR /2 QR 3

14 FAN08M6X V FB CV V CS V CS IMIN BNK MAX BNK BNK V DS f =/ BNK MIN EXT BNK EXT BNK EXT f BNK MIN = / BNK MAX Fixed Blanking Time Modulaed Blanking Time Fixed Blanking Time PFM Figure 33. Frequency Fold back Funcion Cable Drop Compensaion (CDC) FAN08 inegraes cable drop compensaion funcion; his circuiry compensaes he drop due o he cable conneced beween he PCB oupu of he charger and he final equipmen. As he drop is linearly varying wih he oupu curren level, his level can be compensaed by accouning for he load oupu curren. The weighing of CDC provides a consan oupu volage a he end of he cable over he enire load range in CV mode. The volage of cable drop compensaion a oupu is proporional o compensaion weighing ha is inernal reference volage wih CDC compensaion as V O N S R U I R L O V VR CV V CDC I O CC NOM V VR CV + V CDC V VR CV V CV Mode (eq. 7) V CDC =60mV operaing curren I DD OP (.2 ma). When VDD drops o he VDD urn off volage V DD OFF (6.5 V), operaion curren reduces o I DD ST (20 A) and he proecion is rese and he supply curren drawn from bulk capacior begins o charge he VDD hold up capacior. When VDD reaches he urn on volage V DD ON (7.5 V), he FAN08 resumes normal operaion. In his manner, he Auo Resar mode alernaely enables and disables he swiching of he power FET unil he abnormal condiion is eliminaed as shown in Figure 35. V DS V DD OVP V DD ON V DD OFF Power On Faul Occurs Faul Removed I DD OP 0 I O CC NOM Figure 34. CV CC Curve wih CDC I O I DD ST Figure 35. Auo Resar Mode Operaion Proecions The FAN08 self proecion includes VDD Over Volage Proecion (VDD OVP), Inernal Chip Over Temperaure Proecion (OTP), Over Volage Proecion ( OVP), Under Volage Proecion ( UVP), CS pin Proecion (CSP), Brown ou and Brown In proecion, and all of proecion are implemened as Auo Resar (AR) mode. When he Auo Resar Mode proecion is riggered, swiching is erminaed and he power FET remains off, causing VDD o drop because of IC VDD Over Volage Proecion (VDD OVP) VDD over volage proecion prevens IC damage from over volage sress. I is operaed in Auo Resar mode. When he VDD volage exceeds V DD OVP (28 V) for he de bounce ime, D VDDOVP (20 s), due o abnormal condiion, he proecion is riggered. This proecion is ypically caused by he auxiliary winding urns are oo many, load regulaion is no good beween ransformer winding, informaion is no available anyhow and so on. 4

15 FAN08M6X Brown In and Brown Ou Line volage informaion is used for brown ou and brown in proecion. When he I curren ou of he pin during he power FET conducion ime is less han I Brown OUT (320 A) for longer han 7 ms, he brown ou is riggered. The brown ou is se o around 20% margin of he minimum volage on he bulk capacior o allow adaper deliver maximum power under he low line full load condiion. The inpu bulk capacior volage o rigger brown ou proecion is given as V BO V BLK MIN.2 I Brown OUT R U N p (eq. 8) where V BLK.MIN is he minimum volage on he bulk capacior. For he brown in proecion, when he I curren ou of he pin during he power FET conducion ime is over han I Brown OUT (465 A) for more han 4 consecuive swiching cycles, he brown in is riggered. The inpu bulk capacior volage o rigger brown in proecion is given as V BI I Brown IN R U N p (eq. 9) Over Volage Proecion ( OVP) over volage proecion prevens damage caused by oupu over volage condiion. I is operaed in Auo Resar mode. Figure 36 shows he inernal circui of OVP proecion. When abnormal sysem condiions occur, which cause sampling volage o exceed V OVP (2.95 V) for more han de bounce cycles (N OVP ), PWM pulses are disabled and FAN08 eners Auo Resar proecion. over volage condiions are usually caused by open circui of he feedback nework or a faul condiion in he pin volage divider resisors. For pin volage divider design, R U is obained from Equaion 8 and 9 and R L is deermined by Equaion 3. V O OVP can be deermined by Equaion 0 V O OVP N s R U R L V OVP (eq. 0) Under Volage Proecion ( UVP) In he even of an oupu shor, oupu volage will drop and he primary peak curren will increase. To preven operaion for a long ime in his condiion, FAN08 incorporaes under volage proecion hrough pin. Figure 37 shows he inernal circui for UVP. By sampling he auxiliary winding volage on he pin a he end of SR FET conducion ime, he oupu volage is indirecly sensed. When sampling volage is less han V UVP (.6 V) and longer han de bounce cycles N UVP, UVP is riggered and he FAN08 eners Auo Resar Mode. To avoid UVP riggering during he sarup sequence a sarup blanking ime, UVP BLANK (40 ms), is included when sysem is power on. For pin volage divider design, R U is obained from Equaion 8, 9 and R L is deermined by Equaion 3. V O UVP can be deermined by Equaion. V R U R L V O UVP N s R U R L V UVP (eq. ) S/H Auo Resar V UVP PWM Figure 37. UVP Proecion Circui D Q UVP Debounce ime Couner Cycle by Cycle Curren Limi During sarup or overload condiion, he feedback loop is sauraed o high and is unable o conrol he primary peak curren. To limi he curren during such condiions, FAN08 has cycle by cycle curren limi proecion which forces he o urn off when he CS pin volage reaches he curren limi hreshold, V CS LIM (0.7 V). V WAUX R U R L S/H V Auo Resar PWM D Q OVP Debounce ime Couner Secondary Side Diode Sho Proecion When he secondary side diode is damaged, he slope of he primary side peak curren will be sharp wihin leading edge blanking ime. To limi he curren during such condiions, FAN08 has secondary side diode shor proecion which forces he o urn off when he CS pin volage reaches.6 V. Afer one swiching cycle, i will operae in Auo Resar mode as shown in Figure 38. Figure 36. OVP Proecion Circui 5

16 FAN08M6X Curren Sense Shor Proecion Curren sense shor proecion prevens damage caused by CS pin open or shor o ground. Afer four swiching cycle, i will operae in Auo Resar mode. Figure 38 shows he inernal circui of curren sense shor proecion. When abnormal sysem condiions occur, which cause CS pin volage lower han 0.2 V afer de bounce ime ( CS shor ) for more han 4 consecuive swiching cycles, PWM pulses are disabled and FAN08 eners Auo Resar proecion. The I CS Shor is an inernal curren source, which is proporional o line volage. The de bounce ime ( CS shor ) is creaed by I CS shor, capacior (2 pf) and hreshold volage (3.0 V). This de bounce ime ( CS shor ) is inversely proporional o he DC link capacior volage, V BLK. appears on he drain node. The FAN08 pin can receive he volage ringing via C DS and C GS, is given as V C GD V C GD C Drain (eq. 2) GS Once pin received he signal of volage ringing, FAN08 will urn on he power FET immediaely and ge oupu volage informaion via pin. If he volage of pin is lower han he hreshold of V DNY EN, he swiching frequency increases immediaely. VDD VBLK Np NS RSNS CSNS COUT VO M H IDRE R V BLK I DS R CS N P R CS_COMP C CSF CS I CS Shor 2pF 3.0V 0.2V Auo Resar CS Shor D Q PWM Couner Driver Conrol V O V DRE HiZ CGD CGS 200 kω M L Drain CDS GND DRAIN VIN VDD SD FAN6250 NTC.6V D Q I O MAX Auo Resar PWM Couner LEB 0.7V I DRE Figure 38. Curren Sense Proecion Circui Dynamic Response Enhancemen (DRE) PSR flyback converer regulaes oupu volage wihin requiremen specificaion hrough deecs signal which proporional o oupu volage, However signal can only deec when power FET is swiched. To ge beer sandby power performance, he swiching frequency is decreases o quie low frequency, he oupu volage canno be mainained as load suddenly increases from exremely ligh load o heavy load during such condiions. Therefore, FAN08 build in a Dynamic Response Enhancemen (DRE) funcion o deec oupu volage dropping immediaely when FAN08 pair wih FAN6250. Figure 39 shows DRE funcion relaive signal working sequence. In he ligh load o no load condiion, when he ime of swiching period is longer han ime HIZ EN (67 s), he Hi Z mode will be enabled which is le pin become high impedance. Therefore, he pin is changed from oupu o inpu and he signal on he pin can be received. FAN6250 VIN pin can deec he oupu volage (V O ). When V O is lower han he hreshold of V DRE, he FAN6250 drain pin will sink a curren (I DRE ) from he secondary winding o ground and his curren is via he ransformer o primary side. Because of he ransformer leakage inducance and he drain lumped capaciance, some volage ringing V S V DNY DIS V DNY EN Hi Z Mode Enabled Hi Z Mode Enabled HIZ EN HIZ EN HIZ EN Figure 39. DRE Funcion Deecing Sequence Secondary side Shu Down Inform Proecion When Shu Down funcion of FAN6250 is riggered, he SR conroller will urn off he inenionally as shown in Figure 40 and keep his saus unil VIN OFF is ouched When SR FET urns off inenionally, he secondary curren I SEC goes hrough he SR FET from source o drain diode and o generae he forward diode volage V SD ( A ) as V SD ( A ) I SEC ( A ) r D V f (eq. 3) Where r D is resisance of he diode and V f is forward volage. Usually he forward diode volage (V SD ) is around 0.7 V o.3 V. The forward diode volage (V SD ) will be refleced o pin by urns raio and divider resisor as V ( A ) (V O V SD ) R L (eq. 4) N S R U R L 6

17 FAN08M6X Afer he blanking ime ( BNK ), FAN08 samples he pin volage and plus 00 mv as V SO. During he discharge ime, once is larger han V SO and more han 5 consecuive swiching cycles, PWM pulses are disabled and FAN08 eners Auo Resar proecion. SR ISEC VDrain VO 0V TDIS O =+00mV BNK Normal OFF SR Figure 40. SR FET Normal OFF and Inenionally OFF ISEC VDrain VO 0V BNK Inenionally OFF TDIS D(A) (V O V SD ) R L N S R U R L O =+00mV = A PCB Layou Guideline Prin circui board (PCB) layou and design are very impor for swiching power supplies where he volage and curren change wih high dv/d and di/d. A good PCB layou minimizes excessive EMI and prevens he power supply from being disruped during surge/esd ess. The following guidelines are recommended for layou designs. To improve EMI performance and reduce line frequency ripples, he oupu of he bridge recifier should be conneced o capaciors C BLK and C BLK2 firs, hen o he ransformer and MOSFET The primary side high volage curren loop is C BLK2 Transformer MOSFET R CS C BLK2. The area enclosed by his curren loop should be as small as possible. The race for he conrol signal (CS, and ) should no go across his primary high volage curren loop o avoid inerference Place R HV for proecion agains he inrush spike on he drain pin of depleion FET (200 k is recommended).r CS should be conneced o he ground of C BLK2 direcly. Keep he race shor and wide (Trace 4 o ) and place i close o he CS pin o reduce swiching noise. High volage races relaed o he drain of MOSFET and RCD snubber should be away from conrol circuis o preven unnecessary inerference. If a hea sink is used for he MOSFET, connec his hea sink o ground As indicaed by 2, he area enclosed by he ransformer auxiliary winding, D AUX and C VDD, should also be small Place C VDD, C, R L, R CS_COMP and C CSF close o he conroller for good decoupling and low swiching noise As indicaed by 3, he ground of he conrol circuis should be conneced as a single poin firs, hen o oher circuiry Connec ground by 3 o 2 o 4 o sequence. This helps o avoid common impedance inerference for he sense signal Regarding he ESD discharge pah, use he shorcu pad beween AC line and DC oupu (mos recommended). Anoher mehod is o discharge he ESD energy o he AC line hrough he primary side main ground. Because ESD energy is delivered from he secondary side o he primary side hrough he ransformer sray capacior or he Y capacior, he conroller circui should no be placed on he discharge pah. 5 shows where he poin discharge roue can be placed o effecively bypass he saic elecriciy energy For he surge pah, selec fusible resisor of wire wound ype o reduce inrush curren and surge energy and use inpu filer (wo bulk capaciors and one inducance) o share he surge energy LF 5 TX RSNS CSNP DR Fuse Bridge Choke CBLK CBLK2 CSNP RSNP Np Ns CO VO AC IN XC RHV DSNP 5 CY Na RD R U DAUX 2 CVDD FAN08 VDD AUX RGR CS GND RGF DG R L C CCSF RCS_COMP RCS 3 4 Figure 4. Recommended Layou for FAN08 7

18 FAN08M6X ORDERING INFORMATION Device Operaing Temperaure Range Package Shipping FAN08M6X 40 C o +25 C 6 Lead, SOT23 Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD80/D. 8

19 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SCALE 2: SOT 23, 6 Lead CASE 527AJ ISSUE B DATE 29 FEB 202 6X E 0.0 C A e D TOP VIEW SIDE VIEW 3 A B E 6X b 0.20 M A2 A C C A S SEATING PLANE B S DETAIL A L DETAIL A END VIEW L2 GAGE PLANE SEATING PLANE c NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DATUM C IS THE SEATING PLANE. MILLIMETERS DIM MIN MAX A A A b c D E E e BSC L L BSC GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* XXX M X X 0.85 PITCH DIMENSIONS: MILLIMETERS *For addiional informaion on our Pb Free sraegy and soldering deails, please download he ON Semiconducor Soldering and Mouning Techniques Reference Manual, SOLDERRM/D. XXX = Specific Device Code M = Dae Code = Pb Free Package (Noe: Microdo may be in eiher locaion) *This informaion is generic. Please refer o device daa shee for acual par marking. Pb Free indicaor, G or microdo, may or may no be presen. DOCUMENT NUMBER: STATUS: REFERENCE: Semiconducor Componens Indusries, LLC, 2002 Ocober, 2002 Rev. 0 DESCRIPTION: 98AON3432E ON SEMICONDUCTOR STANDARD SOT 23, 6 LEAD hp://onsemi.com Elecronic versions are unconrolled excep when accessed direcly from he Documen Reposiory. Prined versions are unconrolled excep when samped CONTROLLED COPY in red. Case Ouline Number: PAGE OF XXX 2

20 DOCUMENT NUMBER: 98AON3432E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #SOT TO ON SEMICON- 9 DEC 2008 DUCTOR. REQ. BY B. BERGMAN. A REDRAWN TO JEDEC STANDARDS. REQ. BY D. TRUHITTE. 2 JAN 20 B CORRECTED LABEL FOR MOLDED BODY DIMENSION OF TOP VIEW TO E. REQ. BY D. TRUHITTE. 29 FEB 202 ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. Semiconducor Componens Indusries, LLC, 202 February, 202 Rev. B Case Ouline Number: 527AJ

21 ON Semiconducor and are rademarks of Semiconducor Componens Indusries, LLC dba ON Semiconducor or is subsidiaries in he Unied Saes and/or oher counries. ON Semiconducor owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of ON Semiconducor s produc/paen coverage may be accessed a /sie/pdf/paen Marking.pdf. ON Semiconducor reserves he righ o make changes wihou furher noice o any producs herein. ON Semiconducor makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does ON Semiconducor assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Buyer is responsible for is producs and applicaions using ON Semiconducor producs, including compliance wih all laws, regulaions and safey requiremens or sandards, regardless of any suppor or applicaions informaion provided by ON Semiconducor. Typical parameers which may be provided in ON Semiconducor daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. ON Semiconducor does no convey any license under is paen righs nor he righs of ohers. ON Semiconducor producs are no designed, inended, or auhorized for use as a criical componen in life suppor sysems or any FDA Class 3 medical devices or medical devices wih a same or similar classificaion in a foreign jurisdicion or any devices inended for implanaion in he human body. Should Buyer purchase or use ON Semiconducor producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold ON Semiconducor and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha ON Semiconducor was negligen regarding he design or manufacure of he par. ON Semiconducor is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor 952 E. 32nd Pkwy, Aurora, Colorado 800 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: ON Semiconducor Websie: Order Lieraure: hp:///orderli For addiional informaion, please conac your local Sales Represenaive