NCV7424. Four Channel LIN Transceiver

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1 Four Channel LIN Transceiver NCV72 is a four channel physical layer device using he Local Inerconnec Nework (LIN) proocol. I allows inerfacing of four independen LIN physical buses and he LIN proocol conrollers. The device is complian o LIN 2.x Proocol Specificaion package and he SAE J2602 sandard. The NCV72 LIN device is a member of he in-vehicle neworking (IVN) ransceiver family. The device is a monolihic soluion incorporaing imes he NCV ransceiver. Feaures TSSOP 16 Package. Pin-ou Compaible wih One Single LIN NCV7321 Transceiver (Pin Numbers o 7, and 10 o 13) Complian wih LIN2.x, Backwards Compaible o Version 1.3 and J2602 Transmission Rae 1 kbps o 20 kbps Indefinie Shor-Circui Proecion on LIN owards Supply and Ground Bus Pins Proeced Agains Transiens in an Auomoive Environmen Thermal Shudown Sysem ESD on LIN Pin Exceeding 10 kv, No Need for Exernal ESD Proecions Load Dump Proecion (5 V) Inegraed Slope Conrol Resuling ino Excellen EME Performance also wihou any Capacior on LIN Pin Excellen EMI Performance Remoe Wake-up via LIN Bus on all Four Channels 3.3 V and 5 V Compaible Digial Inpus Qualiy NCV Prefix for Auomoive and Oher Applicaions Requiring Unique Sie and Conrol Change Require mens; AEC Q100 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Complian TxD RxD3 TxD3 RxD1 EN TxD2 TxD1 RxD TSSOP 16 CASE 98F PACKAGE PICTURE NCV RxD LIN TSSOP 16 LIN3 LIN1 8 9 LIN2 MARKING DIAGRAM 16 1 NV7 2 0 ALYW NV72 0 = Specific Device Code A = Assembly Locaion L = Wafer Lo Y = Year W = Work Week = Pb Free Package (Noe: Microdo may be in eiher locaion) ORDERING INFORMATION See deailed ordering, marking and shipping informaion in he package dimensions secion on page 11 of his daa shee. Semiconducor Componens Indusries, LLC, 2015 May, 2015 Rev. 2 1 Publicaion Order Number: NCV72/D

2 BLOCK DIAGRAM NCV72 Undervolage POR VINT EN Sae & Wake up Conrol Timeous Osc Thermal Shudown RxD1 COMP Vin Filer LIN1 TxD1 Driver Conrol Slope Conrol Channel1 RxD2 TxD2 Channel2 LIN2 RxD3 TxD3 Channel3 LIN3 RxD TxD Channel LIN RB Figure 1. Block Diagram 2

3 Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol Parameer Min Typ Max Uni Nominal Baery Operaing Volage (Noe 1) V Load Dump Proecion 5 I BB _SLP Supply Curren in Sleep Mode, = 12 V, T J < 85 C V = A V LIN LIN Bus Volage 5 5 V V_Dig_IO Operaing DC Volage on Digial IO Pins (EN, RxD1-, TxD1-) V T J Juncion Thermal Shudown Temperaure C T amb Operaing Ambien Temperaure C V ESD Elecrosaic Discharge Volage (all pins) Human Body Model (Noe 2) Conform o EIA JESD22 A11 B Elecrosaic Discharge Volage (LIN) Sysem Human Body Model (Noe 3) Conform o EIC kv kv 1. Below 5 V on in normal mode, he bus will eiher say recessive or comply wih he volage level specificaions and ransiion ime specificaions as required by SAE J2602. I is ensured by he baery monioring circui. Above 27 V on, LIN communicaion is operaional (LIN pin oggling) bu parameers canno be guaraneed. For higher baery volage operaion above 27 V, LIN pull-up resisor mus be seleced large enough o avoid clamping of LIN pin by volage drop over exernal pull-up resisor and LIN pin min curren limiaion. 2. Equivalen o discharging a 100 pf capacior hrough a 1.5 k resisor. 3. Equivalen o discharging a 150 pf capacior hrough a 330 resisor. Sysem HBM levels are verified by an exernal es house. Table 2. PIN FUNCTION DESCRIPTION Pin Name Descripion 1 TxD Transmi Daa Inpu, Low for Dominan Sae; Pull-up o inernal supply guaraneed above pin inpu hreshold 2 RxD3 Receive Daa Oupu; Low in Dominan Sae 3 TxD3 Transmi Daa Inpu, Low for Dominan Sae; Pull-up o inernal supply guaraneed above pin inpu hreshold RxD1 Receive Daa Oupu; Low in Dominan Sae 5 EN Enable Inpu, Transceiver in Normal Operaion Mode when High, Pull-down Resisor o 6 TxD2 Transmi Daa Inpu, Low for Dominan Sae; Pull-up o inernal supply guaraneed above pin inpu hreshold 7 TxD1 Transmi Daa Inpu, Low for Dominan Sae; Pull-up o inernal supply guaraneed above pin inpu hreshold 8 RxD2 Receive Daa Oupu; Low in Dominan Sae 9 LIN2 LIN Bus Oupu/Inpu 10 Ground 11 LIN1 LIN Bus Oupu/Inpu 12 Baery Supply Inpu 13 LIN3 LIN Bus Oupu/Inpu 1 Ground 15 LIN LIN Bus Oupu/Inpu 16 RxD Receive Daa Oupu; Low in Dominan Sae 3

4 TYPICAL APPLICATION VBAT VCC 2.7 V o 5 V 5.1k 1k RxDx TxDx NCV72 Micro conroller EN 1nF RB KL30 LIN BUS 1,2,3, KL31 Figure 2. Applicaion Diagram, Four LIN Maser Nodes Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameer Min Typ Max Uni Volage on Pin V V Bus Volage (LIN1-) 5 5 V V_Dig_IO DC Inpu Volage on Pins (EN, RxD1-, TxD1-) V T J Maximum Juncion Temperaure C V ESD HBM (All Pins) (Noe ) Conform o EIA JESD22 A11 B CDM (All Pins) According o ESD STM kv V HBM ( and ) (Noe ) 8 8 kv Sysem HBM ( and ) (Noe 5) Conform o EIC kv Sresses exceeding hose lised in he Maximum Raings able may damage he device. If any of hese limis are exceeded, device funcionaliy should no be assumed, damage may occur and reliabiliy may be affeced.. Equivalen o discharging a 100 pf capacior hrough a 1.5 k resisor. 5. Equivalen o discharging a 150 pf capacior hrough a 330 resisor. Sysem HBM levels are verified by an exernal es house.

5 Table. THERMAL CHARACTERISTICS Symbol Parameer Condiions Value Uni R JA_1 Thermal Resisance Juncion o Air, JESD51-3 1S0P PCB Free air 128 K/W R JA_2 Thermal Resisance Juncion o Air, JESD51-7 2S2P PCB Free air 72 K/W FUNCTIONAL DESCRIPTION Overall Funcional Descripion LIN is a serial communicaion proocol ha efficienly suppors he conrol of mecharonic nodes in disribued auomoive applicaions. The domain is class-a muliplex buses wih a single maser node and a se of slave nodes. The NCV72 conains four independen LIN ransmiers, LIN receivers plus common baery monioring, power-on-rese (POR) circuis and hermal shudown (TSD). The used LIN ransmier is opimized for he maximum specified ransmission speed of 20 kbps wih excellen EMC performance due o reduced slew rae of he LIN oupus. The juncion emperaure is moniored via a hermal shudown circui ha swiches he LIN ransmiers off when emperaure exceeds he TSD rigger level. The NCV72 has four operaing saes (unpowered mode, sandby mode, normal mode and sleep mode) ha are deermined by he supply volage, inpu signals EN and aciviy on he LIN bus. The operaing saes and principal ransiions beween hem are depiced in Figure 3. OPERATING STATES Sandby mode LIN ransceivers: OFF LIN erm: 30 k RxD1, 2, 3, : Low o indicae wake up on bus EN = High for > enable Normal mode LIN ransceivers: ON LIN erm: 30 k RxD1, 2, 3, : Received LIN daa LIN1, 2, 3 or wakeup EN = High for > enable EN = Low for > disable Unpowered ( Below Rese Level) Sleep Mode LIN ransceivers: OFF LIN erm: floaing RxD1, 2, 3, : floaing above rese level LIN ransceivers: OFF LIN erm: curren source RxD1, 2, 3, : floaing Figure 3. Sae Diagram Unpowered Mode As long as remains below is power-on-rese level, he chip is kep in a safe unpowered sae. LIN ransmiers are inacive, pins are lef floaing. Pins RxDx remain floaing. The unpowered sae will be enered from any oher sae when falls below is power-on-rese level. Sandby Mode Sandby mode is a low-power mode, where he LIN ransceivers remain inacive. A 30 k resisor in series wih a reverse-proecion diode is inernally conneced beween individual LIN pins and pin. Sandby mode is enered afer a wake-up even is recognized while he chip was in he sleep mode, he RxD1,2,3 or pin is pulled low depending on which of he respecive pins LIN1,2,3 or he valid LIN wake-up occurred. While saying in sandby mode, wake-up signaling by RxDx pins on each LIN channel is fully funcional. This is also in case if wake even(s) sared in sleep mode bu acual ransiion from sleep o sandby was caused by preceding wake-up even on oher LIN channel. Normal Mode In normal mode, he full funcionaliy of he LIN ransceivers is available. Daa are sen o he bus according o he sae of TxDx inpus and RxDx pins reflec he logical symbol received on he bus high-impedan for recessive and Low level for dominan. 5

6 A 30 k resisor in series wih a reverse-proecion diode is inernally conneced beween LIN and pins. To avoid ha, due o a failure of he applicaion (e.g. sofware error, a shor o ground, ec.), he LIN bus is permanenly driven dominan and hus blocking all subsequen communicaion, he signal on each TxDx pin passes hrough an independen imer per LIN channel, which releases he bus in case TxDx remains Low for longer han TxD_imeou. The ransmission can coninue once he TxDx reurns o High logical level. This is independen on each channel, means permanen dominan on one channel is no blocking he oher channels from communicaion. In case he juncion emperaure increases above he hermal shudown hreshold, e.g. due o a shor of he LIN wiring o he baery and high ambien emperaure, all four ransmiers are disabled and LIN buses are kep in recessive sae independenly of TxDx inpus. RxDx pins are kep Low during hermal shudown. Once he juncion emperaure decreases below he hermal shudown release level, he ransmission is enabled again. RxD pins are released from assered hermal shudown low level immediaely when chip is below hermal shudown hreshold. As required by SAE J2602, he ransceiver behaves safely below is operaing range i eiher coninues o ransmi correcly (according o is specificaion) or remains silen (ransmis a recessive sae regardless of he TxDx signal). A baery monioring circui in NCV72 deacivaes he ransmier in normal mode if he level drops below MONL_VBB. Transmission is enabled again when reaches MONH_VBB. The inernal logic remains in normal mode and he recepion from he LIN line is sill possible even if he baery monior disables he ransmission. Alhough he specificaions of he monioring and power-on-rese levels are overlapping, i is ensured by he implemenaion ha he monioring level never falls below he power-on-rese level. Normal mode can be enered from eiher sandby or sleep mode when EN Pin is High for longer han enable. When he ransiion is made from sandby mode, RxDx is pu high-impedan immediaely afer EN becomes High (before he expiraion of enable filering ime). Transmission on each channel is only possible for paricular TxDx pin saring from High o Low level (if TxDx pin is Low when enering Normal mode, ransmission is no enabled). Sleep Mode Sleep mode provides exremely low curren consumpion. The LIN ransceiver is inacive and he baery consumpion is minimized. Only a weak pull-up curren source is inernally conneced beween LIN and pins, in order o minimize curren consumpion even in case of LIN shor o. Sleep mode can be enered: Afer he volage level a pin rises above is power-on-rese level. RxDx pins are se high-impedan afer sar-up From normal mode by assigning a Low logical level o pin EN for longer han disable. The sleep mode can be enered even if a permanen shor occurs on he Pin. If a wake-up even occurs during he ransiion beween normal and sleep mode (during he disable filering ime), i will be regarded as a valid wake-up and he chip will ener sandby mode wih he appropriae seing of pins RxDx. LIN Wake up Remoe (or LIN) wake-up can be recognized on all pins on NCV72 when bus is exernally driven dominan for longer han LIN_wake and a rising edge on LIN occurs aferwards see Figure. Wake-up evens can be exclusively deeced in sleep mode or during he ransiion from normal mode o sleep mode. Due o iming olerances, valid wake-up evens beginning shorly before normal-o-sleep mode ransiion can be also someimes regarded as valid wake ups. Deecion of Remoe Wake Up LIN recessive level LIN_wake 0% 60% Sleep Mode o_sb Sandby Mode LIN dominan level Figure. LIN Bus Wake up Deecion 6

7 Definiions All volages are referenced o (Pins 10, 1. These pins are elecrically conneced inside of he package). Posiive currens flow ino he IC. NCV72 ELECTRICAL CHARACTERISTICS Table 5. DC CHARACTERISTICS ( = 5 V o 27 V; T J = 0 C o +150 C; R L(LIN VBB) = 500, unless oherwise specified. Typical values are given a V( ) = 12 V and T J = 25 C, unless oherwise specified.) Symbol Parameer Condiions Min Typ Max Uni CURRENT CONSUMPTION I BB _ON_rec Consumpion Normal Mode; LIN Recessive V = ma I BB _ON_dom Consumpion Normal Mode; LIN Dominan TxDx = Low ma I BB _STB Consumpion Sandby Mode V = ma I BB _SLP Consumpion Sleep Mode V = A I BB _SLP_18V Consumpion Sleep Mode, < 18 V V = A I BB _SLP_12V Consumpion Sleep Mode, = 12 V, T J < 85 C V = 9 30 A POR AND MONITOR PORH_ PORL_ Power on Rese Rising V High Level on Power on Rese Low Falling V Level on MONH_ MONL_ LIN TRANSMITTERs V_dom_LoSup V_dom_HiSup V_REC I_lim R slave LIN RECEIVERs V_bus_dom V_bus_rec Baery Monioring High Level Baery Monioring Low Level Dominan Oupu Volage Dominan Oupu Volage LIN Recessive Oupu Volage Shor Circui Curren Limiaion Inernal Pull up Resisance Bus Volage for Dominan Sae Bus Volage for Recessive Sae Rising.1.5 V Falling 3 V TxDx = Low; = 7.3 V V TxDx = Low; = 18 V V TxDx = High; I LIN = 10 A (Noe 6) 1.5 V V = = 18 V; TxDx = Low ma k V_rec_dom Receiver Threshold LIN Bus Recessive Dominan V_rec_rec Receiver Threshold LIN Bus Dominan Recessive The volage drop in Normal mode beween LIN and pin is he sum of he diode drop and he drop a serial pull up resisor. The drop a he swich is negligible. See Figure 1. 7

8 Table 5. DC CHARACTERISTICS ( = 5 V o 27 V; T J = 0 C o +150 C; R L(LIN VBB) = 500, unless oherwise specified. Typical values are given a V( ) = 12 V and T J = 25 C, unless oherwise specified.) Symbol Parameer Condiions Min Typ Max Uni LIN RECEIVERs V_rec_cn Receiver Cenre Volage (V_rec_dom + V_rec_rec) / V_rec_hys Receiver Hyseresis (V_rec_rec V_rec_dom) I_off_dom LIN Oupu Curren, Bus exernally driven o dominan sae Normal Mode, Driver Off; = 12 V; TxDx = High; V = 0 V ma I_off_dom_slp LIN Oupu Curren, Bus exernally driven o dominan sae Sleep Mode, Driver Off; = 12 V; TxDx = High; V = 0 V A I_off_rec LIN Oupu Curren, Bus in Recessive Sae Driver Off; < 18 V; < V < 18 V 2 A I_no_ I_no_ Communicaion no Affeced LIN Bus Remains Operaional = = 12 V; 0 < V < 18 V 1 1 ma = = 0 V; 0 < V < 18 V 0 5 A C Capaciance on pin No esed in producion, guaraneed by design pf PIN EN Vil_EN Low Level Inpu Volage V Vih_EN High Level Inpu Volage V Rpd_EN Pull down Resisance o Ground k PIN RxDx Iol_RxDx Low Level Oupu Curren V RxD = 0. V, Normal Mode, V = 0 V ma Ioh_RxDx PIN TxDx Vil_TxDx Vih_TxDx High Level Oupu Curren Low Level Inpu Volage High Level Inpu Volage V RxD = 5 V, Normal Mode, A V = V V Rpd_TxDx Pull up on TxDx Pins k THERMAL SHUTDOWN T JSD T JSD_HYST Thermal Shudown Juncion Temperaure Thermal Shudown Hyseresis Temperaure Rising C 5 C 6. The volage drop in Normal mode beween LIN and pin is he sum of he diode drop and he drop a serial pull up resisor. The drop a he swich is negligible. See Figure 1. 8

9 Table 6. AC CHARACTERISTICS ( = 5 V o 27 V; T J = 0 C o +150 C; R L(LIN VBB) = 500, unless oherwise specified. For he ransmier parameers, he following bus loads are considered: L1 = 1 k / 1 nf; L2 = 660 / 6.8 nf; L3 = 500 / 10 nf Symbol Parameer Condiions Min Typ Max Uni LIN TRANSMITTER D1 Duy Cycle 1 = BUS_REC(min) / D2 Duy Cycle 2 = BUS_REC(max) / D3 Duy Cycle 3 = BUS_REC(min) / D Duy Cycle = BUS_REC(max) / D1e Duy Cycle 1 = BUS_REC(min) / D2e Duy Cycle 2 = BUS_REC(max) / D3e Duy Cycle 3 = BUS_REC(min) / De Duy Cycle = BUS_REC(max) / x_prop_down_x x_prop_up_x Propagaion Delay of TxDx o. TxD High o Low Propagaion Delay of TxDx o. TxD Low o High TH REC(max) = 0.7 x TH DOM(max) = x BIT = 50 s V( ) = 7 V o 18 V TH REC(min) = 0.22 x TH DOM(min) = 0.28 x BIT = 50 s V( ) = 7.6 V o 18 V TH REC(max) = x TH DOM(max) = x BIT = 96 s V( ) = 7 V o 18 V TH REC(min) = x TH DOM(min) = x BIT = 96 s V( ) = 7.6 V o 18 V TH REC(max) = 0.7 x TH DOM(max) = x BIT = 50 s V( ) = 5 V o 0 V, (Noes 7 and 8) TH REC(min) = 0.22 x TH DOM(min) = 0.28 x BIT = 50 s V( ) = 5 V o 0 V, (Noes 7 and 8) TH REC(max) = x TH DOM(max) = x BIT = 96 s V( ) = 5 V o 0 V, (Noes 7 and 8) TH REC(min) = x TH DOM(min) = x BIT = 96 s V( ) = 5 V o 0 V, (Noes 7 and 8) s s x_sym_x Propagaion Delay Symmery rx_prop_down_x rx_prop_up_x s fall Falling Edge Normal Mode; = 12 V s rise Rising Edge Normal Mode; = 12 V s sym Slope Symmery Normal Mode; = 12 V 0 s LIN RECEIVERs rec_prop_down_x rec_prop_up_x rec_sym_x Propagaion Delay of o RxDx Receiver Falling Edge Propagaion Delay of o RxDx Receiver Rising Edge Propagaion Delay Symmery s s rec_prop_down_x rec_prop_up_x s 7. The exernal pull-up resisor for duy cycles on V( ) = 0 V is 1 k 8. No esed in producion Exended baery range (5 V; 0 V) is esed on limied sample base only 9

10 Table 6. AC CHARACTERISTICS ( = 5 V o 27 V; T J = 0 C o +150 C; R L(LIN VBB) = 500, unless oherwise specified. For he ransmier parameers, he following bus loads are considered: L1 = 1 k / 1 nf; L2 = 660 / 6.8 nf; L3 = 500 / 10 nf Symbol Parameer MODE TRANSITIONS AND TIMEOUTS _wake Duraion of Dominan for Deecion of Wake up via bus o_sb enable disable Delay from LIN Bus Dominan o Recessive Edge o Enering of Sandby Mode afer Valid LIN Wake up Duraion of High Level on EN Pin for Tran siion o Normal Mode Duraion of Low Level on EN Pin for Tran siion o Sleep Mode Condiions TxD_imeou TxD Dominan Timeou Normal Mode, TxD = Low, Guaran ees Baudrae as Low as 1 kbps Min Typ Max Sleep Mode s See Figure s 7. The exernal pull-up resisor for duy cycles on V( ) = 0 V is 1 k 8. No esed in producion Exended baery range (5 V; 0 V) is esed on limied sample base only Uni s s ms TxDx BIT BIT 50% BUS_dom(max) BUS_rec(min) TH REC(max) TH DOM(max) Thresholds of receiving node 1 TH REC(min) TH DOM(min) Thresholds of receiving node 2 BUS_dom(min) BUS_rec(max) Figure 5. Bus Transmier Duy Cycle 10

11 100% 60% 0% 60% 0% 0% fall rise Figure 6. Bus Transmier Rising and Falling Times 60% 0% RxDx rec_prop_down rec_prop_up 50% Figure 7. Bus Receiver Timing TxDx BIT BIT 50% 60% 0% x_prop_down x_prop_up Figure 8. Transmier Timing ORDERING INFORMATION Par Number Descripion Temperaure Range Package Shipping NCV72DB0R2G Quad LIN Transceiver 0 C o +125 C TSSOP 16 (Pb Free) 2500 / Tape & Reel For informaion on ape and reel specificaions, including par orienaion and ape sizes, please refer o our Tape and Reel Packaging Specificaions Brochure, BRD8011/D. 11

12 PACKAGE DIMENSIONS 0.15 (0.006) T 0.15 (0.006) T 0.10 (0.00) T SEATING PLANE L U PIN 1 IDENT. U D S S 2X L/2 C 16X K REF 0.10 (0.00) M T U S V S A V G B U H TSSOP 16 CASE 98F ISSUE B J N N J1 F DETAIL E DETAIL E SOLDERING FOOTPRINT 7.06 K K1 ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.010) M W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y1.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.0 BSC BSC M PITCH 16X X 1.26 DIMENSIONS: MILLIMETERS ON Semiconducor and are regisered rademarks of Semiconducor Componens Indusries, LLC (SCILLC). SCILLC owns he righs o a number of paens, rademarks, copyrighs, rade secres, and oher inellecual propery. A lising of SCILLC s produc/paen coverage may be accessed a /sie/pdf/paen Marking.pdf. SCILLC reserves he righ o make changes wihou furher noice o any producs herein. SCILLC makes no warrany, represenaion or guaranee regarding he suiabiliy of is producs for any paricular purpose, nor does SCILLC assume any liabiliy arising ou of he applicaion or use of any produc or circui, and specifically disclaims any and all liabiliy, including wihou limiaion special, consequenial or incidenal damages. Typical parameers which may be provided in SCILLC daa shees and/or specificaions can and do vary in differen applicaions and acual performance may vary over ime. All operaing parameers, including Typicals mus be validaed for each cusomer applicaion by cusomer s echnical expers. SCILLC does no convey any license under is paen righs nor he righs of ohers. SCILLC producs are no designed, inended, or auhorized for use as componens in sysems inended for surgical implan ino he body, or oher applicaions inended o suppor or susain life, or for any oher applicaion in which he failure of he SCILLC produc could creae a siuaion where personal injury or deah may occur. Should Buyer purchase or use SCILLC producs for any such uninended or unauhorized applicaion, Buyer shall indemnify and hold SCILLC and is officers, employees, subsidiaries, affiliaes, and disribuors harmless agains all claims, coss, damages, and expenses, and reasonable aorney fees arising ou of, direcly or indirecly, any claim of personal injury or deah associaed wih such uninended or unauhorized use, even if such claim alleges ha SCILLC was negligen regarding he design or manufacure of he par. SCILLC is an Equal Opporuniy/Affirmaive Acion Employer. This lieraure is subjec o all applicable copyrigh laws and is no for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Lieraure Disribuion Cener for ON Semiconducor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderli@onsemi.com N. American Technical Suppor: Toll Free USA/Canada Europe, Middle Eas and Africa Technical Suppor: Phone: Japan Cusomer Focus Cener Phone: ON Semiconducor Websie: Order Lieraure: hp:///orderli For addiional informaion, please conac your local Sales Represenaive NCV72/D

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