Asymmetric multilevel outphasing transmitter using Class-E PAs with discrete pulse width modulation

Transcription

1 Asymmetric multilevel utphasing transmitter using Class- PAs with discrete pulse width mdulatin The MT Faculty has made this article penly available. Please share hw this access benefits yu. Yur stry matters. Citatin As Published Publisher Chung, SungWn et al. Asymmetric Multilevel Outphasing Transmitter Using class- PAs with Discrete Pulse Width Mdulatin. MTT-S nternatinal Micrwave Sympsium Digest (MTT), Cpyright 21 nstitute f lectrical and lectrnics ngineers () Versin Final published versin Accessed Tue Oct 3 14:24:22 DT 218 Citable Link Terms f Use Detailed Terms Article is made available in accrdance with the publisher's plicy and may be subject t US cpyright law. Please refer t the publisher's site fr terms f use.

2 Asymmetric Multilevel Outphasing Transmitter using Class- PAs with Discrete Pulse Width Mdulatin SungWn Chung, Philip A. Gdy, Taylr W. Bartn, David J. Perreault, and Jel L. Dawsn Micrsystems Technlgy Labratries, Massachusetts nstitute f Technlgy, Cambridge, MA 2139 Abstract-We present a high-eciency transmitter architecture based n asymmetric multilevel utphasing (AMO), but with a new methd f generating discrete amplitude levels frm the cnstituent amplifiers. AMO and multilevel LNC (ML-LNC) transmitters imprve their eciency ver LNC by switching the supplies f the pwer amplifiers (PAs) amng a discrete set f vltages. This allws them t minimize the ccurrence f large utphasing angles. Hwever, it is als pssible t generate a discrete set f amplitudes by varying the duty cycle f the wavefrm that drives the PAs. The chief advantage f this discrete pulse width mdulatin (DPWM) is hardware simplicity, as it eliminates the need fr a fast, lw-lss switching netwrk and a selectin f pwer supply vltages. We demnstrate this cncept with a 48-MHz, 2- W peak utput pwer AMO transmitter using a fur-level DPWM. At peak utput pwer, the measured pwer-added eciency is 77.7%. Fr a 16-QAM signal with a 6.S-dB peakt-average pwer rati, the AMO prttype imprves the average eciency frm 17.1% t 36.5% cmpared t the standard LNC system. ndex Terms- pwer amplifier (PA), utphasing, Class-, pulse width mdulatin (PWM), asymmetric pwer cmbining, asymmetric multilevel utphasing (AMO), LNC, digital predistrtin.. NTRODUCTON Wideband RF pwer amplifiers (PAs) with high eciency are f great imprtance in high-data-rate cmmunicatins. Tremendus effrts t beat the linearity-eciency tradeff fr PAs has led t a wide variety f architectures, including plar, utphasing, envelpe tracking, feedfrward, Cartesian feedback, predistrtin, Dherty, RF pulse width mdulatin (PWM), and RF delta-sigma mdulatin [1 ]. Outphasing architectures [2], [3] are capable f transmitting very wideband signals and are thus suitable fr wideband cmmunicatin in multi-standard applicatins. Hwever, the pwer eciency f utphasing is pr at large pwer back-ff, which is a critical drawback fr wideband signals with high peak-t-average pwer ratis (PAPR). Outphasing with lssless pwer cmbining [4], [5] imprves eciency at the cst f reduced linearity and bandwidth. This paper presents an utphasing transmitter architecture using Class- PAs with discrete pulse width mdulatin (DPWM) fr high-eciency wideband RF This wrk was spnsred by the Department f the Air Frce under Cntract FAS271-5-C-2. Opinins, interpretatins, cnclusins, and recmmendatins are thse f the authr and are nt necessarily endrsed by the United States Gvernment. This wrk was als funded in part by the MT Deshpande Center. Class- PA with a resnant gate driver / ; _.' : fi Fig.. Asymmetric multilevel utphasing (AMO) transmitter with discrete pulse width mdulatin (DPWM). transmissin. DPWM imprves the classical utphasing pwer eciency by allwing independent, discrete envelpe amplitude changes in each f the tw Class- PAs. n cntrast, cnventinal RF PWM Class- PAs [6], [7] cntinuusly mdulate the input duty cycle ver a large range with very fine reslutin. One practical prblem with the cnventinal PWM apprach is that in rder t achieve a wide dynamic range at GHz carrier frequencies, pulse widths n the rder f a few picsecnds are required, which are dicult t generate. Furthermre, input pulses with very lw duty ratis are nt prcessed effectively by PAs s that the transmissin f high PAPR results in pr linearity. With DPWM, these prblems are vercme by restricting the duty cycles t a discrete set and aviding small duty cycles. Outphasing is used fr fine amplitude cntrl and fr generating very small amplitudes.. ASYMMTRC MULTLVL OUTPHASNG (AMO) The architecture f an AMO transmitter with DPWM is shwn in Fig. 1. ach envelpe amplitude f the tw Class PAs is chsen frm a discrete set f values such that the utphasing angle is minimized. The tw PA utputs are cmbined based n the algrithm utlined in [8] in rder t achieve high eciency transmissin ver a wide range f utput pwers. The use f DPWM with the AMO architecture is mtivated by an eciency analysis ver the entire range f utput pwer levels. The utput pwer f the system can be mdulated in tw fundamental ways: either by varying the utphasing angles r the envelpe amplitudes f the inputs t the Wilkinsn cmbiner. n the case f utphasing, the amplitudes are held cnstant and the utphasing angle cntrls the utput pwer as in a LNC architecture. Q /11$

3 1[j==::;==:::;Z::::;==;:':::;- :-;:::::;O 9 i Q; a. 1 O L Nrmalized Output Pwer (db) 1 -AMO w/4-lvl DPWM AMO wi 3-lvl DPWM l:! 8._._. AMO w/2-lvl DPWM.s 'iij C ---PWM LNG Nrmalized Output Pwer (db) Fig. 2. Asymmetric pwer cmbining eciency. Fig. 4. Drain eciency f ideal AMO-DPWM transmitters using a single supply. :J C. ' ' -16, m 5!'l 9 Q) 8 ' -3 4';' 7!. U > a «' w ' Q) u; r-'----:o_'::',12 iij '5-12. z -2!----': 5-1:':- 15:::2:' ==4=4:':: 55 nput Pulse Duty Cycle (percent) (a) C Fig. 3. (a) PA utput pwer and eciency with varying input duty cycles, (b) simulated impact f resnant PA drivers n the duty cycle and amplitude f PA input pulses, depending n input drive inductr Q. Likewise, fr envelpe amplitude cntrl the amplitudes are varied, either by mdulating the PA supply vltage as in [8] r by PWM f the PA input as in this wrk. The eciency f utphasing with an islating cmbiner is cmpared t that f PWM f a single class- PA in Fig. 2. The eciency f pwer cmbining with an ideal 2-way Wilkinsn pwer cmbiner is given by ''a = f (V cs fh + V2 cs (2) 2 2(V? + Vn where V and V2 are the amplitudes f the tw RF sinusid inputs whse utphasing angles are Bl and B2 (see Fig. 1 fr ntatinal cnventin). Because the AMO architecture allws V and V2 t be unequal, there is lss in the cmbiner fr AMO even when there is n utphasing. This asymmetric cmbining effect is shwn in Fig. 2 fr the special case where the Bl and B2 are zer and the amplitude f V2 is swept cntinuusly between and V. AMO transmitters take advantage f the higher eciency f envelpe amplitude cntrl by cmbining discrete amplitude changes with the fine envelpe cntrl prvided by utphasing. n this paper, we present the use f PWM fr amplitude cntrl in an AMO transmitter. This apprach can either replace r supplement the supply vltage mdulatin presented in [8]. (b) (1) 1 9 i e Nrmalized Output Pwer (db) Fig. 5. Drain eciency f ideal AMO-DPWM transmitters using a 4- level supply mdulatr (red line) vs. 4-level supply mdulatr cmbined with 2-level DPWM (blue line).. DSCRT PULS WDTH MODULATON (DPWM) DPWM prvides discrete envelpe amplitude mdulatin, withut supply vltage mdulatin, t each f the tw Class- PAs used in utphasing. By limiting the input duty cycle variatin t a finite number f discrete pulse widths, DPWM eliminates the need fr extremely accurate pulse cntrl. DPWM can be implemented by (1) hard-switching inverter gate drive, (2) pulse input t resnant gate drive, (3) resnant gate drive with gate bias mdulatin. ach implementatin has trade-ffs. Fr example, the first tw methds have limited pwer cntrl range while gate bias mdulatin has a finite settling time. Likewise, a resnant input drive requires an inductr, making it best suited fr a discrete implementatin. Regardless f the DPWM implementatin, the utput pwer and drain eciency f an ideal Class- PA will have the relatinship t duty cycle shwn in Fig. 3(a). A. mpact f Resnant PA Driver The limited input duty cycle range f DPWM allws a resnant gate driver t be used. This is an imprtant advantage ver cnventinal PWM, as resnant gate drivers are ften simpler t implement and mre ecient than hard-switched drivers. Fig. 3(b) shws the impact f a resnant PA driver n a l-w Class- PA with 5-D gate resistance, -pf gate capacitance, zer switch resistance, and ideal resnant /11$

4 V ( ' f----' ' ---'------'----j. _ V,h A -A P {\f -rr -A A - Vb; V V \TVVv V. Class- PA with Discrete Pulse-Width Mdulatin (DPWM).,/ '-'\ Fig. 6. Prttype 48-MHz AMO transmitter with DPWM. utput filter. The resnant PA input netwrk with 5- n surce resistance and an inductr with a finite Q, as shwn in Fig. 1, shapes a surce pulse Vs int an input pulse Vi. When the surce duty cycle gets smaller, the input amplitude gets smaller s that the resnant driver cannt turn n the main transistr f a Class- PA. T prvide sucient PA input amplitude, the minimum input duty cycle shuld be larger than arund 2%. As a result, the maximum PA pwer back-ff that can be achieved by DPWM is limited t less than 6 db. Additinally, because this input amplitude variatin affects the Class- PA utput pwer, predistrtin is necessary t prvide a linear utput. B. ciency f AMO with DPWM Fig. 4 shws the drain pwer eciency f an ideal AMO-DPWM transmitter using a single supply. An ideal C1ass- PA mdel [9] was used t get these results. When DPWM prvides 6-dB pwer back-ff, n mre than fur duty cycles (23%, 27%, 32%, 5%) are necessary t get high eciency. As shwn in Fig. 5, this DPWM apprach can als be cmbined with a multilevel supply mdulatr as in [8] t prvide even higher verall eciency with nly tw duty cycles (35%, 5%). V. TRANSMTTR MPLMNTATON T demnstrate the feasibility f the AMO with DPWM system, a prttype was designed and implemented with discrete cmpnents at an perating frequency f 48MHz. Fig. 6 shws a circuit schematic f the prttype, which is identical t that in [1] except fr the gate driver. ach c1ass- PA was implemented using the ST Micrelectrnics PD576 RF LDMOS, and was designed fr a supply vltage f 12V with low utput pwer. Thus the maximum utput pwer f the prttype utphasing PA is 2W. Fur parallel Fairchild NC7ZW4 CMOS inverters prvide the gate drive. The pwer cmbiner used in the prttype cnsists f tw 1: 1 transfrmers, each implemented with 18AWG 5-turn bifilar windings A, : Antenna.iiii.2=== ,---,---r--, PDF ----line -AMO.15 - PWM f-+--t--t--j---j--7'+-if--l..1f--t--j---j---f-,71'-/ l ,/.5 _ --j----i Nrmalized Output Pwer (db) Fig. 7. Measured PWM pwer-added eciency vs. utput pwer, alng with ptimized DPWM levels fr a 16-QAM signal with 6.5dB PAPR. The PDF f the 16-QAM signal is als shwn. n a Ferrnics Cbalt-Nickel ferrite trid cre. The pulse width f each c1ass- PA is cntrlled by varying the gate bias vltage f the main transistr, as shwn in Fig. 6. V. XPRMNTAL RSULTS Fig. 7 shws the measured PWM pwer-added eciency (PA) vs. utput pwer fr the prttype transmitter. Fr a given number f discrete pulse widths, this data can be used t find the ptimum set f DPWM levels that maximize the eciency fr a given amplitude prbability density functin (PDF). n this wrk we chse t use fur DPWM levels, and we tested ur system with a 5-ksym/s 16-QAM signal with a PAPR f 6.5dB and a carrier frequency f 48 MHz. The crrespnding ptimum eciency curves fr the AMO prttype are shwn in Fig. 7. t can be seen that the AMO system with DPWM prvides a significant eciency imprvement ver the standard LNC system fr a large utput pwer range. Fig. 8 shws the measured amplitude and phase f the utput vltage at the fundamental f the RF utput frequency versus the utphasing angle. The phase measurements are nrmalized t the utput phase at the maximum utput pwer. There are 1 different curves, each fr a different cmbinatin f discrete pulse widths /11$26. C21 266

5 OJ) <1J '.t:: - '5 B- Output Phase vs. Outphasing Angle Output Amplitude vs. Outphasing Angle 18 r---,----,---,--,---- -G -12 _18 L-.L----'---'-----'----' GO GO Outphasing Angle (deg) :-. r a.s <1J -. a. : B- O L--L---'----L GO GO Outphasing Angle (deg) Fig. 8. Measured utput amplitude and phase linearity fr the prttype AMO system with DPWM. ach curve crrespnds t a different cmbinatin f discrete pulse widths fr the tw utphased PAs. The ideal curves fr the utput amplitude are shwn in black a ]. :; -.5 line wi p: VM = 1.2%. Z rr Nrmalized -channel a C. :; Z -1.5 AMO wi p: VM = 1.% r L-.-f-L -l.s Nrmalized -channel Fig. 9. Measured VM f 5-ksym/s 16-QAM with 6.5-dB PAPR after predistrtin. fr the 2 utphased PAs. Due t PA mismatch (which is the main surce f the distrtin), sme cmbinatins cannt achieve zer utput amplitude even when bth PAs use the same discrete pulse width and are cmpletely ut f phase, as can be seen in Fig. 8. Thus it is imprtant that the discrete levels and cmbinatins are chsen t achieve sucent amplitude dynamic range while maximizing the verall eciency. A lkup table cnstructed frm the data in Fig. 8 is used t crrect fr the static nnlinearity. T demnstrate the linearity f the system, we tested the prttype with a 5-ksym/s 16-QAM signal with a PAPR f 6.5dB and a carrier frequency f 48 MHz. The digital baseband data generatin and assciated signal prcessing were perfrmed in MATLAB and upladed int the internal memry f arbitrary functin generatrs. The baseband phase data fr each PA was upcnverted t 48MHz with an Agilent vectr signal generatr, and the system utput was fed int an HP 894 vectr signal analyzer fr spectrum and errr vectr magnitude (VM) analysis. Fig. 9 shws the measured demdulated 16-QAM cnstellatin f the prttype fr bth the standard LNC case and fr the AMO-DPWM system after predistrtin (PD). After i -1 V Fig. 1. LNe -UNCwith PO -AMO-DPWM with PO - i/ / L /. r.- \ Frequency (MHz) Measured transmit spectrum f the 16-QAM signals. predistrtin, the VM is reduced t 1.%. Fig. 1 shws the measured utput spectrum fr the 5-ksym/s 16-QAM transmissin ver a 48-MHz carrier frequency. Fr the 16-QAM signal, the AMO system imprves the verall eciency frm 17.1 % t 36.5% cmpared t the standard LNC system, an eciency imprvement f mre than 2x. V. CONCLUSONS The AMO transmitter using c1ass- PAs with DPWM was prpsed t nt nly greatly increase transmitter eciency but als enable wideband RF transmissin. The DPWM technique was described as a methd t prvide an ecient carse utput envelpe cntrl, with utphasing prviding the remaining fine envelpe cntrl. Finally, we demnstrate a 4-level AMO transmitter at 48MHz which imprves the verall eciency frm 17.1 % t 36.5% fr a 5-ksym/s 16-QAM signal with a PAPR f 6.5dB. RFRNCS [] F. H. Raab, Pwer amplifiers and transmitters fr RF and micrwave, Trans. Micrwave Thery Tech., vl. 5, n. 3, pp , Mar. 22. [2] H. Chireix, High-pwer utphasing mdulatin, Prc. f the R, vl. 23, pp , [3] D. C. Cx, Linear amplificatin with nnlinear cmpnents, Trans. Cmmun., pp , Dec [4] S. Mludi, K. Takinami, M. Yussef, M. Mikhemar, and A. Abidi, An utphasing pwer amplifier fr a sftware-defined radi transmitter, in SSCC Dig. Tech. Papers, 28, pp [5] R. Beltran, F. H. Raab, and A. Velazquez, HF utphasing transmitter using c1ass- pwer amplifiers, in Prc. nt'l Micrwave Symp., 29, pp [6] J. Keyser, R. Uang, Y. Sugiyama, M. wamt,. Galtn, and P. Asbeck, Digital generatin f RF pulsewidth mdulated micrwave signals using delta-sigma mdulatin, in Prc. nt'l Micrwave Symp., 22, pp [7] J. S. Walling, S. S. Taylr, and D. J. Alistt, A c1ass-g supplymdulatr and c1ass- PA in 13 nm CMOS, J. Slid-State Circuits, vl. 44, n. 9, pp , Sept. 29. [8] S. Chung, P. A. Gdy, T. W. Bartn,. W. Huang, D. J. Perreault, and J. L. Dawsn, Asymmetric multilevel utphasing architecture fr multistandard transmitters, in Prc. RFC Symp., 29, pp [9] F. H. Raab, dealized peratin f the Class tuned pwer amplifier, Trans. Circuits Syst. 1/, vl. CAS-24, n. 12, pp , Dec [1] P. Gdy, D. J. Perreault, and J. L. Dawsn, Outphasing energy recvery amplifier with resistance cmpressin fr imprved eciency, Trans. Micrwave Thery Tech., Dec /11$26. C21 267