Frequency Limits of InP-based Integrated Circuits

Transcription

1 Plenary, Indium Phosphide and Related Materials Conference, May 15-18, Matsue, Japan Frequency Limits of InP-based Integrated Circuits Mark Rodwell, E. Lind, Z. Griffith, S. R. Bank, A. M. Crook U. Singisetti, i M. Wistey, G. Burek, A.C. Gossard University of California, Santa Barbara Sponsors J. Zolper, S. Pappert, M. Rosker DARPA (TFAST, SWIFT, FLARE) D. Purdy, I. Mack Office of Naval Research Kwok Ng, Jim Hutchby Semiconductor Research Corporation Collaborators (HBT) M. Urteaga, R. Pierson, P. Rowell, M-J Choe, B. Brar Teledyne Scientific Company X. M. Fang, D. Lubyshev, Y. Wu, J. M. Fastenau, W.K. Liu International Quantum Epitaxy, Inc. S. Mohney Penn State University Collaborators (III-V MOS) A. Gossard, S. Stemmer, C. Van de Walle University of California Santa Barbara P. Asbeck, A. Kummel, Y. Taur, University of California San Diego J. Harris, P. McIntyre, Stanford University C. Palmstrøm, University of Minnesota M. Fischetti University of Massachusetts Amherst rodwell@ece.ucsb.edu , fax

2 Specific Acknowledgements (Prof.) Erik Lind Dr. Zach Griffith Dr. Mark Wistey 125 nm HBTs process technology theory / epi design 500 & 250 nm HBTs 150 GHz Logic 100 GHz op-amps InGaAs MOSFET process technology theory / epi design

3 THz Transistors are coming soon; both InP & Silicon InP Bipolars: 250 nm generation: 780 GHz f max, 424 GHz f τ, 4-5 V BV CEO 125 nm & 62 nm nodes ~THz devices db Z. Griffith H 21 U ma/μ μm 2 10 f = 780 GHz max f = 424 GHz τ Hz IBM IEDM '06: 65 nm SOI CMOS 450 GHz f max, ~1 V operation Intel Jan '07: 45 nm / high-k h / metal gate continued rapid progress continued pressure on III-V technologies V ce If you can't beat them, join them! unclear if Si MOSFETs will work well at sub-22-nm gate length InGaAs/InAs/InP channels under serious investigation for CMOS VLSI. Datta, DelAlamo, Sadana,...

4 THz InP vs. near-thz CMOS: different opportunities 65 / 45 / 33 / nm CMOS vast #s of very fast transistors... having low breakdown, sloppy DC parameters what NEW mm-wave applications will this enable? massive monolithic mm-wave arrays 1 Gb/s over ~1 km mm-wave MIMO DC parameters limit analog precision...

5 THz InP vs. near-thz CMOS: different opportunities InP HBT: THz bandwidths, good breakdown, analog precision db U 20 H f = 780 GHz max f = 424 GHz τ Hz & I, I (A) c b I c I b V be (V) ma/μ μm GHz, 70 mw amplifiers (design) In future: 700 or 1000 GHz amplifiers? V ce M. Jones 200 GHz digital logic (design) In future: 450 GHz clock rate? Z. Griffith M. Urteaga (Teledyne) GHz gain-bandwidth op-amps low 2 GHz In future: 200 GHz op-amps for low-im3 10 GHz amplifiers? Z. Griffith

6 Transistor Benchmarks f max matters db U H 21 f t = 660 GHz f max = 218 GHz Hz Tuned amplifiers: f max sets bandwidth Mixed-signal: C cb ΔV/ I c, C je ΔV/ I c, R ex I c /ΔV, R bb I c /ΔV, ex c τ f bb c no gain above GHz BVCEO is not the only voltage limitit (ma/μm 2 ) J e ! 6.8 V BVCEO V (V) ce Need Safe Operating Area...at least BV ceo /2 at J max /2 thermal resistance, high-current breakdown high-temperature operation (~75 C)? Goal is >1 THz f τ and f max <50 fs CΔV / I charging delays emphasize InP-collector DHBTs

7 HBT Scaling Laws

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9 InP DHBTs: May 2007 (GHz) max f m 200 GHz GHz 400 GHz 500 GHz 600 GHz nm = f max f τ popular or Teledyne RSC ( f + f ) / 2 UIUC DHBT NTT 500 SFU 600nm Fujitsu HEMT UIUC SHBT UCSB 300 NGST Updated March nm Pohang SHBT HRL IBM SiGe Vitesse f τ (1 τ f τ f τ f f max max + 1 max metrics : f mw/ μm alone max much better ) 1 power amplifiers: metrics : PAE, associated gain, low noise amplifiers: F min digital : f ( C ( R clock cb ex, associated gain, I, hence ΔV / I f t (GHz) ( τ + τ ) ( R b bb I c c c ), / ΔV ), / ΔV ), c

10 HBT Scaling Roadmaps

11 2005: InP 500 nm Scaling Generation emitter base 500 nm width 16 Ω μm 2 contact ρ 300 width, 20 Ω μm 2 contact ρ collector 150 nm thick, 5 ma/μm 2 current density 5 V, breakdown f τ 400 GHz f max 500 GHz power amplifiers 250 GHz digital it clock rate 160 GHz (static dividers) (178 GHz) (150 GHz)

12 2006: 250 nm Scaling Generation, 1.414:1 faster emitter nm width 16 9 Ω μm 2 access ρ base width, Ω μm 2 contact ρ collector nm thick, 5 10 ma/μm 2 current density V, breakdown f τ GHz f max GHz power amplifiers GHz digital it clock rate GHz (static dividers) (425 GHz) (780 GHz)

13 2007: 125 nm Scaling Generation almost-thz HBT emitter nm width Ω μm 2 access ρ base width, Ω μm 2 contact ρ collector nm thick, ma/μm 2 current density V, breakdown f τ GHz f max GHz power amplifiers GHz digital it clock rate GHz (static dividers)

14 2008-9: 65 nm Scaling Generation beyond 1-THz HBT emitter nm width Ω μm 2 access ρ base nm width, Ω μm 2 contact ρ collector nm thick, ma/μm 2 current density V, breakdown f τ GHz f max GHz power amplifiers GHz digital it clock rate GHz (static dividers)

15 HBT Scaling Challenges

16 Scaling challenges: What looks easy, what looks hard? key device parameter required change collector depletion layer thickness decrease 2:1 base thickness decrease 1.414:1 emitter junction width decrease 4:1 collector junction width decrease 4:1 emitter resistance per unit emitter area decrease 4:1 current density increase 4:1 base contact resistivity decrease 4:1 (if contacts lie above collector junction) base contact resistivity (if contacts do not lie above collector junction) unchanged Hard: Thermal resistance (ICs) Emitter contact + access resistance Yield in deep submicron processes Contact electromigration (?), dark-line defects (?) Probably not as hard : Probably not as hard : Maintaining adequate breakdown for 3 V operation...

17 Temperature Rise: Transistor, Substrate, Package cylindricall heat flow near junction spherical flow for r > L e planar flow for r > D HBT / 2 P L e P P Tsub D / 2 ΔTsubstrate ln 2 π K InPLE We πk InP LE D K InP D increases logarithmically insignificant variation increases quadratically if T sub is constant ΔT package 1 + π 1 2 K P Cu chip W chip se, Kelvin junctio on temperature ri T sub = 40 μm (150 GHz / f clock ) total substrate: cylindrical + spherical regions package substrate: planar region master-slave D-Flip-Flop clock frequency, GHz Wiring lenghts, clock rates, power densities, etc. scaled from demonstrated 150 GHz digital ICs

18 HBTs: 500 nm Generation

19 500 nm Generation in Manufacturing: Teledyne Self-aligned Dielectric Sidewall Process No short-circuits from liftoff defects. Emitter Contact Emitter can be much thinner small etch undercut. Base Contact Dielectric Sidewall (red), U(blue e) (db) J E = 6.5 ma/um 2 V CE = 1.5 V f τ = 405GHz f max = 392 GHz emitter emitter metal EB grade base dielectric sidewall spacer base contact window base metal H21 0 RF Gains Frequency (GHz) Electroplate emitter contact Etch emitter semiconductor Dielectric sidewall deposition Base contact patterning Selectively deposit base metal M. Urteaga et al, 2004 IEEE Device Research Conference, June 21-23, 2004 c.f. also Minh Le et al IEDM 2006 (Vitesse)

20 Example ICs in 500 nm HBT 175 GHz, 7.5 mw 142 GHz, 800 mw 128 GHz, 206 mw medium-power amp. master/slave latch master/slave latch V. Paidi Z. Griffith M. Urteaga P. Rowell D. Pierson B. Brar mesa HBT UCSB mesa HBT UCSB N+ Fe N+ Fe N+ N+ S.I. sidewall /pedestal HBT Teledyne Other Results: 160 Gb/s multiplexer (T. Swahn et al, Chalmers / Vitesse) ~5000-HBT direct-digital frequency synthesis ICs (Vitesse, Teledyne)

21 HBTs: 250 nm Generation

22 250 nm scaling generation InP DHBTs Emitter contact resistance 5 Ω μm 2 Base contact t resistance is < 5 Ω μm 2 Z. Griffith E. Lind

23 DHBTs: 250 nm Scaling Generation Z. Griffith E. Lind nm thick collector 60 nm thick collector U 30 U H 21 db 20 H 21 db 20 ma A/μm 2 10 f = 780 GHz max f =424GHz τ Hz ma/μ μm 2 10 f = 218 GHz max f = 660 GHz t V 0 1 ce V Emitter access: 5.1 Ω μm 2 ce 2 3 Base contact: 6.3 Ω μm Hz

24 Example IC Designs in 250 nm HBT M. Jones Z. Griffith 340 GHz, 70 mw, medium-power amplifiers 200 GHz master-slave latches...fabrication planned summer/fall fabrication on hold...

25 125 nm InP HBT development

26 Emitter Access Resistance 125 nm generation requires 5 Ω - μm 2 emitter resistivities iti 65 nm generation requires 1-2 Ω - μm 2 Erik Lind Adam Crook Seth Bank Uttam Singisetti Recent Results: ErAs/Mb MBE in-situ 1.5 Ω - μm 2 Mb MBE in-situ 0.6 Ω - μm 2 TiPdAu ex-situ 0.5 Ω - μm 2 TiW ex-situ 0.7 Ω - μm 2 Degeneracy contributes 1 Ω - μm 2 20 nm emitter-base depletion layer contributes 1 Ω - μm 2 resistance 10 2 J(mA/um^2) Fermi-Dirac Boltzmann T e =0 nm 10 nm steps Equivalent series resistance approximation V be - φ E fn x ( x) = J qn( x) T e =100 nm

27 Epitaxial Layer Development for 125 nm Generation Erik Lind InGaAs base: low sheet resistivity, it low transit time, but collector must be graded d ev low-current breakdown dominated d by tunneling in setback layer base collector V cb = 0.0 V nm : Zach Griffith 30 B-C grade redesign: thin the setback, thin the grade 1) less superlattice periods... ev ) nm 2) thinner (sub-monolayer) superlattice periods random alloy grade Current (A/cm2) calculation Vcb (V) ma/μm V ce 3) thin GaAs/InGaAs strained-layer grade DC data shows expected increase in breakdown. Transport (RF) data is pending.

28 125 nm Emitter Process Erik Lind Blanket sputter deposition TiW emitter contact metal Optical lithography ICP reactive-ion etching ICP RIE etch of InGaAs/InP semiconductor, Selective wet etch to base 125 nm emitter 500 nm undercut at emitter ends 61 nm junction: 40 nm lateral undercut

29 UCSB 125 nm DHBT Development Erik Lind Adam Crook 125 nm emitter process InGaAs/InP Emitter Metal emitter contact resistivity ~ 0.7 Ω - μm 2 base contact resistivity ~ 3-5 Ω -μm 2 Target performance ~ GHz simultaneous f t & f max, 3-4 V breakdown

30 How might we build the 62.5 nm HBT? Mesa process: control of etch undercut with dry+wet process Alternatives: - dielectric sidewall process - sidewall process with extrinsic base regrowth: allows thinner base

31 InP-based FETs; MOSFETs & HEMTs

32 InP-based HEMTs & MOSFETs : Why? InGaAs/InP HEMTs: mm-wave low-noise amplifiers imum Noise Figure, Mini 8 7 dbghz f τ = Frequency, GHz f τ = 500 GHz F min 1+ g ( R + R + R mi s g i ) A ~2.5:1 f τ / f signal ratio provides 3 db noise figure. Γ Low-noise GHz preamplification is a key application for 1-THz-f τ HEMTs f f τ InGaAs/InP MOSFETs: post-22-nm VLSI (?) Higher mobility and peak electron velocity than in Silicon higher ( I d / W g ) and lower ( CΔV / I ) at sub-22-nm scaling (?)

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35 Some Encouraging Initial Data non-parabolic bands (variable m*) significantly increase feasible sheet charge Asbeck / Fischetti / Taur simulate drive currents much larger than for constant-m* model -- mobilities seem to be acceptable even in thin wells M. Wistey preliminary data... and our current device designs... metal gate source contact drain contact dielectric N+ regrowth InGaAs channel N+ regrowth InP sub-channel barrier undoped undoped substrate P + substrate substrate well: 2.5 nm InGaAs, 2.5 nm InP N+ InGaAs/InAs extrinsic source & drain by regrowth device design and fabrication: Asbeck group: UCSD Taur group: UCSD Fischetti group: U. Mass Rodwell group: UCSB Palmstrøm group: U. Minn

36 Frequency Limits of InP-based Integrated Circuits InP Bipolar Transistors Scaling limits: contact resistivities, device and IC thermal resistances. 62 nm (1 THz f τ, THz f max ) scaling generation is feasible. 700 GHz amplifiers, 450 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible? InP Field-Effect Transistors Low electron effective mass difficulties with further scaling Guarded optimism regarding 22 nm generation for VLSI Serious difficulties beyond.

37 (end)

38 non-animated versions of the three key scaling slides

39 HBT scaling laws Goal: double transistor bandwidth when used in any circuit keep constant all resistances, voltages, currents reduce 2:1 all capacitances and all transport delays 2 τ = T 2D + T v thin base ~1.414:1 τ b b n b / c = T c 2 v thin collector 2:1 T b W e W bc T c C A R ex = ρc/a/ A I A cb c /Tc e 2 c, Kirk e / Tc reduce junction areas 4:1 reduce emitter contact resistivity 4:1 (current remains constant, as desired ) ( ) emitter length L E ΔT P πk L InP E L e P need to reduce junction areas 4:1 ln + W reduce widths 2:1 & reduce length 2:1 doubles ΔT e πk InPLE reducing widths 4:1, keep constant length small ΔT increase R bb ρsw 12L e e + ρsw 6L e bc + ρc A contacts reduce base contact resistivity 4:1 reduce widths 2:1 & reduce length 2:1 constant R bb reducing widths 4:1, keep constant length reduced R bb Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

40 Back-of-Envelope FET Scaling Goal double transistor bandwidth when used in any circuit reduce 2:1 all capacitances and all transport delays keep constant all resistances, voltages, currents I d v exit ΔV ~ c v W ( V V ΔV ) eq exit ~ v exit Lg g ~ ( kt / m / μ gs th * 2 ) 1/ (non-degenerate) thin layers 2:1 1 / ceq ~ Tox / ε ox + Tw / 2ε c well eq doubled g ~ c v W reduce W g 2:1 g m, I d held constant m eq exit g C ~ c L W + α W reduce L g 2:1 C gs reduced 2:1 Cgs eq g g 1 dielectric fringing ( C gd Cs b, Cd b ) all proportional towg, ρ ρ L R c s S D s = + / Wg LS / D Wg g (C gd, C s-b, C d-b ) all reduced 2:1 reduce L s/d 2:1,reduce ρ c 4:1 (R s, R d ) held constant 2:1 vertical scaling 2:1 increased ( g m / W g ) 2:1 reduced W g 2:1 reduced fringing capacitances

41 FETs no longer scale well tunneling through h oxide high-k h dielectrics i (if feasible) Thin layers & low effective mass limit channel sheet charge density * ( E E ) qn / m f well * ( E E ) 1/ T 2 m well Low density of states limits drive current g m ~ c eq v W g where 1/ c eq c s well infinite well approximation high sheet-charge in thin well populate higher-mass band minima * e Solomon & Laux, 2001 IEDM 2 2 ~ (2) πh / q m + T / ε + T / 2ε density-of-states term dominates, limits ( g m / W g )and ( I d / W g ) fringing i & substrate t capacitances no longer scale, can dominate over C gs Thin quantum wells have low mobility Li SST 2005; Gold et al,, SSC 1987; Sakaki et al,, APL 1987 μ 2 6 ( E W ) T / well ox ox w well

42 InP DHBT: 500 nm Scaling Generation Z. Griffith h 21 U db f t = 450 GHz, f max = 490 GHz Hz 600 nm wide emitter, 120 nm thick collector, 30 nm thick base