GHz Bipolar ICs: Device and Circuit Design Principles

Transcription

1 Short Course, IEEE Bipolar / BiCMOS Circuits and Technology Meeting, 9 October 2011, Atlanta, Georgia GHz Bipolar ICs: Device and Circuit Design Principles Mark Rodwell, UCSB Munkyo Seo, Teledyne Scientific Collaborators: Teledyne HBT Team: M. Urteaga, R. Pierson, P. Rowell, B. Brar, Teledyne Scientific Company Teledyne IC Design Team: J. Hacker, Z. Griffith, A. Young, M. J. Choe, Teledyne Scientific Company UCSB HBT Team: V. Jain, E. Lobisser, A. Baraskar, J. Rode, H.W. Chiang, A. C. Gossard, B. J. Thibeault, W. Mitchell UCSB IC Design Team: S. Danesgar, T. Reed, Eli Bloch, H-C Park, J-H Kim rodwell@ece.ucsb.edu, mseo@teledyne-si.com

2 Motivation / Overview

3 DC to Daylight. Far-Infrared Electronics optical THz How high in frequency can we push electronics? microwave 3-30 GHz mm-wave GHz far-ir (sub-mm) 0.3-3THz mid-ir 3-30 THz near-ir THz Frequency (Hz)...and what would be do with it? THz radio: vast capacity bandwidth, # channels THz imaging systems Tb/s optical fiber links

4 THz Transistors: Not Only For THz Circuits 500 GHz digital logic fiber optics THz amplifiers THz radios imaging, sensing, communications precision analog design at microwave frequencies high-performance receivers Higher-Resolution Microwave ADCs, DACs, DDSs

5 ICs to 600 GHz : Teledyne and UCSB 570 GHz fundamental VCO M. Seo, TSC CSIC 2010 VEE Vtune VBB 340 GHz dynamic frequency divider M. Seo, TSC IEEE MWCL GHz low-noise amplifier M. Seo, TSC other ICs by J. Hacker 204 GHz static frequency divider (ECL master-slave latch) Z. Griffith, TSC CSIC 2010 Vout 300 GHz fundamental PLL M. Seo, TSC IMS GHz op-amp with 54 dbm IP3 at 2 GHz Z. Griffith, TSC IMS GHz 48 mw power amplifier T. Reed, UCSB CSIC 2011 Other ICs in design: GS/s track/hold optical PLLs coherent optical receivers 340 GHz arrays

6 At High Frequencies The Atmosphere Is Opaque Mark Rosker IEEE IMS 2007

7 Stage Voltage Gain, db THz Bipolar Transistors: Where Next? Stage Voltage Gain, db array transmitters: critical for sub-mm-wave radio / radar P P received transmit N N 16 2 receive transmit 2 R 32 x 32 array db increased SNR vastly increased range R e 340 GHz 670 GHz 1080 GHz HBT / HEMT integration for mixed-signal increasing f, f Frequency, Hz max, ( I bias / C load ) decreasing g m x, ( Rin Rload R Frequency, Hz out ) 100 MHz design frequency III-V NFET vs. Si PFET active loads: much lower C load /I bias 128 nm node: scaled interconnects high packing density speed, power 32 nm / 3 THz node, beyond Transition to production R&D pilot foundry design tools, reliability, scaled interconnects CMOS control integration: 3-D, flip chip

8 Bipolar Transistors: Models, Scaling Laws, State of Art, Roadmaps

9 Bipolar Transistor: Structure & Models R be / g m g qi nkt m E / C b c be C T T 2 b c je / 2v g / 2D n m " sat" ( ) c b T b / v thermal 1 2f base collector C je nkt qi E C bc nkt qi E R ex R coll

10 Base-Collector Distributed RC Parasitics R / ex contact, emitter A emitter emitter length L E R W / 12L spread R W / 4L gap s s e gap E E R W / 6L spread, contact s bc E R contact contact, base / A base_ contacts C A / T cb, e cb, gap emitter C A / T gap C A / T cb, contact c c base_ contacts c

11 R bb C cb Time Constant, F max, Simple Hybrid- model f max cb C C R cb, gap cb, e bb f ( R C ( R cbi contact 8R bb C contact C cbi cb, contact R R where R contact spread, contact spread, contact R R gap gap / 2) R spread Vaidyanathan & Pulfrey IEEE Trans. Elect. Dev. Feb ) R C C bb cbi cbi true total base resistance C : C cbx cbx true totalc ratio set tofit cb f max from above

12 tau ec, ps Key 2 nd -Order Effects in III-V HBTs: Omitted for Brevity C cb /A e (ff/m 2 ) J(mA/um^2) Current Voltage Partial -induced Ccb Degenerate velocity overshoot :decreases c Nakajima, Japanese Journal of Applied Physics, Feb modulation of cancellation by collector velocity modulation. Betser and Ritter, IEEE Trans. Elect. Dev., April 1999 Urteaga & Rodwell, IEEE Trans. Elect. Dev., July inverse current density, 1/J,m 2 /ma electron injection into base:increases Rodwell, Le, Brar, Proc IEEE, February 2008 Jain & Rodwell, IEEE Electron. Dev. Lett., to be published (2011) collector velocity :increases c J (ma/m 2 ) e More detailed information regarding III-V bipolar transistor physics and design: V 0.0 V 0.2 V V cb = 0.6 V R ex Fermi-Dirac Boltzmann Equivalent series resistance approximation V - be

13 Space Charge, Kirk Effect, Minimum C cb charging time SiGe HBT InP DHBT Collector Depletion Layer Collapse V cb 2, min ( qnd )( Tc / 2 ) Collector Field Collapse V cb ( J / v sat qn d )( T 2 c / 2 ) J 2 max 2v eff ( Vcb Vcb,min 2) / Tc Note that V be, hence ( V ) cb V ce C cb V LOGIC / I C A T V I collector c LOGIC Collector capacitance charging time minimized by setting J = J max...if so, charging time scales linearly with collector thickness. C V A LOGIC collector C V CE VCE,min Aemitter 2veff T

14 f (GHz) C cb /A e (ff/m 2 ) Space-Charge-Limited Current (Kirk effect) in BJTs J e (ma/m 2 ) I c (ma) Decreased ( f, f max ),increased at high J. Kirk threshold increases with increased V C cb 0.6 V cb 0.2 V 0.0 V cb cb -0.2 V cb f, -0.3 V cb ce. Increase in V dv di A ce c effective R L E ce, sat spacecharge current flux area W E with increased J is 2T C T A sat 2 c where the effective collector 2v effective J (ma/um 2 ) e V V V 4 3 V = 0.6 V cb J (ma/m 2 ) e A = 0.6 x 4.3 m 2 jbe V cb = 0 V Peak f t, f max I = 180 ua b step V (V) ce 5

15 b c I Bipolar Transistor Design T 2D 2 b T 2v c C A n sat cb c /Tc c, max vsatae ( Vce,operating V ce,punch-through ) / T T b 2 c We W bc emitter length L E T c T P L E 1 L ln W e e R ex contact / A e W W e bc Rbb sheet 12Le 6L e A contact contacts

16 b c Bipolar Transistor Design: Scaling T 2D 2 b T 2v c C A I n sat cb c /Tc c, max vsatae ( Vce,operating V ce,punch-through ) / T T b 2 c We W bc emitter length L E T c T P L E 1 L ln W e e R ex contact / A e W W e bc Rbb sheet 12Le 6L e A contact contacts

17 Breakdown is Never Less Than The Bandgap

18 Bipolar Transistors: Scaling Laws, Scaling Roadmap scaling laws: to double bandwidth HBT parameter change emitter & collector junction widths decrease 4:1 current density (ma/m 2 ) increase 4:1 current density (ma/m) constant collector depletion thickness decrease 2:1 base thickness decrease 1.4:1 emitter & base contact resistivities decrease 4:1 InP HBT scaling roadmap W e T b W bc T c emitter length L E 150 nm device

19 Recent InP HBT Results: Urteaga et al, DRC 2011

20 Gain (db) J e (ma/m 2 ) Recent InP HBT Results: Jain et al, DRC 2011 I c, I b (A) 30nm emitter, 30nm base, 100nm collector U H 21 f max = 1.0 THz f = 480 GHz 16 A = 0.22 x 2.7 m 2 je 12 I c = 12.1 ma 8 J = 20.4 ma/m 2 e P = 33.5 mw/m 2 4 V cb = 0.7 V Frequency (Hz) P = 20 mw/m 2 30 P = 30 mw/m 2 25 A = 0.22 x 2.7 m 2 20 je 15 I = 200 A b,step 10 5 BV V (V) ce Solid line: V = 0.7V 20 cb Dashed: V = 0V cb 15 n = 1.19 c 10 n = 1.87 b 5 I b I c V be (V)

21 Can we make a 1 THz SiGe Bipolar Transistor? Simple physics clearly drives scaling transit times, C cb /I c thinner layers, higher current density high power density narrow junctions small junctions low resistance contacts InP SiGe emitter nm width m 2 access base nm contact width, m 2 contact Key challenge: Breakdown 15 nm collector very low breakdown Also required: low resistivity Ohmic contacts to Si very high current densities: heat collector nm thick ma/m ? V, breakdown f GHz f max GHz PAs GHz digital GHz (2:1 static divider metric) Assumes collector junction 3:1 wider than emitter. Assumes SiGe contacts no wider than junctions

22 Interconnects

23 III-V MIMIC Interconnects -- Classic Substrate Microstrip Thick Substrate low skin loss W Zero ground inductance in package interconnect substrate Brass carrier and assembly ground IC with backside ground plane & vias 1 1/ H skin 2 r H No ground plane breaks in IC near-zero ground-ground inductance IC vias eliminate on-wafer ground loops High via inductance TM substrate mode coupling k z 12 ph for 100 m substrate GHz lines must be widely spaced ground vias must be widely spaced Strong coupling when substrate approaches ~ d / 4 thickness Line spacings must be ~3*(substrate thickness) all factors require very thin substrates for >100 GHz ICs lapping to ~50 m substrate thickness typical for 100+ GHz

24 Coplanar Waveguide No ground vias No need (???) to thin substrate Hard to ground IC to package +V +V +V 0V Parasitic microstrip mode ground plane breaks loss of ground integrity substrate mode coupling or substrate losses k z III-V: semi-insulating substrate substrate mode coupling -V 0V +V 0V Parasitic slot mode Silicon conducting substrate substrate conductivity losses Repairing ground plane with ground straps is effective only in simple ICs In more complex CPW ICs, ground plane rapidly vanishes common-lead inductance strong circuit-circuit coupling poor ground integrity loss of impedance control ground bounce coupling, EMI, oscillation 40 Gb/s differential TWA modulator driver note CPW lines, fragmented ground plane 35 GHz master-slave latch in CPW note fragmented ground plane 175 GHz tuned amplifier in CPW note fragmented ground plane

25 III-V MIMIC Interconnects -- Thin-Film Microstrip narrow line spacing IC density no substrate radiation, no substrate losses fewer breaks in ground plane than CPW... but ground breaks at device placements still have problem with package grounding InP 34 GHz PA (Jon Hacker, Teledyne)...need to flip-chip bond W thin dielectrics narrow lines high line losses low current capability no high-z o lines Z ~ 1/ o o 2 r H W H H

26 III-V MIMIC Interconnects -- Inverted Thin-Film Microstrip narrow line spacing IC density Some substrate radiation / substrate losses No breaks in ground plane... no ground breaks at device placements still have problem with package grounding InP 150 GHz master-slave latch...need to flip-chip bond thin dielectrics narrow lines high line losses low current capability no high-z o lines InP 8 GHz clock rate delta-sigma ADC

27 If It Has Breaks, It Is Not A Ground Plane! signal line line 1 signal line ground line 2 ground ground plane common-lead inductance coupling / EMI due to poor ground system integrity is common in high-frequency systems whether on PC boards...or on ICs.

28 No clean ground return? interconnects can't be modeled! 35 GHz static divider interconnects have no clear local ground return interconnect inductance is non-local interconnect inductance has no compact model 8 GHz clock-rate delta-sigma ADC thin-film microstrip wiring every interconnect can be modeled as microstrip some interconnects are terminated in their Zo some interconnects are not terminated...but ALL are precisely modeled InP 8 GHz clock rate delta-sigma ADC

29 VLSI mm-wave interconnects with ground integrity narrow line spacing IC density no substrate radiation, no substrate losses negligible breaks in ground plane negligible ground device placements Also: Ground plane at *intermediate level* permits critical signal paths to cross supply lines, or other interconnects without coupling. (critical signal line is placed above ground, other lines and supplies are placed below ground) still have problem with package grounding...need to flip-chip bond thin dielectrics narrow lines high line losses low current capability no high-z o lines

30 Modeling Interconnects, Passives in Tuned ( RF ) IC's Interconnects are tuning elements Narrow bandwidths precision is critical Initial IC simulation uses CAD-systems' library of passive element models. Final design: 2.5-Dimensional electromagnetic simulation of: lines, junctions, stubs, capacitors, resistors, pads GHz HBT amplifier, Urteaga et al, IEEE JSSCC, Sept GHz HBT amplifier, Urteaga et al, IEEE IMS, May GHz HBT amplifier, Agarwal et al, IEEE Trans MTT, Dec

31 Modeling Interconnects: Digital & Mixed-Signal IC's longer interconnects: lines terminated in Zo no reflections. Shorter interconnects: lines NOT terminated in Zo. But they are *still* transmission-lines. Ignore their effect at your peril! If length << wavelength, or line delay<<risetime, short interconnects behave as lumped L and C. L Z, 0 C / Z, l / v 0

32 Design Flow: Digital & Mixed-Signal IC's All interconnects: thin-film microstrip environment. Continuous ground on one plane. 2.5-D simulations run on representative lines. various widths, various planes same reference (ground) plane. Simulation data manually fit to CAD line model effective substrate r, effective line-ground spacing. Width, length, substrate of each line entered on CAD schematic. rapid data entry, rapid simulation. Resistors and capacitors: 2.5-D simulation RLC fit RLC model used in simulation.

33 Network analyzer Calibration... on-wafer LRL

34 On-Wafer Through-Reflect-Line (TRL) Calibration reference plane Through 225um 225um Through line should be long for large probe separation. Minimizes probe-probe coupling. Measurements normalized to the line characteristic impedance. Reflect open 225um short 225um Either open or short needed. Standards need not be accurate. "Open" must have G closer to that of open than that of short. Ports 1 & 2 must be symmetric. Line ΔL ΔL= 90 frequency. /8<ΔL<3/8 Device Under Test 225um 225um DUT Please see also:

35 On-Wafer TRL: Ongoing Issues High-f max transistors have very small ( C cb Y 12 S 12 ) Measurements show small background Y even with extended reference planes. Particular difficulty in extracting Mason's Unilateral gain. Corrupts f max measurement, model extraction. Measurements normalized to line Z 0....line impedance is complex at lower frequencies. must correct for complex Z o in measurements. excessive line resistance degrades precision. Z O R( j) jc jl TRL precision greatly impaired if lines couple to substrate; CPW line standards do not work well.

36 phase(s(2,1)) db(s(2,1)) db(s(1,2)) db(s(2,1)) db(s(1,2)) db(s(2,1)) db(s(1,2)) S(1,1) S(2,2) S(1,1) S(2,2) S(1,1) S(2,2) Verification of GHz TRL Calibration M. Seo Through Open Line freq (140.0GHz to 200.0GHz) freq (140.0GHz to 200.0GHz) freq (140.0GHz to 200.0GHz) freq, GHz freq, GHz m10 freq, GHz m10 freq= 150.0GHz phase(s(2,1))= freq, GHz

37 MSGMAG_dB_pfg MSGMAG_dB_ibm MAG/MSG, Um_ibm Um_pfg "Unilateral gain", linear Difficulties with GHz TRL Calibration Um_ibm_dB Um_pfg_dB "Unilateral gain", db Data on two layouts of 65 nm MOSFET E E11 ( K<1 ) 3E11 freq, Hz 4E11 5E11 6E11 7E11 1E12 9E11 8E freq, GHz U < 0 (!) Measured Y-parameters correlate reasonably with expected device model. Small errors in measured 2-port parameters result in large changes in Unilateral gain and Rollet's stability factor; neither measurement is credible. Y 12 appears to be the key problem. IC S ij measurements are fine. Transistor f max measurements are hard E11 2E11 10*log 10 U (?) U 3E11 freq, Hz Y21 Y12 4 G G G G 4E E E E E12 9E11 8E11

38 50+ GHz Mixed-Signal & ECL design: Principles & Examples

39 High Speed ECL Design Followers associated with inputs, not outputs Emitters never drive long wires. (instability with capacitive load) Double termination for least ringing, send or receive termination for moderate-length lines, high-z loading saves power but kills speed. Current mirror biasing is more compact. Mirror capacitance ringing, instability. Resistors provide follower damping.

40 High Speed ECL Design Layout: short signal paths at gate centers, bias sources surround core. Inverted thin film microstrip wiring. Key: transistors in on-state operate at Kirk limited-current. minimizes C cb /I c delay. Key: transistors designed for minimum ECL gate delay*, not peak (f, f max ). *hand expression, charge-control analysis Example: 8:1 205 GHz static divider in 256 nm InP HBT. 205 GHz divider, Griffith et al, IEEE CSIC, Oct. 2010

41 output power, dbm Feedback Factor, db mm-wave Op-Amps for Linear Microwave Amplification Reduce distortion with strong negative feedback linear response Griffith et al, IEEE IMS, June increasing loop bandwidth 10 increasing feedback 2-tone intermodulation R. Eden Frequency, Hz Even for 2 GHz operation, loop bandwidths must GHz. need very fast transistors input power, dbm physically small feedback loop; bias components surround active core.

42 mm-wave Op-Amps for Linear Microwave Amplification Griffith et al, IEEE IMS, June current-mode analog design...node impedances kept low with transimpedance loading high bandwidth Virtual-ground input stage, Miller feedback around output stage, makes feedback insensitive to generator & load impedances....critical for stability in a 50 GHz loop! (what will the op-amp be connected to?) Z t -stage and loop nesting for high gain even with fast resistor-loaded circuits

43 mm-wave Op-Amps for Linear Microwave Amplification Griffith et al, IEEE IMS, June Griffith et al, IEEE IPRM, May. 2008

44 40 GSample/s Sample/Hold *Design* master-slave track-hold target 40 GS/s, 6 b (??) 256 nm InP HBT Saeid Daneshgar ECL ECL TAS TIS ECL layout: ECL buffer. layout: TASTIS. Bias and transmission-line design strongly follows controlled-impedance ECL examples.

45 RF-IC design Principles & Examples

46 RF-IC Design: Simple & Well-Known Procedures MSG/MAG, db 1: (over)stabilize at the design frequency guided by stability circles 2: Tune input for F min (LNAs) or output for P sat (PAs) 3: Tune remaining port for maximum gain 4: Add out-of-band stabilization. There are many ways to tune port impedances: microstrip lines, MIM capacitors, transformers Choice guided by tuning losses. No particular preferences. 30 U For BJT's, MAG/MSG usually highest for common-base. preferred topology Common-base gain is however reduced by: base (layout) inductance emitter-collector layout capacitance Common emitter Common Collector Common base Frequency, GHz

47 Power Amplifier Design (Cripps method) Current, ma For maximum saturated output power, & maximum efficiency device intrinsic output must see optimum loadline set by: max 8 1 V max V min I max breakdown, maximum current, maximum power density. P mw breakdown mw V ce or V ds (V) parasitic C's and R's represented by external elements... ammeter monitors intrinsic junction current without including capacitive currents...(v collector -V emitter ) measures voltage internal to series parasitic resistances...

48 m) ncy (%) Output Output power power (dbm), (dbm) Gain (db) Power Added Efficiency (%) S-parameter (db) 10 3-stage 150-GHz Amplifier; IBM 65 nm CMOS K-factor S Stability Frequency (GHz) factor (K) S11 (sim) 140 Frequency 160 (GHz) GHz -20 Frequency (GHz) 153 GHz GHz Frequency (GHz) GHz 153 GHz GHz S21 S11 (meas) Frequency (GHz) Acknowledgement: IBM M. Seo, B. Jagannathan, J. Pekarik, M. Rodwell, IEEE JSSCC, Dec S21(meas) S21(sim) S21 (measured using power sensor) S11 (meas) S11 (sim) S22 (meas) S22 (sim) Dummy-prefilled microstrip lines S21(meas) S21(sim) S21 (measured S11 (meas) S11 (sim) S22 (meas) S22 (sim) 10 5 Gain P out 153 GHz 153.0GHz GHz GHz GHz GHz PAE Input power (dbm) 25 20

49 220 GHz, 48 mw HBT Power Amplifier T. Reed et al, IEEE CSIC, Oct. 2011, to be presented. 4-cell design: P sat > GHz schematic of single cell 8-cell design: not yet fully tested: P sat =? Technology: Teledyne 250 nm InP HBT Right-side-up thin-film microstrip wiring. Breaks in ground plane minimized.

50 High Frequency Bipolar IC Design Next: TMIC designs for 340 GHz, 670 GHz transceivers. Digital, mixed-signal, RF-IC (tuned) IC designs----at very high frequencies Even at 670 GHz, design procedures differ little from that at lower frequencies: classic IC design extends readily to the far-infrared. Key considerations: Tuned ("RF") ICs Rigorous E&M modeling of all interconnects & passive elements Continuous ground plane required for predicable interconnect models. Higher frequencies close conductor planes higher loss, lower current Key considerations: digital & mixed-signal : Transmission-line modeling of all interconnects Continuous ground plane required for predicable interconnect models. Unterminated lines within blocks; terminated lines interconnecting blocks. Analog & digital blocks design to naturally interface to 50 or 75.