ECE 145A / 218 C, notes set xx: Class A power amplifiers

Transcription

1 ECE 145A / 218 C, notes set xx: Class A power amplifiers Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu , fax

2 Class A power amplifier: what do we mean? PA has input, output tuning loadline would be as so

3 Transistor Output Characteristics: Real 250nm InP HBT mW/um 2 5mW/um 2 J e (ma/ m 2 ) V (V) ce 500nm InP HBT Current, ma mw breakdown mw V ce or V ds (V)

4 Transistor Output Characteristics: Idealized " V knee "or " Vsat" I max V br : breakdown Minimum voltage: V Maximum voltage: V Maximum current : FETs : I bipolars : max I W max g max, # gate fingers L e sat I br, # emitter fingers

5 Transistor Output Characteristics: Real " V knee "or " Vsat" I max V br : breakdown V V br sat varies with current varies with current Subsequent lecture notes are therefore somewhat idealized

6 Transistor Output Characteristics: Power Transistor power V ce c or V DS Constant power : hyperbola on I I I D out, V out plane J e (ma/ m 2 ) mW/um 2 5mW/um 2 Case1: low - frequency power amp frequency (thermal time constant) loadline must lie below maximum power density curve V (V) ce Case 2 : high - frequency power amp frequency (thermal time constant) *bias point * must lie below maximum power density curve -1

7 Device Bandwidth vs Operating Point bipolar transistors : Z. Griffith, 2012 IPRM Low voltage, high current : "Kirk effect" space - charge - limited current reduction in ft, increase in Ccb reduced bandwidth High voltage : all semiconductors : push - out of collector depletion region III- V semiconductors : reduction of electron velocity in collectror reduction in ft,*de*crease in Ccb reduced bandwidth

8 Device Bandwidth vs Operating Point: FETs Variations of g m, C gs, f t, over loadline.

9 Device Bandwidth vs Operating Point: FETs Increased drain bias increased drain depletion increased transit time, decreased C, decreased gd G ds Also : variation of gm with current. Low at both low currents and high currents Current Density (ma/ m) L g = 25 nm I on = 500 A/ m (at I =100 na/ m, V =0.5 V) off DD V DS = 0.1 to 0.7 V 0.2 V increment Gate Bias (V) g m (ms/ m)

10 Operating areas Safe operating area standard terminology region bounded by power, V br, I max fast operating area not standard terminology region with adequately high f t, f max Loadline must lie within both

11 Oversimplified SOA/FOA; for class Maximum, minimum voltages Maximum current Wg or L E

12 Simple class A power analysis Bias point in center of rectangle. Loadline reaches corners of rectangle Z P P L DC ( V V RF,max max DC I ( V V DC max min ) / ( V V max min max V ) I max min / 8 ) I max / 4 maximum drain/collector efficiency I drain/collector P RF,max / P DC 1/ 2

13 Power-added efficiency P.A.E. ( P P P out DC out 1 P in P P ) / in out P DC drain/collector 1 1 gain Noting that Pout for one stage is Pin for the next, if we have a chain of PAs with identical PAE, **at that specific operating RF power **, then the PAE of the cascade will be that of the individual PAs.

14 Power Amplifier Design For highest efficiency, each stage should be loaded with Z L opt, ( Vmax Vmin ) / I max The interstage networks are tuning networks, not matching networks. Thus far, we have neglected transistor parasitics.

15 Loadline: inclusive of transistor parasitics Transistors have resistive, capactive parasitics. It is the *internal* ( I C, V ) or ( I Loadline current must be electron current, not CE ) which must follow the above loadline. Current meters must be placed inside the capactive parastics. How do we do this? D, V DS C dv / dt displacement current.

16 Loadline: inclusive of transistor parasitics Read the CAD device model determine transistor capacitances. Add external negative capacitances to cancel these. Add voltmeter and current meter. These correctly measure the loadline Then add external positive capacitances.

17 Example of ammeter, voltmeter placement Here I took the CAD model and 1) created a variant with zero C 2) used this for the active transistor model. 3) created a second variant with C 4) created a third variant with C In this manner, voltage variation of, zero C cbx only only. the capacitances is correctly accounted for. cb cbi c, sub parasitic C's and R's represented by external elements... ammeter monitors intrinsic junction current without including capacitive currents...(v collector -V emitter ) measures voltage internal to series parasitic resistances...

18 Power Amplifier Methodology The above technique, direct loadline method known as the Cripps technique requires that you know, add, subtract capacitances. Alternate techniuque : load pull Empirical, not analytical will cover in a few slides contours

19 Power Amplifier Design (Cripps Method) Design steps are 1) input stabilization (in-band) 2) output tuning for correct load-line 3) input tuning (match) 4) out-of-band stabilization Example: 60 GHz, 30 mw PA, 130 nm BiCMOS

20 Power Amplifier Design Example Power amplifier *cell*. 20micron emitter finger. bias : Ic 10mA, Vcb 1.86 Volts V CE 2.5V. The biasing technique used is just for CAD experimentation; not practical The inactivated output LC network is a bandpass filter

21 Power Amplifier Design Example First, simulate the transistor vs frequency at the bias point, determine fmax, MAG/MSG at the design frequency. determine the stability factor at the design frequency if unstable, stablize (input network) at the design frequency

22 PA example: output network Note the output network : ideal transformer plus parallel inductance. This is not the final ouput network :it is used to quickly find Y L,opt.

23 PA example: measuring the loadline Dropping down in the heirarchy into the device model, we see the monitoring ammeter plus negative and positive Ccb.

24 PA example: finding the optimum load The input is not yet matched, and the load is not yet tuned. We drive the transistor with a large drive signal and observe the loadline

25 Power Amplifier Design Example With noinductive tuning, and with a 1:1 transformer ratio, The loadline initially looks like this :

26 Power Amplifier Design Example First add the inductive tuning, adjusting the shunt L to eliminate loadline looping

27 Power Amplifier Design Example Then adjust the tnansformer ratio to obtain a loadline passing through the target endpoints ( V min, I max ) and ( V max, I min 0A) We had expected a straight line. The looping (3per cycle) is 3rd harmonic generation

28 Power Amplifier Design Example We have now determined Y We then (not shown), in a separate circuit simulation file, design a practical output network which providesy opt We then add this to the PA.. opt.

29 Power Amplifier Design Example Remaining steps : Input matching network Out - of - band stabilization (ece145a) Often : filters to suppress 2nd, 3rd harmonics.

30 Power Amplifier Design Example Here is our final simulated performance

31 Load pull method We can also empirically determine (in CAD, or with instruments) the load impedance giving the largest saturated Pout. We then use this impedance for our PA design

32 Load pull method We can also empirically determine (in CAD, or with instruments) the load impedance giving the largest saturated Pout. We then use this impedance for our PA design Keysight ADS has pre - configured test benches I suspect that other CAD packages do, too. I prefer the Cripps method. to do this.

33 The power-combiner problem Output power : P Necessary load impedance: R So, output power out P ( V out max ( V V max min L V ) I ( V min max ) max 2 / 8 V / 8R L min ) / I max High - frequency transistors have low V max. High or High P P out out requires very low R requires* power - combining* L,

34 Minimum load impedance Transmission lines have some minimum Z line,min See ECE145A notes : width, lateral modes, junction parasitics, high skin loss.. Impedance transformation permits But high Z load : Z line,min increased line losses. Z load line,min ratios increase the line's VSWR Z Z load much below10 will incur high losses

35 Parallel Power-Combining Output power: P OUT = N x V x I Parallel connection increases P OUT Load Impedance: Z OPT = V / (N x I) Parallel connection decreases Z opt High P OUT Low Z opt Needs impedance transformation: lumped lines, Wilkinson,... High insertion loss Small bandwidth Large die area 35

36 from J Buckwalter's 145c notes Wilkinson Power-Combiner Lines are one quarter - wavelength Does provide 2 :1combining, 50Ohm ports. But : Lines are long : large die area Lines are long, hence lossy : loss in power, efficiency

37 Corporate Wilkinson Power-combiner Assume :all these lines are 2 50 impedance Assume :all these lines are quarter - wavelenght. Then : this is a 3-stage Wilkinson power - combiner Then : we have 8 :1power - combining

38 Corporate Wilkinson Power-combiner Corporate Wilkinson combiners are common in textbooks. Corporate Wilkinson combiners are* rare* in ICs. Why? Very long lines. Large die area. High losses

39 Corporate Power-combiners: Non-Wilkinson Real IC power - combiners look like this. The structure is corporate. But, the lines are not 71Ohms And, the lines are much shorter than guide / 4. Shorter lines : less loss, smaller IC.

40 Design of Non-Wilkinson Combiners Even-mode equivalent circuit The equivalent circuit :a multi - section transmission - line transformer. Shunt elements (inductors, capacitors) can also beadded. Line parameters are adjusted to reach Z l,opt and to match input. CAD approach : all similar lines defined by shared variables, simultaneously adjusted

41 Design: Multi-Finger Amplifiers: spatial mode instabilities If each transistor finger is individually stabilized, high-order modes are stable. Amplifier layout usually does not allow sufficient space for this. All spatial modes must then be stabilized. etc... Stabilization method: bridging resistors parallel loading to higher-order modes Select so that (Z S, Z L ) presented to device lie in the stable regions

42 Examples: PAs with corporate combining W-band InP HBT power amplifier - UCSB 34 GH InP HBT power amplifier - Rockwell mm-wave InP HBT power amplifier - Rockwell

43 220 GHz 180mW Power Amplifier (330 mw design) 2.3 mm x 2.5 mm T. Reed, Z. Griffith et al 2013 CSIC symposium 43

44 Transformers for impedance transformation Here the transformer changes (decreases) the real part of the load admittance. Additional tuning elements used toadjust Im(Y L ) Transformers have extensive parastics and require careful electromagnetic modeling

45 Transformers for power combining Here the transformers combine power from 2 cells. Each cell sees1/2 the load impedance The transformer primary can besegmented to extend to N - way combining I. Aoki et al. IEEE JSSC,March 2002

46 Parallel Power-Combining Output power: P OUT = N x V x I Parallel connection increases P OUT Load Impedance: Z OPT = V / (N x I) Parallel connection decreases Z opt High P OUT Low Z opt Needs impedance transformation: lumped lines, Wilkinson,... High insertion loss Small bandwidth Large die area 46

47 Series Power-Combining & Stacks Parallel connections: I out =N x I Series connections: V out =N x V Output power: P out =N 2 x V x I Load impedance: Z opt =V/I Small or zero power-combining losses Small die area How do we drive the gates? Local voltage feedback: drives gates, sets voltage distribution Design challenge: need uniform RF voltage distribution need ~unity RF current gain per element...needed for simultaneous compression of all FETs. M. Shifrin, Y. Ayasli, and P. Katzin, 1992 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symp. M. Rodwell and S. Jaganathan, U.S. Patent 5,945,879, Aug. 31, S. Pornpromlikit, H.-T. Dabag, B. Hanafi, J. Kim, L. Larson, J. Buckwalter, and P. Asbeck, 2011 IEEE CSIC Symp. 47

48 3-conductor transmission Lines Two separate transmission lines (m 3 -m 2, m 2 -m 1 ) E, H fields between m 3 and m 1 perfectly shielded TU3B-1 IMS2014, Tampa, 1-6 June, 2014

49 Standard λ/4 Baluns: Series Combining Z stub Balun combiner: voltages add 2:1 series connection each source sees 25 double I max for each source 4:1 increased P out Standard /4 balun : /4 stub open circuit long lines high losses long lines large die 49

50 Sub-λ/4 Baluns for Series Combining What if balun length is << /4? Stub becomes inductive Sub- /4 balun : stub inductive tunes transistor C out short lines low losses short lines small die 50

51 Sub-λ/4 Baluns for Series Combining 2:1 baluns: 2:1 series connection Each device loaded by 25 HBTs are 2:1 larger than needed for 50 load. 4:1 increased P out. Sub /4 balun: inductive stub balun inductive stub tunes HBT C out. Similar network on input. 51

52 Sub-λ/4 Balun Series-Combiner: Design Each HBT loaded by 25 HBT junction area selected so that I max =V max /25 Each HBT has some C out. Stub length picked so that Z stub =-1/jwC out tunes HBT P out 4 2 V max :1 more power than without combiner. 52

53 Baluns in Real ICs 1) 2) M μm M 1 -M 2 Capacitors M 1 -M 2 Line 86 μm 124 μm M 2 91 μm 42 μm HBTs M 1 thickness: 1 μm 3) 4) M 2 -M 3 Line 52 μm M 1 -M 2 gap: 1 μm M 2 thickness: 1 μm M 2 -M 3 Sidewalls 12 μm 10 μm M 2 -M 3 gap: 5 μm M 3 thickness: 3 μm 1) M 1 as a GND 2) Slot-type transmission lines (M 1 -M 2 ), AC short (2 pf MIM) 3) Microstrip line (M 2 -M 3 ), E-field shielding NOT negligible 4) Sidewalls between M 3 -M 1 (Faraday cages), /16 length TU3B-1 IMS2014, Tampa, 1-6 June,

54 PA Designs Using 2:1 Balun 54

55 16:1 PA Using 4:1 Baluns 4:1 series-connected power-combining Each HBT loaded by 12.5 HBT junction area selected so that I max =V max /12.5 P out 16 2 V max 8 50 Each HBT has some C OUT Stub length picked so that Z stub =-1/jwC out tunes HBT 16:1 more power than without combiner. TU3B-1 IMS2014, Tampa, 1-6 June,

56 PA IC Schematic (2-stages) 2-stage PA using 2:1 and 4:1 baluns 1 st stage 2 nd stage Long lead lines Z load Z load TU3B-1 IMS2014, Tampa, 1-6 June,

57 PA IC Die Image (2-stages) IC Size: 1.08 x 0.98 mm 2 TU3B-1 IMS2014, Tampa, 1-6 June,