RFIC DESIGN ELEN 351 Session4

Transcription

1 RFIC DESIGN ELEN 351 Session4 Dr. Allen Sweet January 29, 2003 Copy right 2003 ELEN 351 1

2 Power Amplifier Classes Indicate Efficiency and Linearity Class A: Most linear, max efficiency is 50% Class AB: linear, max efficiency is 60% Class B: More nonlinear, max efficiency is 75% Class C: Very nonlinear, max efficiency is 85% Classes D, E, F: Switching modes, 85-95% Copy right 2003 ELEN 351 2

3 Linearity Metrics Scaled Linearity = (OIP3 P-1 db) Linear Efficiency = 10 LOG (OIP3/Pdc) Adjacent Channel Power Ratio = (Main Channel average power Adjacent Channel average power) Copy right 2003 ELEN 351 3

4 GaAs HBT Performance Expectations PAE: Matched/Feedback amps:45% to 65%, Darlington amps: 15% to 25% (OIP3 P-1 db): 10 db to 20 db 10 LOG (OIP3/Pdc): 5 db to 15 db ACPR: 50 db to 65 db Copy right 2003 ELEN 351 4

5 Matching for Maximum Gain Zl Copy right 2003 ELEN 351 5

6 Smith Chart Display of S11 and S22 and Zl for Maximum Pout Match for Gain Match for Power Copy right 2003 ELEN 351 6

7 MESFET Power Amplifier Load Line Analysis Copy right 2003 ELEN 351 7

8 Load Line Resistance Calculation With no Restrictions on Voltage Copy right 2003 ELEN 351 8

9 Load Line for a One Finger GaAs HBT Using the G.P Model Bias Point Bias Point Copy right 2003 ELEN 351 9

10 Calculate HBT PA Load Line Resistance Based on Pout Assume the Requirement is for Pout=1 watt from a class A amplifier. Assume 50% conversion efficiency and Vcc=6.0 volts. Pdc=2 watts, and Ic=2watts/6 volts= 333 ma. The number of emitter fingers is N=333/10 = 33 fingers. Load Resistance = Rl = 580/33 = 17.5 Ohms Copy right 2003 ELEN

11 Pure Class A Load Line Analysis Copy right 2003 ELEN

12 Simulated Wave Forms for Pure Class A Operation Copy right 2003 ELEN

13 Simulated Pin vs Pout for Pure Class A Operation Copy right 2003 ELEN

14 Class AB Operation (Low DC Current) Copy right 2003 ELEN

15 Class AB Current and Voltage Wave Forms Copy right 2003 ELEN

16 Pin vs Pout for Class AB Operation Copy right 2003 ELEN

17 Load Line Analysis for Low Voltage Class A Operation Copy right 2003 ELEN

18 Current and Voltage Wave Forms for Low Voltage Operation Copy right 2003 ELEN

19 Pin vs Pout for Low Voltage Operation Copy right 2003 ELEN

20 Ways to Test an Amplifier s Stability/Instability K factor: K>1.0 is Unconditionally stable, 0<K<1.0 is conditionally stable, and K<0 is Unstable. S11 or S22 greater than 1.0 (or positive if expressed in db s) is unstable. Stability circles (ADS element under Simulation-S parameter Palette) Show Unstable Impedance Regions. BE SURE TO TEST STABILITY OVER A WIDE RANGE OF FREQUENCIES. Copy right 2003 ELEN

21 Circuit Elements which Enhance an Amplifier s Stability Parallel or Series Feedback. Place a series R-L network in shunt with the amplifier s input, to cure low frequency instabilities. Place a series R-C network in shunt with the amplifier s input to cure high frequency instabilities. Copy right 2003 ELEN

22 Amplifier Stability Analysis Demonstrating a Problem Copy right 2003 ELEN

23 Improved Stability after Modifying Component Values Copy right 2003 ELEN

24 Simulating Power, Linearity and DC with ADS Harmonic Balance Use Harmonic Balance and a One Tone Frequency Source to Simulate Pin vs Pout. Use Harmonic Balance and an N Tone Frequency Source to Simulate OIP3. Use DC Control Icon to Annotate DC conditions. Copy right 2003 ELEN

25 ADS Harmonic Balance Schematic For Simulating Pin vs Pout Name output node on Schematic Vout Copy right 2003 ELEN

26 ADS Display Trace Expression for Pin vs Pout Choose dbm, Not db for power Copy right 2003 ELEN

27 ADS Harmonic Balance Schematic for Simulating OIP3 Note: be sure to Name the output Node vout Copy right 2003 ELEN

28 ADS Display Trace for OIP3 Simulations Copy right 2003 ELEN

29 Types of GaAs HBT PAs Darlington: Simple, Inherently Stable, Medium Power, 15% to 25% Efficient, Very Broad Bandwidth. Minimum off chip components Feedback: Simple, High Power, High Efficiency (50% to 60%), Some off chip Components Required. Balanced: +3 db Power Combining, Inherently Good in/out matches, Many off chip components. Push Pull: +3 db Power Combining, Natural Impedance Transformation for matching. Off chip Copy right 2003 ELEN

30 Darlington Amplifiers Simple Topology: Two Transistors, 4 Resistors, No on chip Capacitors, No on chip Inductors. Flat, Broadband Gain Response Extends down to D.C. and Rolls off at a High Corner Frequency determined by the device sizes. Inherently Stable. Power and OIP3 trade off with corner Frequency. Device Area determines Gain and Power. Gain to 20 db, P-1 db to +25 dbm, OIP3 to +45 dbm, but not all at once. Use for Low and Medium Power Stages. Copy right 2003 ELEN

31 Darlington Amplifier Topology OUT IN Vbe for both Transistors must be About 1.4 volts Normally Zero Ohms Copy right 2003 ELEN

32 Darlington Amplifier Frequency Response Copy right 2003 ELEN

33 Homework #3: A Darlington Amplifier with Layout Parasitic Elements Copy right 2003 ELEN

34 Darlington Amplifier DC Simulation Copy right 2003 ELEN

35 Menu Pick for DC Annotation Copy right 2003 ELEN

36 Blow up of Darlington Circuit R1 Input Pad Base Line Q1 Collector line R2 R3 Emitter Base Line Q2 R5 Output Pad Copy right 2003 ELEN

37 Darlington Amplifier Simulated Performance Peaking is caused By transmission lines In the transistors bases Copy right 2003 ELEN

38 Darlington Schematic for Simulating OIP3 Copy right 2003 ELEN

39 Darlington OIP3 Simulation dbm Linearity Metrics: (OIP3 P-1) = 10 db 10LOG(OIP3/Pdc)=5 db Copy right 2003 ELEN

40 Darlington Schematic for Simulating Pin vs Pout Copy right 2003 ELEN

41 Simulated Pin vs Pout for the Darlington Amplifier P-1 db PAE=21 % Copy right 2003 ELEN

42 Darlington Amplifier Layout W=50 microns Resistors have A Resistance in Ohms equal to Their length in microns Copy right 2003 ELEN

43 Layout Detail 1 M1 to M2 VIA Copy right 2003 ELEN

44 Layout Detail 2 M1 to M2 VIAS Copy right 2003 ELEN

45 Feedback Amplifiers Highest Power, Efficiency, and Linearity. Feedback promotes Stability and Suppresses Harmonics and Spurious signal. Well matched over Narrow Band Segments only. Output Matching is done off chip to reduce losses at the high power side of the Amplifier PAE up to 60%. P-1 db up to +32 dbm OIP3 up to +50 dbm Copy right 2003 ELEN

46 Feedback Amplifier Topology with Resistive Base Bias Copy right 2003 ELEN

47 Feedback Amplifier Topology with Current Mirror Base Bias for Improved Temp Stability Copy right 2003 ELEN

48 Layout of a Large (A=24) Transistor Copy right 2003 ELEN

49 Ballast Resistors in Large Transistors Copy right 2003 ELEN

50 Balanced Amplifiers Power Combine any two Identical Amplifiers to Double their Output Power. Excellent Broadband Match, no matter how poorly the individual Amplifiers are Matched. Many off chip components, some are Large. Copy right 2003 ELEN

51 Balanced Amplifier Topology Reflections Reflections Copy right 2003 ELEN

52 Push Pull Amplifiers Power Combine any two Identical Amplifiers to Double their Power output. Push Pull Topology uses Baluns or Transformers that provide a natural Impedance Transformation for Matching. A 2:1 Impedance ratio Transformer provides a 4:1 Matching Impedance Ratio. The Virtual Ground Along the Amplifier s Center line can simplify layout by eliminating the need for some Substrate Via Grounds. Many Off Chip Components, some are Large. Copy right 2003 ELEN

53 Push Pull Amplifier Topology Virtual ground point N:1 50/2N 50/2N N:1 50/2N 50/2N Copy right 2003 ELEN