RFIC Design ELEN 351 Lecture 1: General Discussion

Transcription

1 RFIC Design ELEN 351 Lecture 1: General Discussion Instructor: Dr. Allen Sweet Copy right 2003, ELEN351 1

2 General Information Instructor: Dr. Allen Sweet Home work/project submissions: Place all schematics, graphics, and layouts in a power point or ms word file and to instructor. Hard copy is also acceptable. Grade: Based on homework, midterm, and project. Reference books: See handout list for suggestions. Copy right 2003, ELEN351 2

3 Recommended General Software Ms Word Ms Power Point Snagit utility (demo at APPCAD (Available from Agilent) Copy right 2003, ELEN351 3

4 Simulator Options ADS by Agilent Ansoft Serenade (RF package is called Harmonica). Student version is available at ex.cfm Note: the student version is limited to only 25 nodes and 2 transistors. Genesys by Eagleware Golden Gate by Xpedian Copy right 2003, ELEN351 4

5 Layout tool Options ICEditor (demo is available at however files cannot be saved) Mentor Graphics Cadence AutoCAD Fast CAD (demo is available at ) Copy right 2003, ELEN351 5

6 Course Outline General RF/wireless concepts, simulators, simple design example. Receiver/Transmitter architectural options Layout techniques PA Design LNA Design Mixer Design VCO Design Battery issues and tradeoffs, economics of RFICs Technology comparison Copy right 2003, ELEN351 6

7 What is an RFIC? Any integrated circuit for used in the frequency range: 100 MHz to 6 GHz. Generally RFIC s contain the analog front end of a radio transceiver, or some part of it. RFIC s can be the simplest SP1T switch, up to the whole front end of a radio transceiver. RFIC s are fabricated in a number of technologies: Si Bipolar, Si CMOS, GaAs HBT, GaAs MESFET/HEMT, and SiGe HBT are today s leading technologies. Copy right 2003, ELEN351 7

8 Typical Applications for RFICs Cellular / PCS phones Cellular / PCS infrastructure WLANS GPS BlueTooth Wireless PDAs Mobile Communications Copy right 2003, ELEN351 8

9 Basic Radio Link Copy right 2003, ELEN351 9

10 Path Loss Defines the Received RF Signal Level (In db s) Signal to Noise ratio Copy right 2003, ELEN351 10

11 Shannon s law gives Maximum Data Rate in an RF Channel Rmax = BW LOG2( 1 + S/N), where BW is the RF channel s bandwidth in MHz and Rmax if the Maximum possible data rate for this channel in MBits per second. All practical MOD- DEMOD systems can only approach Shannon s limit. Radio Spectrum is a precious commodity! It must be used wisely, to handle the growing amount of wireless information flow. Copy right 2003, ELEN351 11

12 Multiple Access Techniques Conserve Valuable Spectrum Frequency Division Multiple Access (FDMA) Time Division Multiple Access (TDMA) Code Division Multiple Access (CDMA) Copy right 2003, ELEN351 12

13 FDMA Copy right 2003, ELEN351 13

14 TDMA Data Packets Copy right 2003, ELEN351 14

15 CDMA Copy right 2003, ELEN351 15

16 Block Diagram of a CDMA System Note: Spreading and De Spreading codes are identical Copy right 2003, ELEN351 16

17 Two Port S Parameters Copy right 2003, ELEN351 17

18 Types of Device Models S Parameter: Limited to small signal gain and match analysis only. Equivalent Circuit: Same limitations as the S Parameter Model, except it is scalable with area. Load Pull Impedance: For PA design, limited in usefulness to output circuit design only. Large Signal Model: No limitations, this is the most useful class of models.with these models, ALL measurable parameters can be simulated. Copy right 2003, ELEN351 18

19 Types of Large Signal Models GaAs HBT: Gummel-Poon, and VBIC GaAs MESFET: Curtice, TOM, Materka, Statz, Tajima, GaAs HEMT: EE_HEMT Si Bipolar: Gummel-Poon CMOS: Many Copy right 2003, ELEN351 19

20 The Impedance Smith Chart LINES OF CONSTANT REACTANCE INDUCTIVE SHORT (RESISTIVE AXIS) OPEN Z0 POINT CAPACITIVE CIRCLES OF CONSTANT RESISTANCE Copy right 2003, ELEN351 20

21 Impedance locus of a 10 ohm Resistor in series with a 5 nh coil Copy right 2003, ELEN351 21

22 Impedance locus of a 10 ohm Resistor in series with a 5 pf cap Copy right 2003, ELEN351 22

23 Impedance locus of an ideal 50 Ohm transmission line, Grounded at one end Copy right 2003, ELEN351 23

24 RFIC Design Process Steps Specifications Identify Topology options (literature search) Choose a Foundry Obtain Foundry s Device Models and Design Rules Initial Simulations Choose final Topology Stability Analysis (Amplifiers only) Temperature Analysis Copy right 2003, ELEN351 24

25 RFIC Design Process Steps, Continued Initial Layout Include all Layout Parasitic elements in Topology Minimize Layout Area, Preserving Performance The Art of the Trade Off Complete Final Layout Create Test Cells for Critical Circuit Blocks DRC at the Foundry Assemble the Reticle, Tapeout Mask Making, Wafer Fabrication Copy right 2003, ELEN351 25

26 Homework Assignment #1: Simulate the following Amplifier Copy right 2003, ELEN351 26

27 BIAS CHOKE Circuit Details: FEEDBACK RESISTOR INPUT BLOCKING CAP OUTPUT BLOCKING CAP TRANSISTOR AREA=3 FINGERS BASE BIAS STABILIZING RESISTOR Copy right 2003, ELEN351 27

28 Gummel Poon InGaP/GaAs HBT Device Model: 2x12 micron emitter finger Copy right 2003, ELEN351 28

29 Simulated Gain/Match/DC Conditions GAIN OUTPUT MATCH INPUT MATCH Copy right 2003, ELEN351 29

30 Smith Chart Display: Amplifier s Input and Output Impedances OUTPUT IMPEDANCE INPUT IMPEDANCE Copy right 2003, ELEN351 30

31 Simulated Noise Figure Copy right 2003, ELEN351 31

32 Simulated Stability Factor (K) Copy right 2003, ELEN351 32