Frequency Limits of Bipolar Integrated Circuits

Transcription

1 IEEE MTT-S Symposium, June 13, 2006 Frequency Limits of Bipolar Integrated Circuits Mark Rodwell University of California, Santa Barbara Collaborators Z. Griffith, E. Lind, V. Paidi, N. Parthasarathy, U. Singisetti ECE Dept., University of California, Santa Barbara M. Urteaga, R. Pierson, P. Rowell, B. Brar Rockwell Scientific Company Sponsors J. Zolper, S. Pappert, M. Rosker DARPA (TFAST, ABCS, SMART) I. Mack, D. Purdy, Office of Naval Research , fax

2 THz Transistors: What does this mean? What are they for? How do we make them?

3 What could we do with a THz Transistor? High-Resolution Microwave ADCs and DACs mm-wave radio: 40+ Gb/s on 250 GHz carrier 340 GHz imaging systems 320 Gb/s fiber optics Why develop transistors for mm-wave & sub-mm-wave applications? compact ICs supporting complex high-frequency systems.

4 THz Transistors: What does this mean? A 1 THz current-gain cutoff frequency (f τ ) alone has little value a transistor with 1000 GHz f τ and 100 GHz f max cannot amplify a 101 GHz signal RF-ICs & MIMICs need high power-gain cutoff frequency (f max ) also need high breakdown & high safe operating area (power density) 100+ GHz digital also needs low (C depletion ΔV / I ) and low (I*R parasitic /ΔV ) So, how do we make a transistor with >1 THz f τ, >1 THz f max <50 fs CΔV / I charging delays and < 100 mv (I*R parasitic ) parasitic voltage drops?

5 THz Transistors: How do we make them?

6 Present Status of Fast III-V Transistors f max (GHz) 200 GHz GHz 400 GHz Updated July GHz 500 nm = 250 nm f t (GHz) f max f τ RSC UIUC_SHBT NTT_fmax Fujitsu HEMT SFU UIUC_DHBT UCSB 500 nm NGST Pohang HRL IBM SiGe Vitesse UCSB 250 nm popular f ( f τ (1 τ f f power amplifiers: PAE, associated gain, mw/ μm low noise amplifiers: F or + τ digital : f τ ( C ( R ( R ( τ min b f f max max + 1 clock cb ex bb f max ) / 2, associated gain, I, hence I c c + τ / ΔV ), / ΔV ), c f ) alone max much better metrics : ΔV / I c ) 1 ), metrics : Red = manufacturable technology for 10,000- transistor ICs

7 Bipolar Transistor Scaling Laws Design changes required to double transistor bandwidth key device parameter collector depletion layer thickness base thickness emitter junction width collector junction width emitter resistance per unit emitter area current density base contact resistivity (if contacts lie above collector junction) base contact resistivity (if contacts do not lie above collector junction) required change decrease 2:1 decrease 1.414:1 decrease 4:1 decrease 4:1 decrease 4:1 increase 4:1 decrease 4:1 unchanged

8 InP HBT Scaling Roadmaps Key scaling challenges emitter & base contact resistivity current density device heating collector-base junction width scaling & Yield! key figures of merit for logic speed

9 2005: InP 500 nm Scaling Generation Target Performance: 400 GHz f τ 500 GHz f max 150 GHz digital clock rate (static dividers) 250 GHz power amplifiers emitter: 500 nm width, 15 Ω μm 2 contact resistivity emitter contact base contact: 300 nm width, 20 Ω μm 2 contact resistivity InGaAs base BC grade collector base contact emitter N- drift collector collector: 150 nm thick, 5 ma/μm 2 current density 10 mw/μm 2 power 2V N+ sub collector S.I. InP substrate

10 2006: 250 nm Scaling Generation, 1.414:1 faster Target Performance: 500 GHz f τ 700 GHz f max 230 GHz digital clock rate (static dividers) 400 GHz power amplifiers emitter: 250 nm width, 7.5 Ω μm 2 contact resistivity emitter contact base contact: 150 nm width, 10 Ω μm 2 contact resistivity InGaAs base BC grade collector base contact emitter N- drift collector collector: 100 nm thick, 10 ma/μm 2 current density 20 mw/μm 2 power 2V N+ sub collector S.I. InP substrate

11 125 nm Scaling Generation almost-thz HBT Target Performance: 700 GHz f τ ~1000 GHz f max 330 GHz digital clock rate (static dividers) 600 GHz power amplifiers emitter: 125 nm width, 5 Ω μm 2 contact resistivity emitter contact base contact: 75 nm width, 5 Ω μm 2 contact resistivity InGaAs base BC grade collector base contact emitter N- drift collector collector: 75 nm thick, 20 ma/μm 2 current density 40 mw/μm 2 power 2V N+ sub collector ~3-4 V breakdown (BVCEO) S.I. InP substrate

12 65 nm Scaling Generation beyond 1-THz HBT Target Performance: 1.0 THz f τ 1.7 GHz f max 450 GHz digital clock rate (static dividers) 1 THz power amplifiers emitter: 62.5 nm width, 2.5 Ω μm 2 contact resistivity emitter contact base contact: 70 nm width, 5 Ω μm 2 contact resistivity InGaAs base BC grade collector base contact emitter N- drift collector N+ sub collector collector: 53 nm thick, 35 ma/μm 2 current density 70 mw/μm 2 power 2V 2-3 V breakdown (BVCEO) S.I. InP substrate

13 THz Transistors: addressing the key scaling challenges

14 Our HBT Base Contacts Today Use Pd or Pt to Penetrate Oxides TEM : Lysczek, Robinson, & Mohney, Penn State Sample: Urteaga, RSC Pt Reacted region InGaAs Pt Contact after 4hr 260C Anneal Au Pt Wafer first cleaned in reducing Pd & Pt react with III-V semiconductor Penetrate surface oxide Today provide 5 Ω-μm 2 resistivity (base) investigate better cleaning, alternative reaction metals Reacted region InGaAs Pt/Au Contact after 4hr 260C Anneal Chor, E.F.; Zhang, D.; Gong, H.; Chong, W.K.; Ong, S.Y. Electrical characterization, metallurgical investigation, and thermal stability studies of (Pd, Ti, Au)-based ohmic contacts. Journal of Applied Physics, vol.87, (no.5), AIP, 1 March p

15 Reducing Emitter Resistance: ErAs Emitter Contacts Material ErAs ErSb GaAs InP GaSb Lattice constant Å 6.108Å Å Å Å mismatch to ErAs -1.6% 2.1% 5.8% mismatch to ErSb -8.0% -4.0% -0.2% Epitaxial semimetal similar crystal structure to III-V semiconductors can be grown by MBE ErAs: Rocksalt structure Zimmerman, Gossard & Brown, UCSB III-V: Zinc blend structure III Er As Q. G. Sheng, J. Appl. Phys. (1993) A Guivarc h, J. Appl. Phys. (1994) In-situ contacts no oxides, no contaminants Lattice matched few defect states no surface Fermi pinning Thermodynamically stable little intermixing Well-controlled (atomic precision) interface *A. Guivarc h, Electron. Lett.(1989) **C.J.Palmstrøm Appl. Phys. Lett. (1990)

16 Temperature Rise Within Transistor & Substrate For each doubling in digital clock rate HBT scaling logarithic temperature increase ΔT InP,1 emitter width W e decreases 4 :1 HBT spacing D decreases 2 :1 P πk L InP E L ln W e e +K Thinning the substrate aggressively allows acceptable substrate temperature rise even at 300 GHz digital clock rate temperature rise in substrate, Kelvin Tsub = 15 μm ( 160 GHz/ f clock ) master-slave D-Flip-Flop clock frequency, GHz

17 Temperature Rise Within Package Assumptions : Transistor spacing : 20 μm (150 GHz/ f V = 2 V bias ce 1000 transistors/ic IC power = 1.5 ( transistor dissipation) clock ) For each doubling in digital clock rate emitter width W HBT spacing D decreases 2 :1 chip dimensionsw e decreases 4 :1 chip decrease 2 :1 Total Package Temperature Rise 2 + π Pchip ΔTpackage 2π K W Cu chip At 3 ma per transistor (100 Ω loading) acceptable package temperature rise with 1000 transistors / IC even at 300 GHz digital clock rate. package temperature rise, Kelvin ma per transistor (25 Ω logic load resistor) 3 ma per transistor (100 Ω logic load resistor) f GHz clock,

18 UCSB DHBTs: nm Scaling Generation Zach Griffith 1.7 μm base-collector mesa 1.3 μm base-collector mesa 600 nm emitter width

19 InP DHBT: 600 nm lithography, 120 nm thick collector, 30 nm thick base Zach Griffith Gains (db) U 25 h A = 0.6 x 4.3 um 2 jbe 10 I = 20.6 ma, V = 1.53 V c ce 5 J = 8.0 ma/um 2, V = 0.6 V e cb f = 450 GHz, f = 490 GHz t max Frequency (Hz) I b, I c (A) Gummel characteristics V CB = 0.0 V (dashed) V = 0.3 V (solid) CB I c n = 1.12 c I b n = 1.41 b V (V) be C cb /A e (ff/μm 2 ) A jbe = 0.6 x 4.3 μm 2 1.5ps/V 1.0 ps/v A jbc = 1.3 x 6.5 μm 2 V = -0.3 V cb -0.2 V 0.0 V 0.8 ps/v 0.6 ps/v 0.4 ps/v 0.2 V V = 0.6 V cb C cb /I c =0.2 ps/v J (ma/μm 2 ) e 5 Ccb (ff) β 40, V BR,CEO = 3.9 V. Emitter contact R cont < 10 Ω μm 2 Base : R sheet = 610 Ω/sq, R cont = 4.6 Ω μm 2 Collector : R sheet = 12.1 Ω/sq, R cont = 8.4 Ω μm 2

20 InP DHBT: 600 nm lithography, 75 nm collector, 20 nm base DC characteristics 20.0 V cb = 0 V 0.01 V = 0.0 V (dashed) CB V = 0.3 V (solid) CB Peak f τ J e (ma/μm 2 ) I b, I c (A) I c n = 1.15 c I b n = 1.47 b V ce (V) V be (V) Peak f max A je = μm 2, I b,step = 175 μa Average β 50, BV CEO = 3.2 V, BV CBO = 3.4 V (I c = 50 μa) Emitter contact (from RF extraction), R cont 8.6 Ω μm 2 Base (from TLM) : R sheet = 805 Ω/sq, R cont = 16 Ω μm 2 Collector (from TLM) : R sheet = 12.0 Ω/sq, R cont = 4.7 Ω μm 2 RF characteristics

21 UCSB / RSC / GCS 150 GHz Static Frequency Dividers IC design: Z. Griffith, UCSB HBT design: RSC / UCSB / GCS IC Process / Fabrication: GCS Test: UCSB / RSC / Mayo size current density C cb /I c units μm 2 ma/μm 2 psec / V data current steering 0.5 x data emitter followers 0.5 x clock current steering 0.5 x V cb V f τ GHz f max GHz clock emitter followers 0.5 x Output Power (dbm) frequency (GHz) Output Power (dbm) frequency (GHz) Minimum input power (dbm) P DC,total = mw divider core without output buffer mw probe station 25 C frequency (GHz)

22 175 GHz Amplifiers with 300 GHz f max Mesa DHBTs V. Paidi, Z. Griffith, M. Dahlström 7 db gain 175 GHz 7.5 mw output power 2 fingers x 0.8 um x 12 um, ~250 GHz f τ, 300 GHz f max, V br ~ 7V, ~ 3 ma/um 2 current density S 21, S 11, S 22 db S 11 S 22 S 21 7-dB small-signal gain at 176 GHz 8.1 dbm output power at 6.3 db gain Frequency, GHz

23 250 nm scaling generation DHBTs 100 % I-line lithography Emitter contact resistance reduced 40%: from 8.5 to 5 Ω μm 2 Base contact resistance is < 5 Ω μm 2 --hard to measure Recall, 1/8 μm scaling generation needs 5 Ω μm 2 emitter ρ c

24 0.30 µm emitter junction, W c /W e ~ 1.6

25 First mm-wave results with 250 nm InP DHBTs 150 nm material 250 nm emitter width f τ = 420 GHz f max = 650 GHz ~6 V breakdown 30 mw/um 2 power handling results submitted postdeadline to 2006 DRC, E. Lind et al

26 330 GHz Cascode Power Amplifiers In Design Thin-film microstrip lines Output P sat = 50 mw (17 dbm) 10-dB associated power gain use the 650 GHz f max transistors Gain (db), Output Power (dbm) 20 Output Power 15 Gain 10 PAE Input Power, dbm PAE (%) 15 S 21, S 11, S 22 ( db ) S 22 S Frequency, GHz S 11

27 Frequency Limits of Bipolar Integrated Ciruits Done: ~475 GHz f t & f max 150 GHz static dividers 160 Gb/s MUX & DMUX (Chalmers/Vitesse) 250 nm results coming very soon. expect ~200 GHz digital clock rate, 340 GHz amplifiers THz transistors will come The approach is scaling. The limits are contact and thermal resistance.

28 Performance Parameters for Fast Logic & Mixed-Signal Gate Delay Determined by : ΔV Depletion capacitance charging through the logic swing ΔV LOGIC ( Ccb + Cbe,depletion ) IC Depletion capacitance charging through the base resistance R bb ( C + C ) Supplying base + collector I C Rbb( τ b + τ c ) ΔVLOGIC The logic swing must be at least LOGIC cbi stored charge kt > 4 q be,depletion through the base resistance + R ex I c ( τ in in clock clock clock clock ( ΔV I )( C + C ) R b High ex + τ ) typicall y 10-25% of total delay; c LOGIC ( I / C ) C Delay not well correlated with C cb cb be,depl is a key HBT design must be very low for low ΔV is 55% - 80% of total. logic f τ objective. at high J out out Design HBTs for fast logic, not for high f t & f max

29 Performance Parameters for mm-wave Power Gain...under large-signal conditions Breakdown AND power density U 10 8 MSG/MAG, db Common emitter Common base J e (ma/μm 2 ) mw/um V BVCEO 5 Common Collector 2 10 mw/um Frequency, GHz V ce (V)...gain is less than MAG/MSG... P max = 8 ( 1 )( V max V min ) I max