Process Technologies and Integrated Circuits

Transcription

1 InP HBTs: Process Technologies and Integrated Circuits Mark Rodwell University of California, Santa Barbara , fax

2 Acknowledgments Collaborators Prof. A. Gossard, Dr. A. Jackson, Mr. J. English Materials Dept., University of California, Santa Barbara M. Urteaga, R. Pierson, P. Rowell, B. Brar Rockwell Scientific Company Lorene Samoska, Andy Fung Jet Propulsion Laboratories S. Lee, N. Nguyen, and C. Nguyen Global Communication Semiconductors Prof. Suzanne Mohney and Group, Penn State Prof. Ian Harrison, Univ. Nottingham Present HBT Team Members Z. Griffith, C. Kadow, N. Parthasarathy, U. Singisetti, C. Sheldon Past HBT Team Members (random order) V. Paidi, D. Scott, Y. Dong, M. Dahlström, Y. Wei, M. Urteaga, L. Samoska, S. Lee, Y.-M. Kim, Y. Betser, D. Mensa, U. Bhattacharya, PK Sundararajan, S. Jaganathan, J. Guthrie, H-J. Kim, R. Pullela, B. Agarwal, Q. Lee. Sponsors US DARPA: John Zolper, Steve Pappert US ONR: Dan Purdy, Ingham Mack, Max Yoder US ARO, JPL presidents fund, Agilent Technologies, Sun Microsystems, Walsin Lihwa Thanks To Prof. Bill Frensley, UT Dallas, for the use of BandProf

3 Applications

4 High Frequency Electronics: Applications Optical Fiber Transmission 40 Gb/s InP HBT fiber chip set (Gtran Inc.) 40 Gb/s: InP and SiGe ICs commercially available 80 & 160 Gb/s is feasible Gb/s InP ICs now clearly feasible ~100 GHz modulators demonstrated (KTH Stockholm) GHz photodiodes demonstrated in 1980's challenge: limit to range due to fiber dispersion challenge: competition with WDM using 10 Gb CMOS ICs 250 GHz digital radio: 100 Gb/s over 1 km in heavy rain Radio-wave Transmission / Radar / Imaging GHz, GHz, GHz 100 Gb/s transmission over 1 km in heavy rain 300 GHz imaging i for foul-weather aviation science spectroscopy, radio astronomy mm-wave sensor networks 300 GHz imaging Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought Gb/s Wireless Home Networks

5 Fast IC Technologies InP HBT: 500 nm emitter SiGe HBT: 130 nm emitter CMOS: 90 nm node: 455 GHz f τ / 485 GHz f max ~4 V breakdown 150 GHz static dividers 178 GHz amplifiers 300 GHz f τ / 350 GHz f max 96 GHz static dividers 77 GHz amplifiers 150 GHz push-push VCO- 75 GHz fundamental ~200 GHz f τ / 250 GHz f max ~1-1.5 V breakdown 60 GHz 2:1 mux 91 GHz amplifiers InP HBTs as ultra high speed technology: ~500 GHz bandwidth even at 500 nm scaling with minimal parasitic reduction Potential for much wider bandwidths at ~100 nm scaling InP HBTs for radio astronomy InP HBTs for radio astronomy feasibility of 100 mw power amplifiers at 200 GHz & perhaps 300 GHz aid in developing THz diode frequency multiplier chains

6 InP DHBTs for 33 / 45 / 60 / 77 /... / 94 GHz power? InP HBTs have the necessary bandwidth W-band amps need 200 GHz f t & fmax Today's InP HBTs: GHz f t & fmax InP HBTs can handle the necessary voltage 10 V breakdown adequate power 370 GHz HBTs have 5.6 V breakdown 200 GHz (W-band) HBTs will have 10 V Gains (db) f max 30 U H f t I = 13.2 ma c J (ma/um 2 ) e 10 A = 0.6 x 4.25 um 2 jbe 5 J = 5.17 ma/um 2, V = 0.6 V e cb f = 391 GHz, f = 505 GHz t max Frequency (Hz) GHz V cb = 0.6 V /μm 2 ) J e (ma/ A je = 0.4 x 7 μm 2 I b step = 500 μa HBT with pedestal HBT without pedestal 20 mw/μm 2 device failure V (V) ce InP HBTs can handle the necessary power density 10 mw/um 2 DC dissipation is reliable 5 mw/um 2 RF output power 2.5 mw/um in 0.5 um technology 2 THz-Volt breakdown-bandwidth product E max V sat =2*10 13 Volt/second J e (ma/μm 2 ) loadline 10 mw/μmμ 2 18 mw/μm 2 Power amplifiers to ~80 GHz in 1 um processes 1 um GaAs HBT processes are cheap, why not so InP? V ce (V) Power amplifiers to ~350 GHz in 250 nm processes mm-wave & sub-mm-wave systems for radio astronomy

7 HBT technology

8 Indium Phosphide Heterojunction Bipolar Transistors Z. Griffith

9 epitaxial i layer designs

10 PK Sundararajan DHBT epitaxy: Graded InAlAs Emitter, InGaAs base, InAlGaAs Grades InAlAs emitter InAlAs/InGaAs CSL grade bandgap-graded graded InGaAs base InAlAs/InGaAs CSL grade InP collector high breakdown important for microwave power important for logic low thermal resistance necessary for high power density essential for microwave power essential for logic Layer Material Doping Thickness (Å) Emitter cap In 0.53 Ga 0.47 As cm -3 : Si 300 N + emitter InP cm -3 : Si 700 N - emitter InP cm -3 : Si 500 Emitter-base grade In 0.53 Ga 0.26 Al 0.21 As to In Ga As P: cm -3 : Si N: cm -3 : C Base In 0.53 Ga 0.47 As N: cm -3 : C 400 Basecollector 0.53 Ga 0.47 As In N: cm -3 : Si 240 to In grade 0.53 Ga 0.26 Al 0.21 As Pulse doping InP cm -3 : Si 30 Collector InP N: cm -3 : Si 1,630 Subcollector InP N: cm -3 : Si ~1000 Å Performance ft and fmax good or better than SHBTs emitter emitter cap graded base collector subcollector

11 DHBT epitaxy: Abrupt InP Emitter, InGaAs base, InAlGaAs C/B Grade InGaAs 3E19 Si 400 Å InP 3E19 Si 800 Å InP 8E17 Si 100 Å InP 3E17 Si 300 Å Emitter V be = 0.75 V, V ce = 1.3 V InGaAs 8E19 5E19 C 300 Å Setback 3E16 Si 200 Å Grade 3E16 Si 240 Å Base Collector InP 3E18 Si 30 Å InP 3E16 Si 1030 Å InP 1.5E19 Si 500 Å InGaAs 2E19 Si 125 Å InP 3E19 Si 3000 Å SI-InP substrate Key Features: Abrupt InP emitter benefit unclear Collector setback eases grade design Thin InGaAs in subcollector remove heat Thick InP subcollector decrease R c,sheet

12 Other InP DHBT Layer Structures InGaAs/InGaAsP/InP grade InP/GaAsSb/InP DHBT IEDM suitable for MOCVD growth - does not need B/C grading - excellent results - E/B band alignment through h GaAsSb alloy ratio (strain) or InAlAs emitter - somewhat poorer transport parameters to date for GaAsSb base

13 Single-HBTs: InGaAs base and InGaAs collector Dino Mensa Layer Material Doping Thickness (Å) low breakdown: scaling beyond ~75 GHz digital clock rate very difficult high collector-base leakage particularly at elevated temperatures. Serious difficulties in real applications very high thermal resistance InGaAs collector and subcollector can reduce with InP subcollector limits power density limits both digital and mm-wave application Emitter cap In 0.53 Ga 0.47 As cm -3 : Si 300 N + emitter InP cm -3 :Si 700 N - emitter InP cm -3 : Si 500 Emitter-base grade In 0.53 Ga 0.26 Al 0.21 As to In Ga As P: cm -3 : Si N: cm -3 : C Base In Ga 047 As cm N: :C 400 Collector In 0.53 Ga 0.47 As N: cm -3 : Si 2000 Subcollector InP N: cm -3 : Si ~1000 Å

14 process flow

15 Basic Mesa IC Process Z. Griffith PK Sundararajan

16 Basic Mesa IC Process Z. Griffith PK Sundararajan

17 Basic Mesa IC Process Z. Griffith PK Sundararajan

18 Basic Mesa IC Process Z. Griffith PK Sundararajan

19 Basic Mesa IC Process Z. Griffith PK Sundararajan

20 Basic Mesa IC Process Z. Griffith PK Sundararajan

21 Basic Mesa IC Process Z. Griffith PK Sundararajan

22 Basic Mesa IC Process Z. Griffith PK Sundararajan

23 Basic Mesa IC Process Z. Griffith PK Sundararajan

24 Basic Mesa IC Process Both junctions defined by selective wet-etch chemistry Narrow base mesa allows for low A C to A E ratio Low base contact resistance Pd based ohmics with ρ -7 Ω cm 2 C < 10 Collector contact metal and metal 1 used as interconnect metal NiCr thin film resistors = 40 Ω / MIM capacitor, with SiN dielectric -- used only for bypass capacitors Low loss, low ε r = 2.7 microstrip wiring environment Microstrip wiring environment. has predictable characteristic impedance controlled-impedance interconnects within dense mixed signal IC s ground plane eliminates signal coupling that occurs through on-wafer gnd-return inductance

25 Completed mesa HBTs &ICs

26 Mesa Process -- Without Passives & Interconnects Z. Griffith PK Sundararajan Top view End view Side view 9200 Ǻ 1.20 μm 4600 Ǻ 4200 Ǻ

27 Mesa Process -- With Passives & Interconnects Z. Griffith PK Sundararajan Process front end transistors, resistors, and M1 interconnects Process back end capacitors, M2, and ground plane formation (M3)

28 Mesa Process -- Some Pictures Zach Griffith

29 Transistor Figures of Merit

30 Short-circuit current-gain cutoff frequency Rgen short-circuit current gain: Iout Iin drive input, short output, measure H 21 =I out /I in H 1 1/ β + jf / f τ Vgen ( ) ( ) 21 ( ( f ) h 21 Ga ains (db) A = 0.6 x 4.3 um 2 A jbe I c = 20.6 ma, V ce = 1.53 V J = 8.0 ma/um 2, V = 0.6 V e cb f = 450 GHz, f = 490 GHz t max t max Frequency (Hz)

31 Current-gain cutoff frequency in HBTs 1 2πf τ kt kt = τ base τ collector C je Cbc + Rex + Rcoll qi E qi E τ base T 2D 2 b n τ collector T 2v c eff RC terms are q ite important for high band idth de ices RC terms are quite important for high bandwidth devices...layers can always be thinned until RC terms dominate!

32 Miguel Urteaga Definition of power gains and f max MSG/MAG is of direct relevance in tuned RF amplifier design Maximum Available Gain Simultaneously match input and output of device MAG = ( ) K K 1 S 21 2 S 12 K = Rollet stability factor ge ne ra tor load R gen V ge n los s le s s matching ne twork los s le s s matching network R L Transistor must be unconditionally stable or MAG does not exist Maximum Stable Gain Stabilize transistor and simultaneously match input and output t of device MSG = S S = Y Y ωc R 1 + kt qi Approximate value for hybrid-π model To first order MSG does not depend on f τ or R bb cb ex c generator R gen V gen los s le s s matching network re s is tive los s (s ta bilization) los s le s s matching network loa d For Hybrid- π model, MSG rolls off at 10 db/decade, while MAG has no fixed slope. So, NEITHER can be used to accurately extrapolate f max R L

33 Unilateral Power Gain Miguel Urteaga Mason s Unilateral Power Gain shunt feedback Use lossless l reactive feedback to cancel device feedback and stabilize the device, then match input/output. generator R gen V gen lo s s le s s matching network lo s s le s s matching network lo a d R L U = 4 Y 2 ( G G G G ) Y series feedback U is not changed by pad reactances U: all 3 30 For Hybrid- π model, U rolls off at 20 db/decade ALL Power Gains must be unity at f max Monolithic amplifiers are not easily made unilateral, so U of only historical relevance to IC design. Ui is usually valuable for f max extrapolation ti Gains, db MAG/MSG common collector MAG/MSG common emitter Frequency, GHz MAG/MSG common base

34 Excess Collector Capacitance, Fmax, and Device Utility B R bb R be C cbx C cbi C be E R ex R c C g m V be Gains, db U: all 3 MAG/MSG common collector MSG CE = S S = MAG/MSG common emitter Frequency, GHz Y Y f MAG/MSG common base ωc cb max 1 Rex + kt qi c fτ 8πR bb C cbi The partitioning between C C has no effect upon f C cbx cbx C cbx has a max cbi and C or U. cbx will be discussed later. large impact upon common - emitter MSG, hence has large impact on usable gain in mm - wave circuits. has a large impact upon digital logic speed. high h f max does not mean low C cb or fast logic

35 What do we need: f t, f max, or? Tuned ICs (MIMICs, RF): fmax sets gain, & max frequency, not ft. low ft/fmax ratio makes tuning design hard (high Q) high C cbx reduces MSG cbx Lumped analog circuits need high & comparable ft and fmax. C cb /I c has major impact upon bandwidth Distributed Amplifiers in principle, fmax-limited, ft not relevant. (low ft makes design hard) digital ICs will be discussed in detail later

36 transistor electrical parameters

37 HBT DC Characteristics

38 HBT transit times

39 Emitter Resistance Dino Mensa Emitter resistance : one limiting factor in scaling for speed high speed devices : high J but high J excessive evidence of edge depletion or damage low ( C b I ) ( I R ) voltage drop E ex cb c R ex 1 R ex =? L E ρ ( W ΔW ) E c ( L )( W ΔW ) = ρ E c E Low resistance obtained with In x Ga 1-x As emitter caps Process control for removal of surface oxides is important. Ti/Pt/Au contacts still best at present with high In fraction.

40 Current Gain: surface conduction, not recombination Surface Conduction: InGaAs has low surface recombination velocity. InGaAs has surface pinning near conduction band. weak surface inversion layer on base, surface conduction to base contact Problem aggravated by InP emitter, as this also pins near conduction band 1 = β = I I b c A E = P I surface I po n + I I bulk c c E ( k 1 qnpo) + ( qn D / W b ) 1 β bulk evidence of surface conduction Dino Mensa emitter base Be: InGaAs 4E19/cm 3 doping

41 Passivation with Silicon Nitride: Ledges Literature suggests that coating InP with Silicon Nitride produces surface states ~200 mev below conduction band edge surface pinning leakage Use InGaAs/InAlAs grades (sketches below) to form ledges: surface pinning for SiN-coated InAlAs is ~400 mev below band edge. Not understood; some processes with SiN on InGaAs or InP still have low leakage. grade SiN N+ N- P+ metal

42 base parameters

43 Base Transit Time Dino Mensa Assumes: D N v exit = 40 cm = / V sec cm/s τ b L = W L b where L g g g / D is n ( kt / Δ E ) = W / b ( )( ) 2 W / L L / D L / v 1 e g the grading length : g n g sat b g Drift - diffusion model correct if τ * >> D m / kt b τ m n 35 fs

44 Base Transit Time: Grading Approaches Dino Mensa Miguel Urteaga Mattias Dahlström Compositional grading: strained graded InGaAs base Base-emitter emitter junction with InAlAs/InGaAs CSL UCSB data showed limited improvement with > 50 mev grading Findings similar to that of Ritter Group /Technion Stain effects on bandgap must be included in grade design 52 mev potential drop : In0.455Ga0.545As In0.53Ga0.47As (strained) Doping grading: carbon graded from ~8 to 5E19 Abrupt (InP-InGaAs) base-emitter junction Analyses by Ishibashi, others, suggests that abrupt launcher has minimal effect on transit time in > 30 nm bases Doping grading is only effective for degenerate base doping; otherwise large doping change induces only small field but requires large sacrifice in base sheet resistance UCSB has used both approaches; neither appears to be conclusively superior.

45 Limits on Base Doping Loss of current gain due to Auger Recombination At high dopings, τ Auger Since 1 N τ base 2 A 1 T bulk recombination dominated by Auger 2 B β 1 ( N A T B ) 2 2 1/ ρ sheet For doping > / 3 cm, we observe more rapid decrease of β than 1/ 2 ρ sheet. Causes : effect of high carbon concentration on strain? very low acceptor ionization?

46 base-collector RC parasitics

47 Base-Collector Distributed Model: exact This "mesh model" can be entered into a microwave circuit simulator (e.g. Agilent ADS) to predict f max, etc.

48 Components of Rbb and Ccb After Pulfrey / Vaidyanathan Miguel Urteaga R = ρ W / 2L horiz s bc E C / cb,e = εl ew e T c R = R + R R = R! x horiz vert cont cont

49 Pulfrey / Vaidyanathan fmax model Note that the external capacitance C is charged through a cb, ext less than Rvert cb, ext ( Rcont Rvert ) < Ccb, extrvert low resistance, C ε = T c 1 ρ contact...the associated charging time is relatively small relatively. C has moderate effect upon cb, ext f max but big impact upon digital and analog speed,

50 collector spacecharge effects

51 Scaling Laws, Collector Current Density, C cb charging time InGaAs base GaAsSb base Collector Depletion Layer Collapse V 2, min + φ > ( qn d )( Tc / 2ε ) cb + 0 ma/μm 2 0 ma/μm 2 Collector Field Collapse (Kirk Effect) V cb + φ > + ( J / v sat qn d )( T 2 c / 2ε ) max = 2ε v ( V + V + 2φ ) / Tc 2 10 ma/μm 2 eff cb cb,min 10 ma/μm 2 J Note that V be φ, hence ( V + φ) cb V ce C cb ΔV LOGIC / I C = ( εa T )( ΔV I ) collector c LOGIC C = ΔV A LOGIC collector C ( V + V ) CE CE A 2v,min emitter eff T Collector capacitance charging time scales linearly with collector thickness if J = J max

52 Kirk effect in DHBTs 500 J Decrease in f τ and f max at high J Kirk - effect threshold increases with increased V ce max = 2εv 2εv sat sat ( V ( V cb ce + V + V cb,min ce,min + 2φ ) / T ) / T 2 c 2 c f (GHz z) τ V cb 0.2 V 0.0 V cb cb -0.2 V cb f, -0.3 V τ cb , J (ma/um 2 ) e Increase in V, dv di ce c R ce, sat = space charge with increased J = 2εv sat T A 2 c where the effective collector current flux area is ( W + T ) A L 2 effective E E C effective A = 0.6 x 4.3 μm 2 jbe 16 J ma/μm 2 e (m ) V cb = 0 V Peak f t, f max I b step = 180 ua V (V) ce I (m ma) c

53 Collector Transit Time T. Ishibashi Tc Tc/ V=0 - From elementary electrostatics (refer to sketch) T C (1 x / Tc ) τ c = dx v ( x ) c 0 T 2v τ is more sensitive to velocity near base. c eff Fortuitous, as initial velocity is high, then decreases due to Γ - L scattering. Tc/ V=0 From best fit to RF data, or from Kirk current density vs. collector voltage : InGaAs : v eff cm/s for ~ 200 nm layers. InP : cm/s for ~ nm layers

54 Current-induced Collector Velocity Overshoot T. Ishibashi J=0 tau, ps ec Å InGaAs base 2000 Å InP collector 280 GHz peak f τ inverse current density, 1/J, μm 2 /ma Increased current reduces Γ - L scattering, increases v( x) in early part of collector reduced collector transit time Q base J= 8 ma/um 2 Qbase τ not = I c T C 0 (1 x / T v( x) correct definition of c Q = τ c = II c I c c ) dx is not exactly proportional collector transit time is base to I c Nakajima, H. "A generalized expression for collector transit time of HBTs taking account of electron velocity modulation," Japanese Journal of Applied Physics, vo. 36, Feb. 1997, pp CAUTION : observed nonlinear τ ec variation is also in part due to modulation in emitter ideality factor with bias current (1/ g m often does not vary as Rex + nkt / qi E ), and due to variation of C je with bias.

55 Transit time Modulation Causes C cb Modulation Q C base holes T ( 1 x / T ) dx + V A/ T = f ( I, V ) c = constant+ Q + ( ) base qn x A ε 0 c bc c c cb electrons Q Q C τ E base holes cb f = V I I V I ΔQ b base base holes cb τ f cb c c cb Camnitz and Moll, Betser & Ritter, D. Root base , + holes - drift collector ev Collector Velocity Modulation: τ f V cb > 0 C I < nm Increasein τ c withv - strong effect in InGaAs SHBTs - weak effect in InP DHBTs cb cb c L Γ reduced C cb f (GH Hz) τ V cb 0.2 V 0.0 V cb cb -0.2 V cb f, -0.3 V τ cb J (ma/um 2 ) e C /A (ff/μm 2 ) cb e V V V 4 3 V = 0.6 V cb J (ma/μm 2 ) e ev Kirk Effect : τ f V cb < 0 C I > nm Increase in C cb is due to both - base pushout into collector cb - and modulationof c τ b by V cb

56 M. Urteaga Transit time Modulation Negative Resistance Infinite Gain collector voltage E (V 0 +ΔV) base electron density J e /(V 0 +ΔV) time positiveg 12 = negative conductance negative G22 = negative conductance V (V 0 +ΔV) subcollector subcollector J e /V 0 ΔV is negative collector current ΔT=2τ c ΔJ=J e(δv/ V 0) time negative capacitance C cb, canc I c τ f ( V ) = / negativeresistance R = 2 ( τ c / 3C cb ),canc cb

57 equivalent circuit model

58 Transistor Hybrid-Pi equivalent circuit model C cbx B R bb C cbi R c C g qi / m E g C nkt R g V be be m be be 0 = = g e j ω ( γτ b + τ c ) m m0 be = C je + g ( τ + τ m b c ) C be E R ex

59 Comments regarding the Hybrid-Pi model The common - base (T) model directly models frequency - dependent transport The hybrid - pi model results from a fit to the T to first order in ω. The capacitance cpc ce C on input impedance be, diff models the effect ec of ( τ b + τ ) c The g m generator nevertheless also requires an associated ~ (0.2 τ + τ c) delay (important b c in fast IC design) g) R bb C cbi and C cbx represent fits to the distributed RC base - collector network

60 thermal considerations

61 Fast DHBTs: high current density high temperature Ian Harrison U. Nottingham (K) Tem mperature Rise Caused by Low K of InGaAs Max T rise in Collector center Edge 5 SC ES C B E E Metal Distance from substrate (μm) Thermal conductivity of InGaAs ~ 5 W/mK Thermal conductivity of InP ~ 68 W/mK Average Tj (Base-Emitter) =26.20 C20 C Measured Tj=26 C good agreement Conclusions Minimize InGaAs thickness in subcollector Use narrow emitter stripes

62 Thermal conductivity of common materials Mattias Dahlström 100 at 300 K 80 InP Si (168) κ (W/K Km) InAs GaAs 20 0 InGaAs InAlAsInGaP SiN SiO polyimid Material Ternaries lattice matched to InP

63 Mattias Dahlström Where is the heat generated, how is it removed? E (ev) InGaAs Emitter InP InGaAs Base InGaAlAs InP E c E v Collector InGaAs Position (A) InGaAs base InP collector base contact InGaAs subcollector InP subcollector SI substrate emitter J E x V CE =6 x 1.5 V=9 mw/μm 2 InGaAs collector collector contact In the intrinsic collector base contact InGaAs base InP collector InGaAs subcollector InP subcollector emitter InGaAs collector collector contact SI substrate Main heat transport t is through h the subcollector to the substrate t Up to 30 % heat transport up through the emitter contact For small thermal resistance: InP collector, InP subcollector, only thin InGaAs in subcollector, InP emitter, narrow emitter junction for radial heat flow

64 Mattias Dahlström Experimental Measurement of Temperature Rise δv be = fixed I θ JA = c dv dt be = φ θ dv dv be CE dt dp JA I I C dp dv δv I CE CE C 1 φ δv ( ) CE ) φ (V/K) fixed c Thermoelectric feedback coefficient from Liu et al J e (ma/μm 2 ) I c (A) Meta run 11 (BCB) E05B05 I c V ce =1.5V V ce =1.3V Temperature rise calculated by measuring I C, V CE and ΔV BE No thermal instability as long as slope< each V BE gives a unique I C V (V) be ΔVBE W. Liu: Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors, IEEE Transactions on Electron Devices, Vol 42 No6, June 1995 W. Liu: H-F. Chau, E. Beam, "Thermal properties and Thermal Instabilities of InP-Based Heterojunction Bipolar Transistors, IEEE Transactions on Electron Devices, Vol 43 No3, March 1996

65 Example of Thermal Data Zach Griffith

66 Current Hogging and Emitter Finger Ballasting Yun Wei I b step = 300 μa I c, ma , ma I c V, Volts ce I step = 380 μa b V, Volts ce Assume initial temperature difference δt between 2 fingers dv be = φ at constant Ic dt dvbe δt δvbe = δt dt δp = V CE δi C δt = θ δi JA C = δp R ex + R ballast 1 + kt / qi E δv be Unstable unless K dv be CE JA thermal stability = < dt Rex + Rballast + kt / qi E V θ 1 W. Liu, H-F Chau, E. Beam III, "Thermal properties and thermal instabilities of InP-based heterojunction bipolar transistors", IEEE Transactions on Electron Devices, vol.43, (no.3), IEEE, March p

67 Thermal runaway within a finger emitter With long emitter finger, current-crowding can occur within finger Long finger: temperature can vary along length of emitter finger loss of strong thermal coupling Temperature gradients along finger results in nonuniform current distribution center of stripe gets hotter carries more current gets hotter Premature Kirk-effect-induced collapse in f t.

68 Yun Wei Measurement of Current hogging in multi-finger DHBT V_DC SRC2 I_Probe I_Probe1 I_Probe I_Probe2 I_DC SRC W. Liu, H-F Chau, E. Beam III, "Thermal properties and thermal instabilities of InP-based heterojunction bipolar transistors", IEEE Transactions on Electron Devices, vol.43, (no.3), IEEE, March p

69 mesa transistor results

70 Zach Griffith InP Mesa DHBTs; 600 nm Emitter Scaling Generation 1.7 μm base-collector mesa 1.3 μm base-collector mesa

71 DC, RF performance 150 nm collector, 47 nm transition Zach Griffith Gains (db) A jbe = 0.6 x 4.3 um U 400 GHz 300 H I c = 13.2 ma, V ce = 1.54 V J e = 5.17 ma/um 2, V cb = 0.6 V f t = 391 GHz, f max = 505 GHz 2 f max f t V cb = 0.6 V J (ma/um 2 ) e C cb /I c ~0.5 ps/v Frequency (Hz) A jbe = 0.6 x 4.3 μm 2 ma/μm 2 ) J e ( I b step = 85 ua V cb = 0 V Peak f τ, f max A jb Average β 36, V BR,CEO = 5.1 V (I = 50 μa) 10-6 c ) Emitter contact (from RF extraction), R cont = 10.1 Ω μm 2 I, I (A) b c jbe = 0.6 x 4.3 μm2μ V ce (V) n c = 1.17 I c I b n b = I (ma A) c Base (from TLM) : R sheet = 564 Ω/sq, R cont = 9.6 Ω μm V CB = 0.3 V (solid) V CB = 0.0 V (dashed) Collector (from TLM) : R sheet = 11.9 Ω/sq, R cont = 5.4 Ω μm V be (V)

72 DC, RF performance 120 nm collector, 42 nm transition Zach Griffith 30 nm base Gains (db) h 21 U f t = 450 GHz, f max = 490 GHz Frequency (Hz) 1.5ps/V V cb = -0.3 V Average β 40, V BR,CEO = 3.9 V. Emitter contact R cont < 10 Ω μm 2 Base: R sheet = 610 Ω/sq, R cont = 4.6 Ω μm 2 Collector: R 1 sheet = 12.1 Ω/sq, R cont = 8.4 Ω μm ps/v 0.8 ps/v 25 I b, I c (A) 0.01 V CB Gummel characteristics = 0.0 V (dashed) V = 0.3 V (solid) CB n c = 1.12 I c 10-8 I b n = 1.41 b V (V) be (ff/μm 2 ) C cb /A e V 0.0 V 0.6 ps/v 0.4 ps/v 0.2 V V = 0.6 V cb C cb /I c =0.2 ps/v Ccb (f ff) 0 A jbe = 0.6 x 4.3 μm 2 A = 1.3 x 6.5 μm 2 jbc J (ma/μm 2 ) e

73 DC, RF performance 100 nm collector, 42 nm transition Zach Griffith Gains (db) MSG/MAG U A jbe = 0.6 x 4.3 um nm collector, 30 nm base H 21 I c = 27.8 ma, V ce = 1.37 V A = 0.6 x 4.3 μm 2 jbe ma/μm 2 ) J = 10.3 ma/um 2,V = 0.4 V e cb f t = 491 GHz, f max = 415 GHz Frequency (Hz) Summary of device parameters Average β 40, V BR, CEO = 3.1 V (I c = 50 μa) Emitter contact (from RF extraction), R cont 7.8 Ω μm 2 J e ( A jb Base (from TLM) : R = 629 Ω/sq, R = 6.2 Ω μm sheet cont I, I (A) b c V cb = 0 V I = 180 ua b step Peak f t, f max V (V) ce jbe = 0.6 x 4.3 μm2μ n c = 1.12 I c n b = 1.44 I b V CB = 0.0 V (solid) V CB = 0.3 V (dashed) I (ma A) c Collector (from TLM) : R sheet = 12.9 Ω/sq, R cont = 4.0 Ω μm V be (V)

74 Summary of HBT performance: April 2005 f (G GHz) max GHz UCSB T.S SHBT (?) 300 GHz Pohang SHBT 250 nm 400 GHz NGST DHBT 150 nm UCSB 210 nm 500 GHz NTT DHBT 150 nm = UCSB 150 nm 150 nm f max f τ UCSB 120 nm HRL 120 nm IBM DBHT SiGe RSC DHBT nm SFU DHBT 65 nm 200 nm 150 nm 200 IBM 75 nm SiGe 100 nm 100 nm 0 Updated April 12, 2005 UCSB 100 nm UIUC SHBT popular ( f + f τ max (1 f τ f τ f max + 1 metrics : ) / 2 f max ) 1 better metrics ti : power amplifiers : PAE, associated itdgain, mw/ μm low noise amplifiers : F min, associated gain, associated DC power digital : f clock ( C ( R ( R cb ex, hence ΔV / I f t (GHz) ( τ + τ ) b c bb I I c c c ), / ΔV ), / ΔV ),

75 Comparison with InP HEMTs GHz ft fmax 500 HBTs have better breakdown than HEMTs use HBTs for power amplifiers GHz) fmax (G HEMTs have better noise than HBTs use HEMTs for LNAs 1.0 Lg = 30 nm Keisuke Shinohara CRL Japan (Now at Rockwell Scientific) ft (GHz) Gate ( Ti / Pt / Au ) Lg = 30 nm (A/mm) Dra ain current 0.8 Vgs = 0 ~ -0.8 V in 0.2 V step 534 ft value Drain-source voltage (V)

76 transistor scaling theory

77 HBT scaling: layer thicknesses 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, τ 's W E W EB L E emitter base base Δx collector reduce T b by 2:1 τ b improved 2:1 reduce T c by 2:1 τ c improved 2:1 τ τ b b W C T / 2D 2 b T / 2v c n sat W BC note that Ccb has been doubled..we had wanted it 2:1 smaller AssumeW C ~ W E

78 HBT scaling: lithographic dimensions 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, τ 's Base Resistance R bb must remain constant L e must remain ~ constant R = R + R + bb = R gap contact ρ sheet ρ spread c, vertical R contact 2L E Ccb/Area has been doubled..we had wanted it 2:1 smaller must make area=l e W e 4:1 smaller must make W e & W c 4:1 smaller L E base W E emitter W EB base Δx collector reduce collector width 4:1 reduce emitter width 4:1 keep emitter length constant W W BC C AssumeW ~ W C E

79 HBT scaling: emitter resistivity, current density 2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's, τ 's Emitter Resistance R ex must remain constant but emitter area=l e W e is 4:1 smaller resistance per unit area must be 4:1 smaller AssumeW ~ C W E Collector current must remain constant but emitter area=l e W e is 4:1 smaller and collector area=l c W c is 4:1 smaller current density must be 4:1 larger W E W EB L E emitter base base increase current density 4:1 reduce emitter resistivity 4:1 Δx collector W C W BC

80 Bipolar Transistor Scaling Laws W E W EB Scaling Laws: design changes required to double transistor bandwidth L E base emitter base Δx collector W C W BC key device parameter required change collector depletion layer thickness decrease 2:1 base thickness decrease 1.414:1 emitter junction width decrease 4:1 collector junction width decrease 4:1 emitter resistance per unit emitter area decrease 4:1 current density increase 4:1 base contact resistivity decrease ~4:1 (if contacts lie above collector junction) base contact resistivity (if contacts do not lie above collector junction) unchanged

81 digital / mixed signal IC design and relationship to transistor

82 We design HBTs for fast logic, not for high f τ & f max Gate Delay Determined by : Depletion capacitance charging through the logic swing ΔV LOGIC ( Ccb + Cbe,depletion ) I C Depletion capacitance charging through the base resistance R bb ( C cbi C ) + be,depletion Supplying base + collector stored charge through the base resistance R bb I ( ) C τ b + τ c Δ VLOGIC b in ( τ +τ ) in clock clock clock clock c typically 10-25% of Dl Delay not well ( ΔV I )( C + C ) High LOGIC C ( I / C ) C cb cb be,depl total correlated ltd delay; with f τ is 55% - 80% of is a key HBT design objective. total. The logic swing must be at least CcbΔVLOGIC ΔV LOGIC A collector T = IC 2V A CE,min kt emitter 2v ΔVLOGIC > 4 + RexIc Rex must be very low for low ΔVlogic at high J q J max, Kirk = 2εv electron (V ce, operating + V ce,full depletion C out out ) / T electron 2 c

83 InP HBT Roadmaps: 40 / 80 / 160 Gb/s digital clock rate Key scaling challenges emitter & base contact resistivity current density device heating collector-base junction width scaling & Yield! key figures of merit for logic speed

84 Why isn't base+collector transit time so important for logic? V out V out (t) out Diffusion capacitance : δqbase = ( τ b + τ c ) δi C di = ( τ b + τ c ) dv ( τ b + τ c ) I = kt / q C C be δ V δv...active only over kt / q voltage swing. be be t V in V in (t) t diffusion + depletion capacitance only depletion capacitance Under Large- Signal Operation : ΔQ base = ( τ + τ ) b c I C ( τ + ) = b τ c Idc ΔV ΔV LOGIC LOGIC Large- signal diffusion capacitance reduced by ratio of Δ kt V LOGIC / q, which is ~ 10 :1 Depletion capacitances present over full voltage swing, no large-signal reduction

85 Scaling Laws, Collector Current Density, C cb charging time InGaAs base GaAsSb base Collector Depletion Layer Collapse V 2, min + φ > ( qn d )( Tc / 2ε ) cb + 0 ma/μm 2 0 ma/μm 2 Collector Field Collapse (Kirk Effect) V cb + φ > + ( J / v sat qn 2 J 10 ma/μm 2 max = 2ε veff ( Vcb + Vcb,min + 2φ ) / Tc 10 ma/μm 2 d )( T 2 c / 2ε ) Note that V be φ, hence ( V + φ) cb V ce C cb ΔV LOGIC / I C = ( εa T )( ΔV I ) collector c LOGIC C = ΔV A LOGIC collector C ( V + V ) CE CE A 2v,min emitter eff T Collector capacitance charging time scales linearly with collector thickness if J = J max

86 Key HBT Scaling Limit Emitter Resistance R L ECL delay not well correlated with f τ or f max Largest delay is charging C cb ΔV Vlogic εaa Δ V collector logic C = ; where J e,max 1 /T cb I T J A C C e emitter J m e 10 ma/μm 2 needed for 200 GHz clock rate Voltage drop of emitter resistance becomes excessive R ex I c = ρ ex J e = (15 Ω μm 2 ) (10 ma/μm 2 ) = 150 mv ΔV logic considerable fraction of ΔV logic 300 mv Degrades logic noise margin 2 c. R ex Noise margin I o V out V in ρ ex 7 Ω μm 2 needed for 200 GHz clock rate 2kT/q+I o R ex ΔV logic =I o R L

87 Breakdown: Thermal failure is more significant than BVCEO J (ma/μm m 2 ) e um X 7 um emitter junction 0.5 um base contact width A jbe =0.6 x 7 μm 2 ~6.8 V low-current BVCEO I b step = 0.4 ma V ce (V) ce Breakdown -V High f τ and br, ceo f max or V br, cbo requires high J - is measured at low J low - current breakdown often not relevant V br, ceo = EmaxT decreases more slowly than f because E max collector increases with thin collectors e e 1 clock ax (ma/um2 ) J ma 12 biased without 2 ~ 7 K ( μm) / mw thermal resistance failure (DC-IV) 10 device failure No RF drift after 3-hr burn-in Dissipation limits power density 18 mw/um 2 2 design limit 10 mw/um P A 2 E = J EVce fclock 2 ECL V 1/ bias points max θ ja fclock V CE μm emitter metal length, ~0.6 μm junctionwidth V (V) ce data above Jan. 2004; failure >29 mw/um 2 Low thermal resistance is critical. DHBTs are superior to SHBTs.

88 digital IC results

89 Digital circuits: towards 200 GHz clock rate 142 GHz latch from UCSB, 150 GHz ICs from UCSB/GSC/RSC 200 GHz is the next goal underlying technology: GHz InP transistors Z Griffith

90 Static Frequency Divider: Standard Digital Benchmark ECL Master-Slave Latch with Inverting Feedback Forms 2:1 Frequency Divider. Maximum clock frequency is measure of technology speed. Standard circuit configuration for consistent benchmarking - no tricks. Small inductive peaking (L/R~1.3 ps). One clock period has 2 latch delay. Each latch is a 2-input gate with an equivalent fanout of 2 or 3 much more strenuous test than 2:1 mux or ring oscillator Z Griffith

91 Hierarchy of ECL Static Frequency Divider ECL NAND/NOR Gate ECL Latch: level-clocked memory element Level Shifters Logic Gate Core Level Shifters Zo C D C Q Q D Q Master-Slave Latch: transition-clocked memory element 2:1 Static Frequency Divider D C Q Q D C Q Q D C Q Q D C Q Q

92 CPW has parasitic modes, coupling from poor ground plane integrity k z 0V +V 0V +V +V +V -V 0V +V 0V CPW mode 0V Microstrip mode Substrate modes 0V Slot mode ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductance ground vias suppress microstrip mode, wafer thinning suppresses substrate modes Microstrip has high via inductance, has mode coupling unless substrate is thin. k z We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs M. Urteaga, Z. Griffith, S. Krishnan

93 UCSB / RSC / GCS 150 GHz Static Frequency Dividers IC design: Z. Griffith, UCSB HBT design: RSC / UCSB / GCS IC Process / Fabrication: GCS Test: UCSB / RSC / Mayo data data clock clock units current emitter current emitter steering followers steering followers size μm x x x x 5.5 current ma/μmμ density C cb /I c psec / V V cb V f τ GHz f max GHz Output Power (dbm m) frequency (GHz) Output Power (db Bm) frequency (GHz) input powe er (dbm) Minimum 20 P DC,total = mw divider core without output buffer mw probe station 25 C frequency (GHz)

94 Z. Griffith, M. Dahlström UCSB 142 GHz Master-Slave Latches (Static Frequency Dividers) Static 2:1 divider: Standard digital benchmark. Master-slave latch with inverting feedback. Performance comparison between digital technologies UCSB technology 2004: InP mesa HBT technology 12-mask process 600 nm emitter width 142 GHz maximum clock. Implications: 160 Gb/s fiber ICs Gb/s serial links Target is 260 GHz clock rate at 300 nm scaling generation Output Po ower (dbm) o C frequency (GHz)

95 Reducing Divide-by-2 Dissipation 50 Ohm 50 Ohm bus 50 Ohm ECL with impedance-matched 50 Ohm bus: 25 Ohm load switch 12 ma 12 ma x 7 x 4 V = 336 mw/latch 12 ma 50 Ohm 50 Ohm bus 50 Ohm CML with impedance-matched 50 Ohm bus: 25 Ohm load switch 12 ma 12 ma x 3 x 3 V = 108 mw/latch 12 ma 12 ma 12 ma 100 Ohm 50 Ohm bus 100 Ohm Low-Power CML 100 Ohm loaded switch 3 ma 3 ma x 3 x 3 V = 27 mw/latch 3 ma 3 ma 3 ma High low power = low C wiring, low C cb, pad Significant dissipation in the emitter-follower level-shifters

96 C cb /I c Charging Rate: ECL is much better than CML CML Zo C /A (ff/μ μm 2 ) cb e V = -0.3 V cb -0.2 V 0.0 V 0.2 V V cb = 0.6 V cb Ccb (ff) ECL C Δ V Δ V A T J (ma/μm 2 ) e cb I C LOGIC = Zo V CE LOGIC + V CE,min A collector emitter C /A (f ff/μm 2 ) cb e 2v C electron ΔV l i = 300mV logic V cb = -0.3 V cb -0.2 V 0.0 V 0.2 V V cb = 0.6 V C cb b (ff) J (ma/μm 2 ) e

97 Phase II divide by 2 Ultra low power CML divider Simulated divider speed With Collector Pedestal A jbe = 1.0 μm 2, f max = 100 GHz 470 μm P divider core 31 mw divider core, 443 μm

98 mm-wave amplifiers

99 Tuned Amplifier Design for Maximum Gain If Device is Unconditionally Stable Simultaneously match input and output of device MAG = S ( ) K K 1 S K = Rollet stability factor generator R gen V gen los s le s s matching network If transistor is unconditionally stable, circuit gain is transistor MAG los s le s s matching network loa d R L If Device is Potentially Unstable generator Stabilize transistor and simultaneously match input and output of device MSG = S 21 = S 12 Y Y R gen V gen los s le s s matching network re s is tive los s (s ta bilization) los s le s s matching network loa d R L If transistor is potentially unstable, circuit gain is transistor MSG Design for maximum gain is rare; usually one designs for maximum saturated power or for minimum noise. Gain is then less, discussion is beyond our scope

100 Common-Base Has Highest Gain, but Layout Parasitics Matter 30 V. Paidi, Z. Griffith, M. Dahlström base plug 25 U ignores layout parasitics base L b MSG/MAG, db Common emitter Common base 5 Common Collector Frequency, GHz Without C ce, L b C ce interconnect t metal emitter base N- collector C ce collector MSG/M MAG With C and L ce b With C ce N+ subcollector semi-insulating InP Frequency, GHz

101 mm-wave IC results

102 Deep Submicron Bipolar Transistors for GHz Amplification M. Urteaga 40 raw 0.3 μm transistor: high power 200 GHz Transistor Gains, db U unbounded U U MSG/MAG H Frequency, GHz 8 S21, db transistor amplifier: 175 GHz Frequency, GHz 10 gain, db transistor amplifier: GHz Frequency (GHz)

103 175 GHz Single-Stage Amplifier Miguel Urteaga 10 30Ω, 0.2ps 0.2pF 50Ω 80Ω, 1.2ps OUT 5 0 S21 S11 S22 IN 50Ω 30Ω, 1.2ps 80Ω, 1.2ps 50Ω 30Ω, 0.6ps db Freq. (GHz) 6.3 db gain at 175 GHz

104 172 GHz Common-Base Power Amplifier V. Paidi, Z. Griffith, M. Dahlström Input Matching Network Output Loadline Match V in V out R L S,S,S, db db gain S dbm saturated output power 4.5-dB associated power gain at 172 GHz DC bias: Ic=47 ma, Vcb=2.1V. transistor fmax was 300 GHz 15 Gain, db, Ou utput Power r, dbm S 22 S Frequency, GHz 5-5 Gain Output Power PAE Input Power, dbm 2 fingers x 0.8 um x 12 um, ~250 GHz f τ, 300 GHz f max, V br ~ 7V, ~ 3 ma/um 2 current density PAE (% %)

105 176 GHz Two-Stage Amplifier V. Paidi, Z. Griffith, M. Dahlström 7-dB gain at 176 GHz 8.1 dbm output power, 6.3 db power gain at 176 GHz 9.1 dbm saturated output power at 176 GHz transistor fmax was 300 GHz V eb,bias λ/4 at f 0 V in Input Matching Network Output Loadline Matching Network Input Matching Network Output Loadline Matching Network V out R L 50 Ohms 50 Ohms λ/4 at f 0 Ga ain, db, Outp put Power, dbm Gain Output Power PAE Input Power, dbm PAE (%) S, S, S db S 11 S 22 V cb,bias S Frequency, GHz

106 measurement issues

107 & GHz On-Wafer Network Analysis HP8510C VNA, Oleson Microwave Lab mm-wave Et Extenders coplanar wafer probes made by: GGB Industries, Cascade Microtech connection via short length of waveguide Internal bias Tee s in probes for biasing active devices GGB Wafer Probes 330 GHz available with bias Tees GHz set-up is similar DC-50 GHz set is standard coax- based system: SNR ok only to ~30 GHz

108 High Frequency HBT Gain Measurements : Standard Pads Measuring wideband transistors is very hard! Much harder than measuring amplifiers. Determining fmax in particular is extremely difficult once it exceeds 400 GHz Standard d "short pads" must strip pad capacitance must strip pad inductance--or ft will be too high! cal bad above ~25 GHz due to substrate coupling make pads small, or lift them off the InP! cal bad above ~25 GHz due to probe coupling use small probe pitch, use shielded (infinity) probes Gain ns (db) A jbe = 0.6 x 4.3 um 2 35 h 30 h 21 I c = 20.6 ma, V ce = 1.53 V J = 8.0 ma/um 2, V = 0.6 V e cb f = 450 GHz, f = 490 GHz t max t max ins (db) Ga Frequency (Hz) 10 MAG/MSG A =06x43um jbe U I c = 20.6 ma, V ce = 1.53 V J e = 8.0 ma/um 2, V cb = 0.6 V 5 f = 450 GHz, f = 490 GHz t max k Frequency (Hz) 10 12

109 High Frequency HBT Measurements : On-Wafer LRL Extended Reference planes transistors placed at center of long on-wafer line LRL standards placed on wafer large probe separation probe coupling reduced still should use the best-shielded probes available Problem: substrate mode coupling method will FAIL if lines couple to substrate modes method works very poorly with CPW lines need on wafer thin-film microstrip lines CPW

110 CPW has parasitic modes, coupling from poor ground plane integrity k z 0V +V 0V +V +V +V -V 0V +V 0V CPW mode 0V Microstrip mode Substrate modes 0V Slot mode ground straps suppress slot mode, but multiple ground breaks in complex ICs produce ground return inductance ground vias suppress microstrip mode, wafer thinning suppresses substrate modes Microstrip has high via inductance, has mode coupling unless substrate is thin. k z We prefer (credit to NTT) thin-film microstrip wiring, inverted is best for complex ICs M. Urteaga, Z. Griffith, S. Krishnan

111 advanced fabrication processes

112 Parasitic Reduction for Improved InP HBT Bandwidth At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics wide emitter contact: low resistance narrow emitter junction: scaling (low R bb /A e ) Pb base thick extrinsic base : low resistance thin intrinsic base: low transit time SiO2 N- SiO2 wide base contacts: low resistance narrow collector junction: low capacitance N+ subcollector These are planar approximations to radial contacts: 2ρρ r bulk 2 R = bulk ln πl W 2ρc Rcontact πlr R total,min extrinsic base extrinsic emitter = N+ subcollector = 2ρ πl bulk ρ ln Wρ contact bulk greatly reduced access resistance extrinsic base Much more fully developed in Si

113 Yield & Scaling Problems: Liftoff, Undercut, Planarity liftoff failure: emitter-base short-circuit base contact base sub collector S.I. substrate excessive emitter undercut base contact base sub collector S.I. substrate planarization failure: interconnect breaks base sub collector S.I. substrate Yield quickly degrades as emitters are scaled to submicron dimensions

114 Controlling Emitter Undercut: Wet-Etch Mesa Process 0.5 um metal ~0.4 um junction cto InP 0.7 um Front and side views 0.6 um metal ~0.4 um junction InAlAs Front and side views Smaller emitters lower yield. Need better fabrication process

115 Manufacturable Emitter Dielectric Sidewall Processes First-Generation: UCSB and Rockwell Scientific Miguel Urteaga Si 3 N 4 thin emitter base contacts by planarization & etch-back Ic (m ma) Vce (V) Urteaga, Rodwell, Pierson, Rowell, Brar, Nguyen, Nguyen: UCSB, RSC, GCS 266 GHz f t, 133 GHz f max,, C cb /I c =0.4 ps/v 2nd-Generation: Rockwell Scientific Miguel Urteaga, Petra Rowell electroplated emitter and base contacts 250 nm emitter Urteaga, Rowell, Pierson, Brar: RSC

116 1 st -Generation Polycrystalline Extrinsic Emitter D. Scott, Y. Wei 30 Emitter junction area: 0.3 x 4 μm Self-aligned, A E_junction =0.3 um x 4 um 1 (db), K U, MSG/MAG, h U MAG/MSG h 21 I =9.72 ma C V =1.2 V CE I C (A) I bstep =100 ua 5 f =148GHz MAX f =280 GHz T K Frequency (GHz) V (V) CE Approach Wide emitter contact for low emitter access resistance Thick extrinsic base for low base resistance Self-aligned refractory base contacts Enabling Technology Low-resistance polycrystalline InAs In-band Fermi-level pinning eliminates barriers Challenges Very complex process Hydrogen passivation Resistance of Refractory contacts

117 2 nd -Generation Epitaxial Extrinsic Emitter C. Kadow W sw W e,cont We Web W b,cont InP anti-oxidation layer InAlAs current-block layer emitter contact InGaAs extrinsic base etch stop layer InGaAs intrinsic base BC grade collector T p regrown emitter W P base contact W under T c pedestal extrinsic base: 150 Ω/square N+ sub collector S.I. InP substrate I [m ma] c I = 2 ma b, step V [V] ce J [ma A/um 2 ] c I, I [A] b c 10-1 V ff t = 0.0 V offset I B I C W E = 1.0 µm Max( β ) = V [V] be

118 1 st -Generation Collector Pedestal Implant Y. Dong Implant N+ Pedestal Formed P- P- N+ N+ N+ S.I. S.I. HBT regrowth Junction Fabrication P- N+ P- N+ N+ N+ S.I. S.I. J (ma/μ μm 2 ) e A je = 0.4 x 7 μm 2 I step = 500 μa b b HBT with pedestal HBT without pedestal 20 mw/μm 2 device failure V (V) ce Good DC characteristics 5.4 V breakdown with a 90 nm thick collector 35 A E =0.7 x 8 um um pedestal C CB (ff) um pedestal um pedestal Reduced extrinsic Ccb Reduced thermal resistance J E (ma / um 2 ) ~2:1 reduction in collector base capacitance

119 Pedestal: Projected 300 nm ρ ρ J e c, emitter c, base = 15 = R ex A E = 10 Ω - μm ma/ μm = 6 Ω - μm ps wiring delay on collector bus 2 2 W 50 nm eb 300 nm W e W b,cont 300 nm emitter contact f clock (divider) f τ C V cb 4 V 275 GHz = 530 GHz f max / I = 0.15 ps/v br,ceo c = 770 GHz InGaAs base BC grade collector 30nm base contact T p 200nm T c 100nm emitter W P 500nm pedestal N+ sub collector Wunder 100nm S.I. InP substrate

120 RGE+Pedestal: Projected 250 nm 20 nm, nm, / cm / cm 3 3 intrinsic base extrinsic base (145Ω/square) W e,cont 500 nm 250 W nm e Web W sw 50 nm W b,cont 300 nm InP anti-oxidation layer InAlAs current-block layer emitter contact InGaAs extrinsic base etch stop layer InGaAs intrinsic base BC grade collector T p 300nm 100nm T c regrown emitter W P 450nm pedestal base contact W100nm under N+ sub collector S.I. InP substrate t ρc, emitter = 6 Ω - μm ρ J c, base e = 17 R ex A E = 10 Ω - μm ma/ μm 2 ~ 3 Ω - μm ps wiring delay on collector bus 2 2 f clock (divider) 330 GHz f τ C V cb = 650 GHz / I br,ceo, c = 0.17 ps/v 4 V f max = 900 GHz

121 Indium Phosphide HBTs InP HBT now: at 500 nm scaling generation 455 GHz f t & 485 GHz f max 150 GHz static dividers & 180 GHz amplifiers demonstrated 200 GHz digital latches & 300 GHz amplifiers are feasible InP HBT: future, at 125 nm scaling generation 2:1 increase in bandwidth (?) ~1 THz f t & f max, 400 GHz digital latches & 600 GHz amplifiers??? demands 4:1 better Ohmic contacts demands 4:1 increased current density. Applications: 160+ Gb/s fiber ICs, 300 GHz MIMICs for communications, radar, & imaging GHz ADCs / DACs / DDFS / etc. & applications unforeseen & unanticipated

122 End