Developing Bipolar Transistors for Sub-mm-Wave Amplifiers and Next-Generation (300 GHz) Digital Circuits

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1 Plenary, Device Research Conerence, State College, PA, June 26, 26 Developing Bipolar Transistors or Sub-mm-Wave Ampliiers and Next-Generation (3 GHz) Digital Circuits Mark Rodwell University o Caliornia, Santa Barbara Collaborators Z. Griith, E. Lind, V. Paidi, N. Parthasarathy, C. Sheldon, U. Singisetti ECE Dept., University o Caliornia, Santa Barbara Pro. A. Gossard, Dr. A. Jackson, Mr. J. English Materials Dept., University o Caliornia, Santa Barbara M. Urteaga, R. Pierson, P. Rowell Rockwell Scientiic Company X. M. Fang, D. Lubyshev, Y. Wu, J. M. Fastenau, W.K. Liu International Quantum Epitaxy, Inc. Lorene Samoska, Andy Fung Jet Propulsion Laboratories S. Lee, N. Nguyen, and C. Nguyen Global Communication Semiconductors Sponsors J. Zolper, S. Pappert, M. Rosker DARPA (TFAST, ABCS, SMART) I. Mack, D. Purdy, M. Yoder Oice o Naval Research rodwell@ece.ucsb.edu , ax

2 Our Speciic Focus : Present III-V transistors have enabled - 3 GHz ampliiers GHz clock rate digital ICs. So, how can we build next-generation ICs? - 6 GHz ampliiers. - 3 GHz digital clock rate.

3 More Generally : Can we build THz transistors? What do we mean by THz transistors? What are they or? How do we make them? What are the requency limits o bipolar integrated circuits?

carrier 34 GHz & 6 GHz imaging systems 32 Gb/s iber optics & adaptive

4 THz Transistors: What Are They For? High-Resolution Microwave ADCs and DACs mm-wave radio: 4+ Gb/s on 25 GHz carrier 34 GHz & 6 GHz imaging systems 32 Gb/s iber optics & adaptive equalizers or 4 Gb/s... Why develop transistors or mm-wave & sub-mm-wave applications? compact ICs supporting complex high-requency systems.

5 THz Transistors: What does this mean? A 1 THz current-gain cuto requency ( τ ) alone has little value a transistor with 1 GHz τ and 1 GHz max cannot ampliy a 11 GHz signal. RF-ICs & MIMICs need high power-gain cuto requency ( max ) impedance matching is hard i τ is low. 1+ GHz digital also needs low (C depletion ΔV / I ) and low (I*R parasitic /ΔV ). So, how do we make a transistor with >1 THz τ >1 THz max <5 s CΔV / I charging delays?

6 Key Perormance Parameters or MMICs / RF-IC's Power ampliiers need breakdown voltage & power density MIMIC / RF-ICs need gain ---hence max P max = 8 ( 1 )( V max V min ) I max 3 25 U MSG/MAG, db Common emitter Common base Common Collector 5 max Frequency, GHz Low-Noise ampliiers need moderate associated gain and low noise F min, HEMT 1+ 2 gmi( RS + Rg + Ri ) Γ τ

7 Key Perormance Parameters or Fast Logic Gate Delay Determined by : ΔV Depletion capacitance charging through the logic swing ΔV LOGIC ( Ccb + Cbe,depletion ) IC Depletion capacitance charging through the base resistance R bb ( C + C ) Supplying base + collector I C Rbb( τ b + τ c ) ΔVLOGIC The logic swing must be at least LOGIC cbi stored charge kt > 4 q be,depletion through the base resistance + R ex I c ( τ out out in in clock clock clock clock ( ΔV I )( C + C ) R b High ex + τ ) c LOGIC ( I / C ) C J typicall y 1-25% o total delay; Delay not well correlated with C cb max, Kirk cb be,depl is a key HBT design objective. = 2εv electron (V ce, operating CcbΔVLOGIC ΔV LOGIC = IC 2V CE,min must be very low or low ΔV is 55% - 8% o total. logic + V τ ce,ull depletion A collector T A emitter 2v at high J C ) / T electron 2 c Design HBTs or ast logic, not or high t & max

8 HBT Scaling Laws HBT Scaling Roadmaps

9 Bipolar Transistor Scaling Laws Goal: double transistor bandwidth when used in any circuit keep constant all resistances, voltages, currents reduce 2:1 all capacitances and all transport delays key device parameter collector depletion layer thickness base thickness emitter junction width collector junction width emitter resistance per unit emitter area current density base contact resistivity (i contacts lie above collector junction) base contact resistivity (i contacts do not lie above collector junction) required change decrease 2:1 decrease 1.414:1 decrease 4:1 decrease 4:1 decrease 4:1 increase 4:1 decrease 4:1 unchanged Epitaxial scaling: layer thicknesses Lithographic scaling: junction dimensions Resistance scaling: contact resistance and thermal resistance

10 InP HBT Scaling Roadmaps Key scaling challenges emitter & base contact resistivity current density device heating collector-base junction width scaling & Yield! key igures o merit or logic speed

11 Present Status o Fast III-V Transistors max (GHz) 2 GHz GHz 4 GHz Updated July GHz E. Lind et al, this conerence 5 nm = 25 nm t (GHz) max τ RSC UIUC_SHBT NTT Fujitsu HEMT SFU UIUC_DHBT UCSB 5 nm NGST Pohang HRL IBM SiGe Vitesse UCSB 25 nm popular ( τ (1 τ power ampliiers: PAE, associated gain, mw/ μm low noise ampliiers: F or + τ digital : τ ( C ( R ( R ( τ min b max max + 1 clock cb ex bb max ) / 2, associated gain, I, hence I c c + τ / ΔV ), / ΔV ), c ) alone max much better metrics : ΔV / I c ) 1 ), metrics : Red = manuacturable technology or 1,- transistor ICs

12 Scaling Generations

25: InP DHBTs @ 5 nm Scaling Generation emitter base 5 nm width 16 Ω μm 2 contact ρ 3 width, 2 Ω μm 2 contact ρ collector 15 nm

13 25: InP 5 nm Scaling Generation emitter base 5 nm width 16 Ω μm 2 contact ρ 3 width, 2 Ω μm 2 contact ρ collector 15 nm thick, 5 ma/μm 2 current density 5 Vbreakdown τ max power ampliiers digital clock rate (static dividers) 4 GHz 5 GHz 25 GHz 16 GHz

14 26: 25 nm Scaling Generation, 1.414:1 aster emitter 5 25 nm width 16 9 Ω μm 2 contact ρ base 3 15 width, 2 1 Ω μm 2 contact ρ collector 15 1 nm thick, 5 1 ma/μm 2 current density Vbreakdown τ 4 5 GHz max 5 7 GHz power ampliiers GHz digital clock rate GHz (static dividers)

15 125 nm Scaling Generation almost-thz HBT emitter nm width Ω μm 2 contact ρ base width, Ω μm 2 contact ρ collector nm thick, ma/μm 2 current density V breakdown τ GHz max GHz power ampliiers GHz digital clock rate GHz (static dividers)

16 65 nm Scaling Generation beyond 1-THz HBT emitter nm width Ω μm 2 contact ρ base nm width, Ω μm 2 contact ρ collector nm thick, ma/μm 2 current density V breakdown τ GHz max GHz power ampliiers GHz digital clock rate GHz (static dividers)

17 Scaling Challenges

Reducing Contact Resistivity Pd or Pt solid-phase-reaction contacts Regrowth or wider emitter contacts current-block layer emitter contact regrown emitter base contact extrinsic base intrinsic base

Chor et al, JAP 2 Wrap-around emitter contact W e T e R R ex ex at W 1 = L A e e e ρcontactρ 2W = 1Ω - μm = 2 nm 2 e bulk ErAs in-situ MBE emitter contacts grown in-situ by MBE no oxides, no

18 Reducing Contact Resistivity Pd or Pt solid-phase-reaction contacts Regrowth or wider emitter contacts current-block layer emitter contact regrown emitter base contact extrinsic base intrinsic base drit collector pedestal N+ sub collector S.I. InP substrate TEM : Lysczek, Robinson, & Mohney, Penn State Sample: Urteaga, RSC E. F. Chor et al, JAP 2 Wrap-around emitter contact W e T e R R ex ex at W 1 = L A e e e ρcontactρ 2W = 1Ω - μm = 2 nm 2 e bulk ErAs in-situ MBE emitter contacts grown in-situ by MBE no oxides, no contaminants Lattice matched ew deect states no Fermi level pinning Thermodynamically stable little intermixing base drit collector sub-collector Zimmerman, Gossard & Brown *A. Guivarc h, Electron. Lett.(1989) **C.J.Palmstrøm Appl. Phys. Lett. (199) Q. G. Sheng, J. Appl. Phys. (1993) A Guivarc h, J. Appl. Phys. (1994)

19 Emitter-Base Degeneracy 1.5 Ω μm 2 Eective Junction Resistance E n E c 1 ma/ μm 2 near degeneracy in emitter - base junction Back o envelope : qn c v thermal = 22 ma/ μm 2 thanks to Bill Frensley or BandPro! Better Approach : ballistic model, J Fermi - Dirac integral * 2 qme ( kt ) F 2 3 1(( E n Ec) / kt ) 4π h [Liang & Lundstrom, unpublished] Approximate series resistance model V be φ built in ρ eq ( kt / q)ln( J = 1.5 Ω μm e 2 / J o ) + J ρ or InP, e ρ eq eq + O( J 1/ m 2 e * e ) J(mA/um^2) Fermi-Dirac Boltzmann Equivalent series resistance approximation V - be φ Degeneracy contributes ~ 1-2 Ω-μm 2 to observed emitter resistivity (?). Solutions: higher mass emitter? superlattice emitter?

20 Temperature Rise Within Transistor & Substrate For each doubling in digital clock rate emitter widthw transistor spacing Increased junction temperature e decreases 4 :1 D HBT decreases 2 :1 cylindrical heat low near junction r < L e spherical heat low planar heat low or L < r < / 2 or r > / 2 e D HBT D HBT P L e P P Tsub D / 2 ΔT substrate ln 2 πk InPLE We πk InP LE D K InP D increases logarithmically with scaling negligible variation with scaling increases quadratically with scaling IF T sub is constant

21 Temperature Rise Within Transistor & Substrate cylindrical heat low near junction spherical low or r > L e planar low or r > / 2 D HBT P L e P P Tsub D / 2 ΔT substrate ln 2 πk InPLE We πk InP LE D K InP D increases logarithmically insigniicant variation increases quadratically i T sub is constant Agressively reducing substrate thickness T allows acceptable substrate temperature rise even at 3 GHz digital clock rate. Wiring lenghts, clock rates, power densities, etc. scaled rom demonstrated 15 GHz digital ICs sub temperature rise in substrate, Kelvin Tsub = 15 μm ( 16 GHz/ clock ) master-slave D-Flip-Flop clock requency, GHz

Temperature Rise Within Package For each doubling in digital clock rate HBT spacings D HBT chip dimensionsw decrease 2 :1 chip decrease 2 :1 Total Package

transistor (1 Ω logic load resistor) 1 2 3 4 5 6 GHz clock, At 3 ma per transistor (1 Ω loading) acceptable package temperature rise with 1 transistors / IC

22 Temperature Rise Within Package For each doubling in digital clock rate HBT spacings D HBT chip dimensionsw decrease 2 :1 chip decrease 2 :1 Total Package Temperature Rise 1 1 Pchip ΔTpackage + π 2 K W Cu chip package temperature rise, Kelvin ma per transistor (25 Ω logic load resistor) 3 ma per transistor (1 Ω logic load resistor) GHz clock, At 3 ma per transistor (1 Ω loading) acceptable package temperature rise with 1 transistors / IC even at 3 GHz digital clock rate. Assumptions : Transistor spacing : 2 μm (15 GHz/ V ce = 2 V bias 1 transistors/ic IC power = 1.5 ( transistor dissipation) clock )

23 Scaling o Breakdown Voltage with InP/InGaAs InP DHBTs Erik Lind I collector is thinned without thinning grade and setback layers.....then Zener tunneling through grade & setback layers can reduce BVCEO nm thick collector Energy (ev) base collector distance (nm) Energy (ev) base 6 nm thick collector collector Should we switch rom type-i DHBT to type-2, eliminating the grade but sacriicing base transport? distance (nm) Type-1 DHBT: InGaAs base Type-2 DHBT: InGaAsSb base Or, should we simply thin the grade, using ewer superlattice periods?...or other approaches...

24 Breakdown Voltage: What do we really need? 1 8 J e (ma/μm 2 ) V BVCEO V ce (V) P max = 8 ( 1 )( V ) max V min I max

25 Breakdown Voltage: What do we really need? 1 8 J e (ma/μm 2 ) mw/um V BVCEO 2 1 mw/um V ce (V) P max = 8 ( 1 )( V ) max V min I max

26 Breakdown Voltage: What do we really need? 1 J e (ma/μm 2 ) 8 6 4! V ce (V) P max = 8 ( 1 )( V ) max V min I max

27 Breakdown Voltage: What do we really need? 1 high τ & max low τ & max 8 J e (ma/μm 2 ) V ce (V) P max = 8 ( 1 )( V ) max V min I max bandwidth decreases at high V ce due to velocity-ield characteristics

28 Scaling challenges: What looks easy, what looks hard? key device parameter collector depletion layer thickness base thickness emitter junction width collector junction width emitter resistance per unit emitter area current density base contact resistivity (i contacts lie above collector junction) base contact resistivity (i contacts do not lie above collector junction) required change decrease 2:1 decrease 1.414:1 decrease 4:1 decrease 4:1 decrease 4:1 increase 4:1 decrease 4:1 unchanged Hard: Thermal resistance (ICs) Emitter contact + access resistance Yield in deep submicron processes Contact electromigration (?), dark-line deects (?) Probably not as hard : Maintaining adequate breakdown or 3 V operation...

to: transistors: BJTs & HBTs, MOSFETS & HEMTs, Schottky diodes, photodiodes, photo mixers, RTDs, Applies

29 Frequency Limits and Scaling Laws o (most) Electron Devices τ C R R top thickness area / bottom ρ contact thickness / area 1/ stripe lenght R bottom R top resistance capacitance transit time device bandwidth applies to: transistors: BJTs & HBTs, MOSFETS & HEMTs, Schottky diodes, photodiodes, photo mixers, RTDs, Applies whenever AC signals are removed though Ohmic contacts Semiconductor lasers avoid R/C/τ limits by radiating through end acets

30 Mesa HBTs

31 Mesa DHBTs at the 5-6 nm Scaling Generation Zach Griith 1.7 μm base-collector mesa 1.3 μm base-collector mesa 6 nm emitter width

32 Zach Griith InP DHBT: 6 nm lithography, 12 nm thick collector, 3 nm thick base Gains (db) 35 3 U 25 h A =.6 x 4.3 um 2 jbe 1 I = 2.6 ma, V = 1.53 V c ce 5 J = 8. ma/um 2, V =.6 V e cb = 45 GHz, = 49 GHz t max Frequency (Hz) 1 12 I b, I c (A) Gummel characteristics V CB =. V (dashed) V =.3 V (solid) CB I c n = 1.12 c I b n = 1.41 b V (V) be C cb /A e (F/μm 2 ) A jbe =.6 x 4.3 μm 2 1.5ps/V 1. ps/v A jbc = 1.3 x 6.5 μm 2 V = -.3 V cb -.2 V. V.8 ps/v.6 ps/v.4 ps/v.2 V V =.6 V cb C cb /I c =.2 ps/v J (ma/μm 2 ) e 5 Ccb (F) β 4, V BR,CEO = 3.9 V. Emitter contact R cont < 1 Ω μm 2 Base : R sheet = 61 Ω/sq, R cont = 4.6 Ω μm 2 Collector : R sheet = 12.1 Ω/sq, R cont = 8.4 Ω μm 2

33 InP DHBT: 6 nm lithography, 75 nm thick collector, 2 nm base Zach Griith DC characteristics 2. V cb = V.1 V =. V (dashed) CB V =.3 V (solid) CB Peak τ J e (ma/μm 2 ) I b, I c (A) I c n = 1.15 c I b n = 1.47 b V ce (V) V be (V) Peak max A je = μm 2, I b,step = 175 μa Average β 5, BV CEO = 3.2 V, BV CBO = 3.4 V (I c = 5 μa) Emitter contact (rom RF extraction), R cont 8.6 Ω μm 2 Base (rom TLM) : R sheet = 85 Ω/sq, R cont = 16 Ω μm 2 Collector (rom TLM) : R sheet = 12. Ω/sq, R cont = 4.7 Ω μm 2 RF characteristics

34 Variation o Transistor Bandwidth with Scaling 2 GHz GHz 4 GHz 5 GHz = max τ popular metrics : ( τ (1 τ or + τ τ max max + 1 max alone ) / 2 max ) 1 max (GHz) Updated July t (GHz) much better power ampliiers: PAE, associated gain, mw/ μm low noise ampliiers: F digital : ( C ( R ( R ( τ min clock b cb ex bb, associated gain, I, hence ΔV / I I c c + τ / ΔV ), / ΔV ), c ) c ), metrics :

35 Variation o Transistor Bandwidth with Scaling 2 GHz GHz 4 GHz 5 GHz = max τ popular metrics : ( τ (1 τ or + τ τ max max + 1 max alone ) / 2 max ) 1 max (GHz) Updated July 5 26 epitaxial scaling t (GHz) much better power ampliiers: PAE, associated gain, mw/ μm low noise ampliiers: F digital : ( C ( R ( R ( τ min clock b cb ex bb, associated gain, I, hence ΔV / I I c c + τ / ΔV ), / ΔV ), c ) c ), metrics :

36 Variation o Transistor Bandwidth with Scaling max (GHz) 2 GHz GHz 4 GHz Updated July GHz = epitaxial scaling t (GHz) max τ? epitaxial, lithographic, & contact resistance scaling? popular ( τ (1 τ power ampliiers: PAE, associated gain, mw/ μm low noise ampliiers: F or + τ digital : τ ( C ( R ( R ( τ min b max max + 1 clock cb ex bb max ) / 2, associated gain, I, hence I c c + τ / ΔV ), / ΔV ), c ) alone max much better metrics : ΔV / I c ) 1 ), metrics :

8 um x 12 um, ~25 GHz τ, 3 GHz max, V br ~ 7V, ~ 3 ma/um 2 current density S 21, S 11, S

37 175 GHz Ampliiers with 3 GHz max Mesa DHBTs V. Paidi, Z. Griith, M. Dahlström 7 db gain 175 GHz 7.5 mw output power 2 ingers x.8 um x 12 um, ~25 GHz τ, 3 GHz max, V br ~ 7V, ~ 3 ma/um 2 current density S 21, S 11, S 22 db S 11 S 22 S 21 7-dB small-signal gain at 176 GHz 8.1 dbm output power at 6.3 db gain Frequency, GHz

5 6.9.59 data emitter ollowers.5 x 4.5.99 clock current steering.5 x 4.5.74.86 V cb V.6.6 1.7 τ GHz 31 26 31 28 max GHz 358 268 358 28 4.4 4.4 clock emitter ollowers.5 x 5.5 4.

38 UCSB / RSC / GCS 15 GHz Static Frequency Dividers IC design: Z. Griith, UCSB HBT design: RSC / UCSB / GCS IC Process / Fabrication: GCS Test: UCSB / RSC / Mayo size current density C cb /I c units μm 2 ma/μm 2 psec / V data current steering.5 x data emitter ollowers.5 x clock current steering.5 x V cb V τ GHz max GHz clock emitter ollowers.5 x Output Power (dbm) requency (GHz) Output Power (dbm) requency (GHz) Minimum input power (dbm) P DC,total = mw divider core without output buer mw probe station 25 C requency (GHz)

39 4:1 Mux in Vitesse VIP3 InP HBT Process T. Swahn et al 15 Gb/s 16 Gb/s

5 to 5 Ω μm 2 Base contact resistance is < 5 Ω μm 2 --hard

40 25 nm scaling generation DHBTs Zach Griith 1 % I-line lithography Emitter contact resistance reduced 4%: rom 8.5 to 5 Ω μm 2 Base contact resistance is < 5 Ω μm 2 --hard to measure Recall, 1/8 μm scaling generation needs 5 Ω μm 2 emitter ρ c

41 .3 µm emitter junction, W c /W e ~ 1.6 Zach Griith

42 First mm-wave results with 25 nm InP DHBTs Erik Lind 15 nm material 25 nm emitter width τ = 42 GHz max = 65 GHz ~6 V breakdown 3 mw/um 2 power handling results to be presented postdeadline this conerence, E. Lind, Z. Griith et al

max (GHz) Epitaxial scaling at 25 nm design rules 2 GHz 8 7 6 5 4 3 2 1 3 GHz 4 GHz Updated July 5 26 5 GHz = 1 2 3 4 5 6 7 8 t (GHz) process ailure max τ new ab run in progress?

43 max (GHz) Epitaxial scaling at 25 nm design rules 2 GHz GHz 4 GHz Updated July GHz = t (GHz) process ailure max τ new ab run in progress?? 1 nm thick collector Energy (ev) 6 nm thick collector Energy (ev) base -.5 collector -1. τ / max, proj ~ 575/55 GHz valence band -1.5 at V =. V cb 25 nm emitter width distance (nm) J e =, 2.5, 5., 7.5, 1, 12.5 ma/μm 2 J e =, 5, 1, 15, 2, 25 ma/μm 2 Γ-electron valley Γ-electron valley. base -.5 collector -1. valence band -1.5 V =. V cb distance (nm) Zach Griith

33 GHz Cascode Power Ampliiers In Design Navin Parthasarathy P sat = 5 mw (17 dbm) 1-dB associated power gain use 65 GHz max transistors Gain (db), Output Power

44 33 GHz Cascode Power Ampliiers In Design Navin Parthasarathy P sat = 5 mw (17 dbm) 1-dB associated power gain use 65 GHz max transistors Gain (db), Output Power (dbm) 2 Output Power 15 Gain 1 PAE Input Power, dbm PAE (%) 15 S 21, S 11, S 22 ( db ) S 22 S Frequency, GHz S 11

45 Manuacturable Process Flows

Parasitic Reduction or Improved InP HBT Bandwidth At a given scaling generation, intelligent choice o device geometry reduces extrinsic parasitics wide emitter contact: low resistance narrow emitter

46 Parasitic Reduction or Improved InP HBT Bandwidth At a given scaling generation, intelligent choice o device geometry reduces extrinsic parasitics wide emitter contact: low resistance narrow emitter junction: scaling (low R bb /A e ) thick extrinsic base : low resistance thin intrinsic base: low transit time SiO2 N- P base SiO2 wide base contacts: low resistance narrow collector junction: low capacitance N+ subcollector These are planar approximations to radial contacts: R R R bulk contact total,min 2ρ bulk = ln πl 2ρc = πlr 2ρ = πl bulk 2 r W ρ ln Wρ contact bulk extrinsic base extrinsic emitter N+ subcollector greatly reduced access resistance extrinsic base Much more ully developed in Si

4 I bstep =1 ua 5 =148GHz MAX =28 GHz T K 1 1 1 1 Frequency (GHz).2.5 1 1.

47 Polycrystalline Extrinsic Emitter D. Scott, Y. Wei 3 Emitter junction area:.3 x 4 μm 2.14 Sel-aligned, A E_junction =.3 um x 4 um U, MSG/MAG, h 21 (db), K U MAG/MSG h 21 I =9.72 ma C V =1.2 V CE I C (A) I bstep =1 ua 5 =148GHz MAX =28 GHz T K Frequency (GHz) V (V) CE Approach Wide emitter contact or low emitter access resistance Thick extrinsic base or low base resistance Sel-aligned reractory base contacts Enabling Technology Low-resistance polycrystalline InAs In-band Fermi-level pinning eliminates barriers Challenges Very complex process Hydrogen passivation Resistance o Reractory contacts

Sel-aligned Sidewall Spacer (S3) Manuacturable HBT Process Miguel Urteaga, Richard Pierson, Petra Rowell Keisuke Shinohara, Berinder Brar Sel-aligned contacts are critical to submicron device scaling.

48 Sel-aligned Sidewall Spacer (S3) Manuacturable HBT Process Miguel Urteaga, Richard Pierson, Petra Rowell Keisuke Shinohara, Berinder Brar Sel-aligned contacts are critical to submicron device scaling. Eliminates lithography alignment tolerance. RSC s S3 HBT process utilizes electroplated contacts with dielectric sidewalls. Eliminates low yield lito processes rom base-emitter junction ormation. Electroplated base contact is selectively deposited on the base semiconductor. Process enables deep submicron scaling while maintaining high levels o perormance and yield H21 (red), U(blue) (db) J E = 6.5 ma/um 2 V CE = 1.5 V RF Gains τ = 45GHz max = 392 GHz Frequency (GHz) Electroplate emitter contact Etch emitter semiconductor Base Contact Emitter Contact Dielectric sidewall deposition Base contact patterning S3 Process Flow Dielectric Sidewall SEM Cross-Section o B-E Junction Selectively deposit base metal

VIP-2 HBT structure: Dielectric Sidewall Minh Le et al Dielectric Spacer allows tightly controlled separation between Emitter and Base to minimize Rbx and Cbcx E B Cross section Note that the base

49 VIP-2 HBT structure: Dielectric Sidewall Minh Le et al Dielectric Spacer allows tightly controlled separation between Emitter and Base to minimize Rbx and Cbcx E B Cross section Note that the base via is olded on top o the transistor to reduce Cbc C E B C Layout G. He, J. Howard, M. Le, P. Partyka, B. Li, G. Kim, R. Hess, R. Bryie, R. Lee, S. Rustomji, J. Pepper, M. Kail, M. Helix, R. Elder, D. Jansen, N. Har, J. Prairie, E. Daniel, and B. Gilbert, Sel-Aligned InP DHBT with t and max over 3 GHz in a new manuacturable technology, IEEE Electron Device Lett., vol. 25, no. 8, pp , Aug. 24.

12 ma 12 ma 1 Ohm 5 Ohm bus 1 Ohm 3 ma 3 ma 3 ma Low-Power CML 1 Ohm loaded switch 3 ma 3 ma x 3 x 3 V = 27 mw/latch High speed @ low power = low

50 Low-Power High-Speed Logic Small Pad Capacitance 5 Ohm 5 Ohm bus 5 Ohm ECL with impedance-matched 5 Ohm bus: 25 Ohm load switch 12 ma 12 ma x 7 x 4 V = 336 mw/latch 12 ma 5 Ohm 5 Ohm bus 5 Ohm CML with impedance-matched 5 Ohm bus: 25 Ohm load switch 12 ma 12 ma x 3 x 3 V = 18 mw/latch 12 ma 12 ma 12 ma 1 Ohm 5 Ohm bus 1 Ohm 3 ma 3 ma 3 ma Low-Power CML 1 Ohm loaded switch 3 ma 3 ma x 3 x 3 V = 27 mw/latch High low power = low C wiring, low C cb, pad base pad capacitance key parasitic in low power bipolar logic CML operates at lower Vce reduced Kirk-eect-limited current

Subcollector & Pedestal Implant Navin Parthasarathy Fe Implant Subcollector Implant Pedestal Implant Epitaxial growth Junction Fabrication Fe S.I. Fe N+ S.I. N+ Fe N+ Fe N+ N+ S.I. N+ Fe N+ Fe N+ N+ S.I. N+ Fe N+ Fe N+ N+ S.I. Gains (db) 35 3 25 2 15 1 5 h 21 U t = 352 GHz, max = 43 GHz 1 9 1 1 1 11 1 12 Frequency (Hz) I c (ma) 2 15 1 5 I = 5 μa b start I = 1 μa b step β ~ 4 BV CEO = 6.

51 Subcollector & Pedestal Implant Navin Parthasarathy Fe Implant Subcollector Implant Pedestal Implant Epitaxial growth Junction Fabrication Fe S.I. Fe N+ S.I. N+ Fe N+ Fe N+ N+ S.I. N+ Fe N+ Fe N+ N+ S.I. N+ Fe N+ Fe N+ N+ S.I. Gains (db) h 21 U t = 352 GHz, max = 43 GHz Frequency (Hz) I c (ma) I = 5 μa b start I = 1 μa b step β ~ 4 BV CEO = 6.8V V (V) CE 5 Subcollector implant eliminates C cb in base pad area. Pedestal urther reduces C cb. C cb (F) mesa 2 A = 1.3 x 8.5 um 2 jbc implanted sub-collector implanted sub-collector + pedestal V (V) cb. Ccb / A e (F/um2 ) I b, I c (A) A =.65 x 4.3 μm.1 2 jbe I c n = 1.18 c I b n = 1.53 b 5 pa V =.3 V (solid) CB V =. V (dashed) CB V (V) be

52 Ultra low power CML Static Frequency Divider: RSC S 3 Process with Pedestal on ation Device technology, other higher-speed circuits, N+ Fe N+ Fe N+ N+.I. Without C cb reduction max = 51 GHz With Pedestal M. Urteaga, K. Shinohara, R. Pierson, P. Rowell, B. Brar, Z. Griith, N. Parthasarathy, M. Rodwell " InP DHBT IC Technology with Implanted Collector-Pedestal and Electroplated Device Contacts", submitted to IEEE CSIC Symposium max = 61.2 GHz (measured) max ~ 1 GHz (simulated) P divider core, 31 mw (includes emitter ollower buers) Low-Power IC Design: Z. Griith, N. Parthasarathy, M. Rodwell, M. Urteaga, K. Shinohara, P. Rowell, R. Pierson, and B. Brar "An Ultra Low-Power ( 13.6 mw/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology", 26 IEEE IMS Symposium

expect ~225 GHz digital clock rate, 3-4 GHz ampliiers 125 nm devices are the next target.

53 Frequency Limits o Bipolar Integrated Circuits 5 nm generation: Done ~475 GHz t & max 15 GHz static dividers (digital ICs) 25 nm results coming very soon. expect ~225 GHz digital clock rate, 3-4 GHz ampliiers 125 nm devices are the next target. 3 GHz digital clock rate, 6 GHz ampliiers THz transistors will come The approach is scaling. The limits are contact & thermal resistance serious challenge: volume applications to support development

Frequency Limits of Bipolar Integrated Circuits

IEEE MTT-S Symposium, June 13, 2006 Frequency Limits of Bipolar Integrated Circuits Mark Rodwell University of California, Santa Barbara Collaborators Z. Griffith, E. Lind, V. Paidi, N. Parthasarathy,