A Self-Adaptive DC/DC Buck Converter Control Modulation Design

Transcription

1 Journal of Electrical and Electronic Engineering 05; 3(4): 87-9 Published online July 3, 05 ( doi: 0.648/j.jeee SSN: (Print); SSN: (Online) A Self-Adaptive DC/DC Buck Converter Control Modulation Design Pengcheng Xu, Zhigang Han Department of Electronic Science and echnology, ongji University, Shanghai, China address: 3xpc@tongji.edu.cn (Pengcheng Xu), hanzhg@tongji.edu.cn (Zhigang Han) o cite this article: Pengcheng Xu, Zhigang Han. A Self-Adaptive DC/DC Buck Converter Control Modulation Design. Journal of Electrical and Electronic Engineering. ol. 3, No. 4, 05, pp doi: 0.648/j.jeee Abstract: DC/DC converter is widely used in many electronic application power supplies. Usually, in the previously DC/DC converter control modulation, the duty cycle can be changed according the feedback signal in pulse width modulation (PWM) or the frequency be changed with a constant time or time in pulse frequency modulation (PFM). A self-adaptive DC/DC converter control modulation is proposed in this paper. Based on the puts of two uniform operational transconductance amplifiers which are influenced by the feedback voltage, both of the pulse time and pulse time will be changed simultaneously. A self-adaptive frequency can be achieved in this control modulation. t can get a same put voltage ripple with a lower control frequency. Keywords: DC/DC, ime, ime, Frequency. ntroduction n a previously typical DC/DC converter with pulse frequency regulation (PFM) [], usually, the time of the pulse can be changed with a constant time or the time of the pulse can be changed with a constant time. n the other widely used control modulation, pulse width regulation (PWM) [], the duty cycle will be changed with a constant frequency. PWM control modulation has lower conversion efficiency in light load, while the PFM control modulation has lower conversion efficiency in high load. For a wide range high efficiency DC/DC converter, from light load to high load, dual-mode converter is been proposed previously. But there is no doubt that it increases the design complication [3-6]. A self-adaptive DC/DC converter regulation is proposed with a simple control mode. he feedback voltage from put will be used to adjust the time and time of the pulse simultaneously. he simulation result shows that this control regulation can get a same voltage ripple with a lower control frequency under the same conditional. And also the self-adaptive frequency achieves the wide range high efficiency. Because lower switching frequency reduces switching losses. As depicted in Fig.0, it is schematic of synchronous buck converter with self-adaptive control modulation. More and more DC/DC converter uses synchronous rectifier for its irreplaceable advantages, like fast transient response and high power density [7]. According the varying feedback voltage from put, both drive voltage pulse frequency and width will be changed. n other words, both time and time of the driving pulse can be adjusted accordingly. his proposed modulation is different from PWM which has a constant frequency and only can adjust pulse width, or PFM which has a constant time or time and only can adjust time or time respectively. C f c dc Fig.. Schematic of self-adaptive control modulation buck DC-DC converter with synchronous rectifier. ref in PN FB

2 88 Pengcheng Xu and Zhigang Han: A Self-Adaptive DC/DC Buck Converter Control Modulation Design. Self-Adaptive Modulation.. Modulation Process By the voltage sampling circuit with divided resistors, a feedback voltage can be generated according the varying put voltage and transfer into the chip. he operational transconduction amplify (OA) can identify and amplify the difference between and reference voltage ref, As depicted in Fig.0 self-adaptive modulation schematic. wo identical OAs are used in the schematic. he noninverting input of one of OAs is, while the other one OA s inverting input is. he put of OAs will be across on resistors and through voltage followers and adjust the current. As a result, the two identical OAs will generate two completely opposite put signals to control the charging and discharging current accordingly. wo completely opposite puts of OAs will convert into relevant current which charge or discharge the capacitor C respectively. F he range of voltage of C F is restrained between reference voltages high and low. Combining with logic circuit, with opposite changing currents can adjust both on and off of pulse. high S Q pulse low charge discharge pulse ref OA _ charge OA _ feedback feedback discharge ref C F Fig.. Schematic for specifying time and of driving pulse... Quantitative Analysis As depicted in Fig.0, the voltage followers can keep the voltages OA _ and OA _ across on the resistors and respectively. he charge current of CF is, charge And the discharge current of discharge OA _ () CF is, OA _ () As depicted in the Fig.0, the voltage across capacitor C F rises and falls between high and low. he switching PMOS and NMOS be turned on or turned off respectively in accordance with put voltage pulse of Set-eset atch. n addition, the put voltage pulse of Set- eset atch can control the switch of charge or discharge of capacitorc F. Consequently, both and will change based on varying. (3) high low CF OA _ f (4) high low CF OA _ + As depicted in Fig.03, the waveform of time and time changing. A negative feedback for stabilizing put voltage can be achieved by adjusting the time and time of the driving pulse at the same time. (5)

3 Journal of Electrical and Electronic Engineering 05; 3(4): _ old _ old _ old _ old _ new _ new _ new _ new a when. ref > b. when < ref Fig. 3. Waveform of time and time changing according feedback voltage. Negative feedback control process as described following: > ref > > OA _ and _ OA > and > ; < ref > > OA _ and _ OA > and >. i( n) i( n ) + Srise t S fall ( t t ) S rise in t S fall t drive Under the affection of filter capacitor, the put voltage can be given as, ( n) n t t 0 ( n) n 0 C i fiter ( t) dt (6) Fig. 4. Waveform of inductor current and self-adaptive driving pulse. As depicted in Fig.04, the wave shape of drive has a varying time and time. From the vertex of to the bottom of, the duty cycle is larger and larger until reaching to the minimum value, vice versa. During each driving period, When 0 < t < t, When t t, i i + S t ( n) ( n ) rise 3. Operational ransconductance Amplify he operational transconductance amplifier (OA) can be defined as an amplifier where all nodes are low impedance except the input and put nodes [8]. ow-impedance node always is connected to the source or gate-drain of MOS. As depicted in Fig.05, it is the schematic of operational transconductance amplifier with buffer. he resistive load is very large, almost Mohm. Otherwise, a resistive load will kill the gain of the OA. he OA used in the schematic with a cascode low-voltage (wide-swing) current mirrors structure for increasing the magnification ability [8-0]. he terminology : m indicates that N and N4 are sized m times wider than the N and N.

4 90 Pengcheng Xu and Zhigang Han: A Self-Adaptive DC/DC Buck Converter Control Modulation Design P As depicted in Fig.06, PMOS cascode current mirror makes sure that both sides flow the same current. N is m times than N for smaller gate-source voltage. One of the constraint conditions is given by cascodep P + (9) biasn gsn gsn ref OU ocasp gm element P N Based on typical MOSFE square-law equation, there is another constraint condition given by cascoden ocasn N 5 m : :m N N N3 N4 Fig. 5. Schematic of operational transconductance amplifier. he low-frequency voltage gain is given by A v v v P N m g ( ) mp ocasp ocasn Where the cascade resistors can be de given as And ( + g ) he 3-dB frequency is now f 3dB ocasp mp op op ( + g ). ocasp mn 5 on 5 on π ( ) C ocasn ocasp For biasing the operational transconductance amplifier and other schematic, a beta-multiplier reference (BM) is elaborately designed. he BM is supply independent biasing for two constraint conditions with DD specifying reference current [8]. (7) (8) gs d + ' W µ n Cox thn (0) Obviously, these two constraint condition equations don t include DD. Combining the two constraint conditions, the biasing current of the proposed design can be expressed in the following form, ref ( ) W µ C m ' n ox () A start-up circuit is added in the beta-multiplier reference for avoiding unwanted operating point that zero current flows in the circuit. f unfortunately, this unwanted state happens with the biasn closing to ground and closing to DD. When in this state, M SU is off and MSU turns on. A leaks current flows into N from. his causes the operating point converte into normal current point. After that, start-up circuit turns off and doesn t affect the beta-multiplier reference operation. 4. Current Mode Bandgap eference n voltage mode bandgap reference, for matching the coefficients between PA (Proportional to Absolute emperature) voltage and CA (Complementary to Absolute emperature) voltage, only a specified reference voltage, usually around., can be generated. However, based on current mode bandgap reference, it has a flexible reference voltage [5, ]. M SU PA CA Combine PA CA PA CA M SU 3 casn P casp M SU N casp PA CA biasn A B C ref N :m N 3 :n Q Q Fig. 6. Schematic of cascode beta-multiplier reference. Fig. 7. Schematic of current-mode bandgap reference.

5 Journal of Electrical and Electronic Engineering 05; 3(4): he two operational amplifiers, as depicted in Fig.07, forces nodes A, B and C to be at the same potential. he diode Q is n time than Q. he PA current can be described as Where PA BE k lnn () q drive 60m 3% BE BE BE n ln ln lnn 0 0 s s k lnn q he change in the PA current with temperature is (3) saw Fig. 8. Self-adaptive DC-DC converter simulation result. able. Specification of the proposed self-adaptive mode control. Description alue Unit PA k lnn q he CA current can be given as CA (4) BE, Q (5) he change in the CA current with temperature is CA BE (4 + m) Eg / q (6) he reference voltage is then the sum of the PA and CA current multiplied by resistor, ( + ) (7) ref PA CA For eliminating the resistor temperature effect, the resistors, and 3 are fabricated by same poly. From the Eq.8, the temperature behavior of the resistor can be fell from the reference voltage. 5. Simulations esult he proposed self-adaptive buck DC/DC converter driving chip is implemented in Foundry GmbH, Germany F50 CMOS process. t used Cadence irtuoso to simulate the schematic with 500n H and Cm F, with a 500mA 500KHZ load. As shown in Fig.08, the simulation result meets the analysis in Fig.04. Form the simulation result, it is obvious that the DC-DC operation in current continuous mode. But driving current is considerable large. Driving PMOS and NMOS should endure so much current. t is really a challenge to MOSFEs. More deliberate design should avoid it and over current protection is needed. 3 input voltage 8 put voltage load 500 ma ripple 60 m Min frequency 30 KHZ Max frequency 56 KHZ he proposed self-adaptive buck DC/DC converter modulation can change the time and time of the pulse simultaneously according the feedback signal. he frequency is not a constant value, but can be adaptive to the application condition. he simulation meets the design specification. A 300 m, A 7.7k P P / Fig. 9. Operational transconductance amplifier simulation result. As shown in Fig.09, with inverting input N 300m, the largest voltage gain occurs at noninverting input equal to inverting input.

6 9 Pengcheng Xu and Zhigang Han: A Self-Adaptive DC/DC Buck Converter Control Modulation Design bias biasn gsp DD.4, bais u comparative with simulation results. And also stability analysis and load transient analysis must be processed in the future before its expansion into commercial integrated circuits. Acknowledgment he author would like to acknowledge Prof. Dr.-ng. obert Weigel and M. Sc. Andreas Bänisch in Erlangen- Nurnberg University for supervising my semester project on CMOS DC-DC converter design, and the anonymous reviewers for their constructive comments. DD Fig. 0. Beta-multiplier bias simulation result. he supply independent characteristor can be shown in Fig.0. After the circuit operating in saturation region, DD >.4, biasing current will be constant value ua. he NMOS gate-source voltage is equal to being with biasn constant. Although proportional to power supply DD, the difference between DD and, namely the PMOS gate-source voltage, also is constant. PA CA sum ref / C 0.5m Fig.. Current-mode bandgap reference simulation result. As depicted in Fig., the PA current has a better linearity than CA current. he nonlinear should be compensated in the high precise application []. he summing up of PA and CA current is proportional to absolute temperature. his can be counteracted by poly resistors negative relation with temperature characteristic. 6. Conclusion he simulations results have demonstrated the feasibility to change both pule time and time on DC-DC converter with comparative low put ripple. t is normal that the final experimental implementation of the on-chip DC-DC converter will degrade some specifications eferences [] B. Sahu, G.A. incon-mora, A accurate, low-voltage,cmos switching power supply with adaptive on-time pulsefrequency modulation (PFM) control, EEE rans. Circuits and Systems, 54 () (007) 3-3. [] Pui-Sun ei, Chang,.C.-H. A high-efficiency PWM DC-DC buck converter with a novel DCM control under light-load, Circuits and Systems (SCAS), 0 EEE nternational Symposium on, pp [3] B. Arbetter,. Erickson, and D. Maksimovic, DC DC converter design for battery-operated systems, in Proc. EEE Power Electron. Specialist Conf., 995, pp [4] Wan-one iou,, Mei-ing Yeh, and Yueh ung Kuo, A High Efficiency Dual-Mode Buck Converter C For Portable Applications. EEE ANSACS POWE EECCS, O. 3, NO., MACH 008. [5] Biranchinath Sahu, Gabriel A. incón-mora, An Accurate, ow-oltage, CMOS Switching Power Supply With Adaptive On-ime Pulse-Frequency Modulation (PFM) Control, EEE ANSACS CCUS AND SYSEMS : EGUA PAPES, O. 54, NO., FEBUAY 007. [6] Abraham. Pressman, Keith Billings, aylor Morey. Switching Power Supply Design. hird Edition. McGraw-Hill Professional.009. [7] X. Zhou, M. Donati,. Amoroso, and F. C. ee, mproved ight-oad Efficiency for Synchronous ectifier oltage egulator Module, EEE ransactions on Power Electronics, ol. 5, NO.5, pp , September, 000. [8].JACOB BAKE. Circuit Design, ay, and Simulation, hird Edition [M]. United States of America, EEE Press, 00:6-8 [9] Phillip E. Allen, Douglas. Holberg, CMOS analog Circuit Design, nd ed. OXFOD UNESY PESS. 00. [0] Behzad azavi, Design of Analog CMOS ntegrated Circuits, McGraw-Hill, nc. New York, NY, USA. 00. [] Charalambos M. Andreou, Savvas Koudounas, and Julius Georgiou, A Novel Wide-emperature-ange, 3.9 ppm/ C CMOS Bandgap eference Circuit [J]. EEE JOUNA OF SOD-SAE CCUS, O. 47, NO., FEBUAY 0: