Final Examination Copyright reserved. Finale Eksamen Kopiereg voorbehou. Analogue Electronics ENE June 2007

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1 Departement Elektriese, Elektroniese en Rekenaar-Ingenieurswese Department of Electrical, Electronic and Computer Engineering Finale Eksamen Kopiereg voorbehou Analoogelektronika ENE Junie 2007 Toetsinligting: Test information: Maksimum punte: Maximum marks: 100 Duur van vraestel: 180 minute Duration of paper: 180 minutes Final Examination Copyright reserved Analogue Electronics ENE June 2007 Volpunte: Full marks: 100 Oopboek / toeboek: Oop (Enige materiaal) Open / closed book: Open (Any material) Eksamineringsbeplanning: n Addisionele 10 minute sal aan die begin van die eksaminering beskikbaar gestel word. Gedurende hierdie tydperk mag kandidate nie op die antwoordstelle skryf nie. Test planning: An additional 10 minutes will be allowed the start of the test. During this period, candidates may not make any markings on the answer scripts. G e e n t o e s t e l m e t n kommunikasiepoort (van enige aard) word toegelaat nie. Any device with a communication port (of whatsoever kind) may not be used. Totale aantal bladsye (hierdie blad ingesluit): Total number of pages (including this page): Die eksamenregulasies van die Universiteit van Pretoria geld. The test & examination regulations of the University of Pretoria apply. BELANGRIK- IMPORTANT 2. Vrae moet in onuitwisbare ink beantwoord word. Geen antwoorde wat in potlood geskryf is sal gemerk word nie. Questions must be answered in indelible ink. Answers in pencil will not be marked. 3. Beantwoord al die vrae en skryf u antwoorde in u Antwoordboek neer. Geen vrae mag op die vraestel beantwoord word nie. Answer all the questions and write the answers in the supplied Answer Book. No questions are to be answered on the Question Paper. 4. Toon alle berekeninge waar van toepassing. Geen punte sal toegeken word vir korrekte antwoorde sonder berekeninge om dit te staaf nie. Show all calculations where applicable. No marks will be given for correct answers without calculations/reasoning to support them. 5. Gebruik duidelik geregverdigde & kundige Ingenieursbenaderings (en/of aannames) waar/indien van toepassing. Use clearly justified & educated Engineering approximations (and/or stated assumptions) where/as appropriate. 6. Datavelle: Vir karakteristieke waar beide tipiese, maksimum en (moontlik) minimum waardes gespesifiseer word, gebruik die minimum waardes. (tensy anders in vraag gespesifiseer) Datasheets: For characteristics where the typical, maximum and (possibly) minimum values are specified, make use of the minimum value (unless/otherwise specified in the question). Interne Eksaminator en Evalueerder I: Internal Examiner & Evaluator I: Eksterne Eksaminator: External examiners: Vertaler (Engels Afrikaans): Translator (English Afrikaans): Beoordeelaar II Evaluator II Saurabh Sinha ( ssinha@ieee.org) Johan Schoeman ( johan.schoeman@eng.up.ac.za) Prof. M. du Plessis ( monuko.du.plessis@eng.up.ac.za) Tjaart Opperman ( tjara@tuks.co.za)

2 Study theme and Study units 1. Introduction to amplifier circuits SU1 Signals SU2 Basic amplifiers 2. Bipolar transistor amplifiers SU3 Bipolar transistor amplifiers & small signal analysis SU4 Graphical analysis and biasing SU5 Basic single stage BJT amplifier configurations 3. Field effect transistor amplifiers SU6 MOSFET transistor amplifier SU7 MOS circuit biasing and basic configurations 4. Differential and multistage amplifiers SU8 BJT and MOSFET differential amplifiers (DAs) 5. Amplifier frequency response SU9 Frequency terminology and Bode plots SU10 Transistor frequency response SU11 s-domain analysis and amplifier transfer functions SU12 Low- and high-frequency responses of the CS and CE amplifiers SU13 Cascode configurations and frequency responses 6. Feedback SU14 Feedback structure and basic feedback topologies SU15 Feedback topology analysis SU16 Loop gain, loop stability, and frequency compensation 7. Output stages and power amplifiers SU17 Output stages SU18 Power transistors and variations on the class AB configurations Questions Notional hours % Contribution 1, 2, 3 & & & Total credits 100 Page 1

3 Question 1 [32] In this problem, it is aimed to design a multi-stage amplifier: V DD r in r out R S A 1 A 2 VCC_CIRCLE v o v s R L V SS S P E C I F I C A T I O N S The following is known/given: A dual supply is available: V DD = 10 V and V SS = 0 V. The source resistance, R S = 5 kω, and the load resistance, R L = 1 kω. A Q2N7000 is used as the MOSFET, and J2N5457 as the JFET. Spice models attached. Only standard 5 % resistors, and standard capacitors are available (specification sheets attached). R B > 0. The circuit schematic to be used is as below. The following is required: a mid-band gain of A v = v o /v s = 20 V/V, an input impedance, r in of about 5 kω, an output impedance, r out of about 430 Ω, and a low frequency cut-off of 100 Hz. VCC_BAR V DD r in r out R 1 R D R S1 J 2 v s C IN M 1 VCC_CIRCLE v o R B C OUT R L R 2 R S2 C B R S3 VCC_BAR V SS 1.1 [20] Complete the design by providing component values to achieve the above specifications. 1.2 [2] Determine the high-frequency pole, ω H for the circuit. 1.3 [5] Draw the Bode magnitude and phase plots. Include the effect of the zero contributed by C B. 1.4 [3] Propose the addition of a capacitor (also specify the component value) to limit the high-frequency response to 20 khz. Show this on the schematic (in the answer script). 1.5 [2] Determine the DC power consumption of the circuit. Page 2

4 Question 2 [7] Consider the simple filter. C 2 R 2 R 1 C 1 - v s R B + OUT VCC_CIRCLE v o Ideal Amplifier Assume: R 1 = 10 kω, R 2 = 100 kω and R 1 C 1 >> R 2 C [1] Sketch the Bode magnitude plot for the amplifier. 2.2 [1] Approximately derive the transfer function of the amplifier, T(jω), in terms of the passive circuit components. 2.3 [2] Sketch the phase plot for the amplifier. 2.4 [1] To accommodate for a non-ideal effect of input offset currents, determine the value of R B. 2.5 [2] The active filter should have a low-frequency cut-off of 100 Hz, and a high-frequency cut-off of 20 khz. Determine the standard values of capacitors, C 1 and C 2 (specification sheet attached). Page 3

5 Question 3 [21] This problem is a first step in an effort to design a feedback amplifier. The next question will fully implement the amplifier with transistors, and resistors. VCC_BAR V VCC_BAR V v s r in-fb R s r in C IN v + v - + v in OUT - A v-se v o1 Q 3 D 1 Q N Open-loop gain Network, A [ A-network ] C OUT VCC_CIRCLE v o D 2 r out R L Q P a R B a r out-fb r out-β + v f - R F1 R F2 r in-β Feedback network, β C IN/OUT The following is given / required: A source impedance, R S = 5 kω, and a load impedance, R L = 8 Ω. The impedances of the A-network, excluding the effects of loading: r in = r in-dm = 10 kω, and r out = 15 Ω. The amplifier is used as a voltage amplifier Closed loop feedback gain, A v-fb = v o /v s = 20 V/V Assume the differential amplifier gain is A v-se = v 01 /(v + -v - ) = 50 V/V. For this problem ONLY: Assume R B is set as 500 Ω; g m3 = 400 ms; R F1 = 19 kω and R F2 = 1 kω. A single supply of 18 V is available. 3.1 [1] Identify the feedback topology (i.e. series/series, shunt/shunt, series/shunt, or shunt/series?) 3.2 [2] Estimate the open loop gain (considering the type of feedback), A o. 3.3 [2] Determine the feedback factor, β. 3.4 [1] Determine the amount of feedback: 1 + A o β 3.5 [8] Determine the resistances: r in-β, r out-β, r in-fb, and r out-fb. 3.6 [1] Determine the closed loop gain (considering the type of feedback), A fb. 3.7 [2] Summarize the above results, using a unilateral model for the closed-loop amplifier. 3.8 Assuming (for this part of the problem) the open-loop gain network has a transfer function: 1000 A( jω) = 2 jω jω [3] Using a Bode plot, estimate the gain margin (GM) [1] Is frequency compensation necessary? Justify your answer. Page 4

6 Question 4 [36] The feedback amplifier shown earlier is implemented with matched transistors (Q 1 and Q 2 ) as shown below. VCC_BAR V R 1 R C1 R C2 Single-Ended (SE) Output v o1 R S C IN v + v - R F2 D 1 Q 1 Q 2 Q 3 Q N C OUT r out VCC_CIRCLE v o v s R 2 R T + v f - R F1 D 2 R B Q P R L r in Differential Amplifier (DA) Feedback Network, β Gain and Biasing Stage Power Amplifier (PA) The following is given/required: A source impedance, R S = 5 kω, and a load impedance, R L = 8 Ω. The impedances of the A-network, excluding the effects of loading: r in = r in-dm >1 kω, and r out < 50 Ω. The A-network consists of the DA, gain/biasing stage and the PA. The amplifier is used as a voltage amplifier Closed loop feedback gain, A v-fb = v o /v s = 20 V/V The differential gain of the DA, A v-se (single-ended output) should be at least 50 V/V. Assume R C1 = R C2. For this problem the following assumptions (of the previous question) may NOT be valid: Assume R B is set as 500 Ω; g m3 = 400 ms; R F1 = 19 kω and R F2 = 1 kω. The PA should deliver 2 W (average power). C IN/OUT ; Assume a diode voltage drop (V f ) of about 0.7 V. A single supply of 18 V is available. Datasheets are attached: Q 1-3 : Q2N3904, Q N : Q2N3055, and Q P : Q2N [25] Complete the design by providing component values to achieve the above specifications. Discuss circuit component changes that may be required for the biasing of Q [1] Approximate the output impedance, r out-se of the DA. 4.3 [2] Determine the CMRR of the DA. 4.4 [3] For a case where R C1 R C2, will the CMRR change? Please justify your answer. 4.5 [3] Determine the dc power dissipation for each transistor. 4.6 [2] Approximate the efficiency of the PA. Page 5

7 Question 5 [4] The PA of the previous problem utilizes two power transistors (Q N and Q P ). The MJE2955T (TO-220) pnp transistor (datasheet attached) is typically mounted on a heat-sink: Assume an electrical power, P elec = 10 W for this question. To improve mounting, one of the materials below can be used as a spacer. For this design it is proposed to use mica: Material Thermal Electrical Thermal Resistance Other Properties [ C/W ] mica Good Excellent ~ Fragile Kapton Good Excellent ~ Very robust aluminium oxide Excellent Fair ~ 0.4 Fragile - easily damaged beryllia Excellent Excellent ~ 0.25 Toxic Sil-Pads Fair + Excellent ~ Convenient Thermal Resistance of Various Mounting Methods (TO-220 Case) An appropriate heat sink is chosen (see datasheet attached). Assume an ambient/air temperature of 25 C. Using relevant datasheets determine the temperatures of the heat sink and the case. Page 6

8 MODIFIED SPICE MODEL FOR JFET 2N5457 *2N5457 MCE *25V 25mA 250 ohm Dep-Mode pkg:to-92 3,1,2.MODEL J2N5457 NJF(VTO=-1.8 BETA= LAMBDA=0.001 RD=35 RS= CGS=0 CGD=0 KF=6.5E-17 AF=0.5 ) MODIFIED SPICE MODEL FOR MOSFET 2N7000 *2N7000 MODEL *Units for TOX (t ox ): m and UO (μ o ): cm 2 /(V.s).MODEL 2N7000 NMOS (LEVEL=3 RS=0.205 NSUB=1.0E15 +DELTA=0.1 KAPPA= TPG=1 CGDO=0 +RD=0.239 VTO=1.000 VMAX=1.0E7 ETA= NFS=6.6E10 TOX=1.0E-7 LD=1.698E-9 UO= XJ=6.4666E-7 THETA=1.0E-5 CGSO=0 L=2.5E-6 +W=0.8E-2 ).ENDS *Hint: -12 F ε o = m ε ox 3.9ε o C ox = = tox tox W K n = μ oc ox = BETA L Page 7

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15 Application Board Level Dimensions = Heat Sink Product Offering Length Width Height Weight (0.60) (0.75) (1.50) (.044) (.044) (.044) (0.50) (0.50) (0.50) Thermal Resistance Natural Convection Thermal Resistance Forced Air C/W@3W 12 C/W@200 LFM C/W@3W 9 C/W@200 LFM C/W@2W 7 C/W@200 LFM Board Level (2.00) (1.38) 4.75 (0.19) C/W@3W 5.2 C/W@200 LFM (0.75) (0.52) 6.35 (0.25) 1.43 gm 62 C/W@2W 16 C/W@200 LFM Board Level (0.75) (0.52) 9.53 (0.38) 1.5 gm 56 C/W@2W 11.8 C/W@200 LFM (0.75) (0.52) (0.50) 1.59 gm 50 C/W@2W 8.8 C/W@200 LFM Board Level (0.70) (1.75) 9.53 (0.38) 2.36 gm 70 C/W@4W 6.0 C/W@400 LFM CHOSEN (0.75) (0.75) 9.52 (0.37) 1.72 gm 49 C/W@2W 9 C/W@200 LFM Assume a fan is deployed Θ sink-air = 5 ºC/W Board Level (1.61) (2.01) (0.73) C/W@6W 6 C/W@200 LFM To convert from LMF (linear feet per minute), you need to multiply the LFM number by the cross sectional area of the fan (in square feet). Page 14

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