Electrostatic Discharge (ESD) Protection for RF Applications

Transcription

1 Electrostatic Discharge (ESD) Protection for RF Applications Juin J. Liou Professor, University of Central Florida, USA Cao Guang-Biao Endowed Professor Zhejiang University, China

2 In Collaboration with: Intel Corporation, Sacramento, CA, USA (ESD for 10-GHz optical transceiver) Intersil Corporation, Palm Bay, FL, USA (ESD for PC port data communication transceiver) Semiconductor Research Corp., NC, USA (ESD compact modeling) Fairchild Semiconductor, Portland, ME, USA (ESD for automobile data communication transceiver) National Institute of Standards and Technology, Washington DC, USA (ESD for gas sensor chip) Analog Devices Inc., Boston, MA, USA (ESD failure criteria and safe operation) National Semiconductor Corp., CA, USA (ESD for power regulator array) Qualcomm Inc., San Diego, CA, USA (ESD for RF IC s) Huahong-NEC, Shanghai, China (ESD for smartcard chip) ESD Design Center, Zhejiang University, China (ESD research and education)

3 Outline Overview (Charge Generation, Damaging Mechanisms, ESD Models, and Protection Schemes) ESD Optimization and Design for RF Functionality Integrity (Minimize Parasitic Capacitance) ESD Modeling (MOSFET and SCR)

4 On-chip ESD protection is a very high priority! Global Semiconductor Revenue Of all the microchips manufactured, about 1-2% will fail within the first year due to the improper handling of microchips at the fab, shipping, or user site. Of all the failed microchips, about 33% is caused by the ESD, resulting in a loss of several hundred million dollars to the industry every year

5 Challenges of ESD The increasingly stringent requirement for effective and robust on-chip ESD protection is often a main roadblock in pushing the microchips to the market. Challenges of realization of ESD protection include: Several different ESD events can take place, and different IC s impose different ESD requirements no universal ESD solution existed and customization needed Design of ESD protection involves with the issues of chip size, protection level, trigger voltage, holding voltage, leakage current, latchup, and current conduction capability design complexity and know-how demanding For RF ESD, parasitic associated with ESD devices needs to be minimized to maintain the RF integrity trade-off between ESD protection and RF performance Technology computer-aided design (TCAD) simulation of ESD is difficult because of the presence of snapback behavior in this device good understanding of simulation tools and device physics required Continue scaling makes the devices more susceptible to ESD stress difficult to implement ESD solutions using the modern and future silicon technology

6 A Phenomenon of Electrostatic Discharge Ouch!~~~ The threshold voltage for a person feeling a discharge is ~ 3,500 V ESD is a process in which charge is transferred from one object to the other

7 Examples of ESD on Microchips

8 Charge Generation (1) This process requires the physical contact between two different materials. During the contact, an exchange of free electrons takes place due to the different materials work functions. Amount of charge generated depends on the contact area, pressure and friction. Triboelectrification process Examples are walking on the carpet, driving cars in dry air.

9 Electrostatic Charge Generated on Human Body Source < 25% RH 65-90% RH Walking across carpet 35,000 V 1,500 V Walking across vinyl tile 12,000 V 250 V Worker at bench 6,000 V 100 V Poly bag picking up from 20,000 V 1,200 V bench Chair w/ urethane foam 18,000 V 1,500 V V = Q/C, so for a small capacitance, the voltage can be very high even if the amount of charge is small. The danger of ESD is everywhere!

10 Charge Generation (2) Object B comes into close proximity with a charged object A. Part of electric field from A terminates on B, resulting in an internal separation of charge When A is removed from the area, a net charge exists in B with a polarity opposite from what existed on A. Inductive process Example is IC handling around a computer monitor.

11 Charge Generation (3) This process involves the physical contact and balancing of voltage between two objects at different potentials. During the time of contact, charge is transferred from the higher potential object to the lower potential object. When the objects are separated, each object will carry a charge with the same polarity. Conductive process Example is automated testing of IC parts.

12 MODELS ESD Models Parameters Time rise (nsec) Time decay (nsec) V peak (V) Standard wave form load HBM < ~ Short/ 500Ω ± ± MM 6 ~ (Ring period) CDM < 0.2 ~ ~2 250 ~2000 IEC 0.7 ~1 ~ ~ ± ± ± 100 ~400 Short/ 500Ω Cu discs 4/30pF Air gap Discharge/ 50MΩ-100MΩ HBM: Human Body Model MM: Machine Model CDM: Charge Device Model IEC: International Electrotechnical Commission The severeness of ESD is determined by the current, not the voltage, generated

13 R L V esd = DC HV supply Simplified Equivalent Circuits and Parasitic Elements C esd R esd S1 L esd DUT Chip Scheme PAD 1 PAD 2 ESD Parasitic Components MODELS C esd (pf) R esd (Ω) L esd (μh) HBM MM 200 CDM 6.8 Few tens of Ω in the discharge path Few tens of Ω in the discharge path 1-2, in the discharge path 1-2, in the discharge path IEC

14 On-Chip ESD Protection Structures Single path at I/O (i.e., ggmos) with one-directional supply clamp Dual path at I/O (i.e., diode, SCR) with one-directional supply clamp Dual path at I/O (i.e., diode, SCR) with bi-directional supply clamp V DD ND PD I/O PS NS V SS The ESD structure is turned on to create a loop to bypass the current associated with ESD during the ESD event The ESD protection structure is turned off and does not interfere with the normal operation when the ESD event is absent

15 Desirable I-V Characteristics of ESD Device Requirements: It2 1) Low leakage current (low standby power consumption) 2) High It2 (ESD robustness). It2 depends on the holding voltage as well as the type of device I t2 is normally in ma/um (um is the device width). A device with very high I t2 means that it is less likely to fail even if the device size is small For example, a device with an I t2 of 10 ma/um means that it requires a width of 100 um in order to sustain an HBM of about 1,500 V 3) Adjustable trigger voltage (to control the turn-on of ESD device) 4) Adjustable holding voltage (to prevent ESD latch-up) 5) ESD device itself cannot be damaged 6) Parasitics associated with ESD devices should be minimal so that the circuit functionality is not degraded (difficult for RF applications)

16 Issue of Trigger Voltage I V DD V SS I/O Pad Core Circuit Supply Clamp V DD V V(-) I I/O ESD Protection Upper bound to prevent core damage Lower bound to prevent turn-on during normal operation V(+) V V SS Both the supply clamp and I/O ESD protection device must not turned on during the normal operation and must be turned on when subject to ESD stress

17 Issue of Holding Voltage and Latchup Vdd to Vss is 5 to 0 V V DD SC-1 SC-2 I TLP (A) I/O Pad Core Circuit Supply Clamp I/O ESD Protection V SS Latchup is a condition where the ESD device cannot be switched off after triggered Latchup occurs when 1) voltage across the ESD device is larger than the device s holding voltage and 2) a sustainable current source is available Latchup is not likely at I/O pad because of limited current supply Latchup is a major issue for supply clamp Lower bound to prevent latch up upper bound to increase It2 V TLP (V)

18 Trigger voltage, Holding Voltage, On-State Resistance, and Latchup Trigger voltage must be larger than the normal operating voltage, but it cannot be too large to cause IC damages In general, holding voltage needs to be small to reduce the power dissipation in the ESD device (power = current x voltage). But to prevent latchup, holding voltage should not be smaller than the normal operating voltage Latchup is a condition where the ESD device is still turned on by the driving current for a long period of time after the passing of ESD event. If the holding current is larger than the current available at the pad, or if the current available at the pad is limited, then no latchup will occur even if the holding voltage is less than the normal operating voltage at the pad. For the supply clamp, the available current is very large (power supply), so the holding voltage of supply clamp must be larger than the Vdd- Vss to prevent latchup in the supply clamp. On-state resistance should be minimize to ensure the ESD device can sustain a very high current capability and to prevent thermal breakdown.

19 Typical ESD Protection Devices I/O I/O R g I/O P+ Cathode R g N well P well N-LVTSCR R g N+ Anode SCR ggnmos Chain of diodes SCR: ggnmos/pmos: Diodes: Robust, but difficult to scale for different ESD requirements Simple structure, but gate oxide can be damaged by high voltage Most widely used I/O protections. Simple structure, but high leakage current, very small trigger voltage, no snapback, and large area

20 Conventional SCR P+ N-well P-sub N+ The emitter-collector avalanche breakdown in the PNP BJT controls the trigger mechanism, the NPN BJT controls the on-state conduction, and the base region of the PNP and NPN determines the current gain and thus the holding voltage.

21 Characteristics of SCR, ggmos, and Diode The diode does not have snapback (trigger voltage is the same as holding voltage). The trigger voltage of a regular diode is 0.7 V and of a Zener diode (under reverse bias) is much higher. But Zener diode requires a large size to prevent current-induced damage due to the large holding voltage. I Trigger and holding voltages of the ggmos depend on the substrate doping density and channel length, which are often limited by the processing technology. SCR can possess a much higher It2 than ggmos and diode. In a recent project, we have designed an SCR with an It2 10 times larger than that of a ggmos having the same area. This implies that, for the same ESD protection level, an SCR can do the job with a much smaller size. V SCR-type characteristic GGMOS-type characteristic Diode-type characteristic (R) Diode-type characteristic (F)

22 Current Discharge Path in a Typical ESD Protection Scheme Case: positive ESD pulse at one I/O and the other I/O grounded Preferred discharging path involves two diodes and one supply clamp The supply clamp provides a small I/O and near constant voltage across the two supply rails Without the supply clamp, one or more diodes will be operating in the breakdown region large-size diodes required Pros: Simple Cons: 1) Only suitable for very low trigger voltage and holding voltage applications 2) Cannot be used for high-level ESD protection unless the area of the diodes is large large chip area consumption and large parasitic capacitance D1 D2 V DD Core Circuit Vdd V SS Control Node Vss C R Current I/O Supply Clamp

23 Another Typical ESD Protection Scheme Turn on when pad subjecting to negative ESD Turn on when pad subjecting to positive ESD Pros: MOS devices Cons: 1) Under the normal operation, voltage drop between the gate and drain cannot be too large 2) Cannot be used for high-level ESD protection because of the limited It2 3) The MOSFET can inadvertently turn on as a diode (i.e., n-channel MOSFET can turn on when the pad is subject to a negative ESD)

24 Outline Overview (Charge Generation, Damaging Mechanisms, ESD Models, and Protection Schemes) ESD Optimization and Design for RF Functionality Integrity (Minimize Parasitic Capacitance) ESD Modeling (MOSFET and SCR)

25 Main challenge for designing ESD protection structure for RF applications All active components in the ESD protection structure (i.e., MOSFET and diodes) must have a relatively large area to withstand the large power dissipation associated with the ESD stress The large device size leads to a large parasitic capacitance and thus a degradation in the RF performance of the core circuit being protected How to design a robust ESD protection structure with a minimal parasitic capacitance?

26 RF performance including the ESD parasitic LNA circuit (P1-P4 are SCR-based ESD devices) K. Higashi et al., 2002 IEEE Radio Freq. IC Symp., p. 285

27 RF performance including the ESD parasitic 2.4 GHz LNA circuit for Bluetooth A. Z. Wang et al., 2002 IEEE Custom Integrated Circuit Conf., p. 411

28 Case study 1. Design and optimization of diodes for minimum parasitic capacitance 2. Design and optimization of supply clamp for minimum voltage drop Floating Rail #1 Supply Clamp Input Output Supply Clamp Floating Rail #2 V- Circuit Core V+ Supply Clamp Input I/O Supply Clamp

29 Key design considerations Parasitic capacitance associated with the supply clamp is not of major concern => A relatively large-size MOSFET can be used in the supply clamp to withstand the power dissipation The sum of the voltage drops across the forward-path diode D1 and supply clamp cannot exceed the breakdown voltage of the reverse-path diode D2 For a fixed technology (e.g., 0.13-μm CMOS), the diode breakdown voltage is fixed => Only the diode area can be optimized to satisfy the requirement of heat dissipation (power rating) One can also design the supply clamp to achieve a smaller voltage drop => Voltage drop across D1 can be increased => Area of D1 can be further reduced I/O D1 D2 V DD Core Circuit V SS Current I/O Supply Clamp ESD protection structure must be fabricated at the same time and use the same technology as the core circuit

30 MOS structure from an existing 0.13-μm CMOS technology Concentration(cm -3 ) SIMS Profile In+B Atlas ATLAS P Depth (μm) Threshold adjust implant + retrograde The doping and junction depth are fixed breakdown voltage is 9.3 V. Only the channel width can be varied and optimized. Substrate and drain terminals are anode and cathode, respectively.

31 Diode design criteria The reverse breakdown voltage must be larger than the sum of the voltage drops across the forward-biased diode and supply clamp (Breakdown voltage requirement) Positive Supply Rail Supply Clamp Input V+ Circuit Core Supply Clamp Input The temperature in the diode must be below a critical temperature C crit (Power rating requirement) Output Supply Clamp Negative Supply Rail V- I/O Supply Clamp

32 Determination of critical temperature The critical temperature is defined as the temperature for which the intrinsic free-carrier density n i is equal to the doping density near the hot spot From the simulation results, the hot spot is found near the surface of N-well and the doping density is N D Simulated for an arbitrary bias condition

33 n i = N D = n io T ( T crit o ) 3/ 2 Eg exp( 2kT crit E go 2kT o ) E g = T T crit crit 2 Here, T o = 300K is the ambient temperature, n i0 is n i at ambient temperature, and k is the Boltzmann constant.

34 Optimization of diode based on power rating requirement Temperature (K) T cric =860K Diode with DNW V HBM =1KV Width=10μm Width=20μm Width=30μm Time (ns) The doping density near the hot spot is about cm -3. Based on the above-mentioned method, Critical temperature is 860 K Then device simulations using Atlas (by Silvaco) are carried out, and, for a given ESD stress (1 kv of HBM), the temperatures near the hot spot (drain junction) in diodes having different widths are obtained.

35 Optimization of diode based on breakdown voltage requirement Voltage drops in the diode and supply clamp are also simulated. Note that V D is the voltage drop across the forward-path diode D1 and is a function of the diode dimension The minimal channel width satisfying both the power rating and breakdown voltage requirements is 30 μm

36 Experimental verifications ESD protection structure was constructed using two back-to-back diodes (with a width of 30 μm) and a clamp circuit with an NMOS (with a width of 160 μm), all fabricated from the 0.13-μm CMOS technology Current (A) V HBM =1KV Diode with DNW (Width:30μm) Measurement Simulation (V D +V Clamp ) (V) Experiment Simulation V HBM =1KV Diode with DNW Width=20μm Width=30μm Width=40μm Time (ns) Time (ns) No damage incurred in the diodes and MOSFET in the supply clamp. The 20- μm width diode was also used but damaged during the test, due to the fact that the reverse diode operated in the breakdown region

37 Parasitic capacitance of the optimized ESD protection structure Capacitance (ff) Diode with DNW (W:30μm) Diode without DNW (W:40μm) V DD =2.5V V Pad =0.5V Frequency (GHz) Capacitance (ff) Freq=10 GHz V DD =2.5V & V Pad =0V V DD =2.5V & V Pad =0V V DD =2.5V & V Pad =1.0V V DD =2.5V & V Pad =1.0V Diode w/o DNW Diode w DNW Experiment Data w DNW V DD =2.5V & V Pad =0.0V V DD =2.5V & V Pad =1.0V HBM Voltage (KV) Single diode Forward and reverse diodes

38 Optimization of Supply Clamp for Minimal Voltage Drop V DD D1 Current I/O Core Circuit I/O Supply Clamp D2 ESD Power Supply Clamp V DD V SS V dd V dd C R Control Node C 1 R 1 C 2 R 2 V SS V ss V ss Conventional gate-couple (GC) SC Novel gate-couple substrate-trigger (GCST) SC

39 An NMOS Transistor with Parasitic Bipolar Action V G V S V D N+ N+ I B Impact Ionization Electrons Injected When Junction Is Forward Biased I C Depletion Boundary I SUB A faster snapback (smaller trigger voltage) is desired, which can be achieved by triggering the substrate V B

40 Snapback characteristics for different substrate voltages Max HBM protection (max charging voltage applied to supply clamp without damaging MOSFET) vs. MOS width Drain Current (A) 10 2 Experiment at Vg=0V 10 1 Vsub=0.0V Vsub=0.3V 10 0 Vsub=0.6V Simulation at Vg=0V Vsub=0.0V Vsub=0.3V Vsub=0.6V Drain Voltage (V) Maximum HBM Volatge (V) Gate-Coupling Gate-Coupling-Substrate-Trigger Width (μm) GCST supply clamp gives rise to a more robust ESD protection than GC supply clamp

41 Total voltage drop for different diode widths Breakdown voltage requirement 10 8 V br =9.3V ESD structure with GC SC (V D +V Clamp ) (V) 6 4 V HBM =1KV Diode with DNW 2 Width=8.75μm Width=10.0μm Width=20.0μm Time (ns) ESD structure with GCST SC

42 Reason for the reduced diode width Power rating requirement 8 V ref1 =7.668V T cric =860K Drain Voltage (V) V ref2 =6.23V Temperature (K) Diode with DNW V HBM =1KV Width=8.75μm Width=10μm Width=20μm 0 With Substrate Trigger Without Substrate Trigger Time (ns) Time (ns) Voltage drop on the supply clamp is reduced when using the substrate triggering A diode width of 10 μm can be used for GCST supply clamp, rather than 30 μm for GC supply clamp

43 Parasitic Capacitance of GC and GCST Structures Capacitance (ff) V DD =2.5V & V pad =0.0V V DD =2.5V & V pad =1.0V GC Structure GCST Structure HBM Voltage (KV)

44 Effect of Junction Perimeter on Capacitance diode with W and L varying 1.20E E E-09 Capacitance(F) 1.00E E E E E-10 diode_w8l0.5 diode_w4l1 diode_w2l2 Capacitance(F) 8.00E E E E-10 diode_w8l0.5 diode_w2l1f2 0.00E E Anode voltage(v) Anode voltage(v) Under the same area, the larger the perimeter the larger the capacitance. The use of multifinger can also increase It2, but at the expense of larger chip area

45 Parasitic C for various ESD devices 0.35 μm technology, 5 KV ESD charging voltage A. Z. Wang et al., 2003 IEEE Int. Symposium on Electron Devices for Microwave and Photoelectronics Applications

46 ESD Protection Using LC Coupling The LC coupling circuit is designed to resonant with an infinite impedance at the operating frequency, thus disconnecting the ESD protecting diode from the RF circuit under the normal operation. When the ESD is present, the LC link is short and the ESD protection circuit becomes functional.

47 ESD Protection Using LC Coupling The idea is good, and the results show improved S 21 when the LC link is used. But the main disadvantage is that the spiral inductor occupies a very large chip area! Also the metal line of the inductor may burnout by the large current associated with the high ESD stress

48 Advanced Dual-Polarity SCR Device for Low Voltage Application (i.e. RF) Device Name D1 D2 D3 D4 D5 D6 N_MLSCR_ N_MLSCR_ N_MLSCR_ N_MLSCR_ The triggering is controlled by the punch-through in P-Well between N+ and N+ regions, which can lead to a large leakage current (several μa)

49 4 3 N_MLSCR_01_50um(F) N_MLSCR_02_50um(F) N_MLSCR_03_50um(F) N_MLSCR_04_50um(F) Device Name D1 D2 D3 D4 D5 D6 Current(A) V N_MLSCR_ N_MLSCR_ N_MLSCR_ N_MLSCR_ Voltage(v) Trigger voltage can be adjusted by changing D6 and can be reduced to 6.5 V On-state resistance can be reduced by reducing D2 and D3 The main drawback is leakage current is on the order of μa

50 NLDD/P-Well/PLDD is the main blocking junction. Note that PLDD doping is higher than P-Well doping, so increasing Lp should reduce trigger voltage. But doing so will also decrease the base resistance of the n/p/n BJT and reduce the holding voltage. Advanced SCR Device for Low Voltage Application (i.e., RF) In this device, the lengths of NLDD and PLDD (Ln and Lp) are varied to produce small trigger voltages.

51 1. MDTSCR-T1 Ln=0.0 Lp= MDTSCR-T2 Ln=0.3 Lp= MDTSCR-T3 Ln=0.5 Lp= MDTSCR-T4 Ln=0.8 Lp= Current (A) Current (A) Voltage (V) Trigger voltage can be adjusted by changing Ln and Lp and can be reduced to 7.0 V Holding voltage can be adjusted by changing D1. It is also a function of Ln and Lp. Leakage current is on the order of A. -7 Voltage (v) Cell Name L x (µm) L n (µm) L p (µm) V T (v) I T (ma) V H (v) I H (ma) DTSCR-T DTSCR-T DTSCR-T DTSCR-T Good candidate for low-trigger, high holding applications

52 SCR Device with External Trigger Circuitry for Low Voltage Application SCR Either G1 or G2 can be used to make the SCR to trigger at a lower trigger voltage The concept is that G1 can be triggered before the SCR and, once it is triggered, the current flows through Rg1 will trigger NPN BJT and the SCR. If G2 is used, then G2 can be triggered at a small voltage, which then triggers PNP BJT and the SCR Generic schematic showing SCR with external triggering circuitry for low-trigger applications This scheme can further reduce the trigger voltage to the range of 5 to 8 V. The lowest trigger voltage of SCR without external trigger is about 8 to 9 V.

53 SCR Device with External Trigger Circuitry for Low Voltage Application Diode-string trigger SCR RC-MOS trigger SCR TLP data of RC- MOS trigger SCR

54 Diode Design for Low Voltage Application Use of diode string (several diodes in series) can provide low trigger voltage. Currents in the P+ and n+ increase toward the pads, resulting in current crowding and hot spots in these regions. This in turn will reduce the thermal breakdown current and ESD robustness of the diode. Need to make the current density more uniform in the diode!

55 Diode Design for Low Voltage Application Improved Traditional Traditional Metal Layout Tapered Metal Layout Under the same areas, the improved structure possesses a higher thermal breakdown current. For the same ESD protection levels, this leads to a smaller area required and thus a smaller capacitance.

56 Comparison of It2 of Diodes (0.6 BiCMOS Process) P+/N well W=10um W=20um W=30um It2 1.1 A 1.58 A 1.69 A It2 increases with increasing area, but not linearly P+/N well W=10um W=20um W=30um It A 1.64 A 1.61 A Using tapered metal layout increases It2, but only if W is less than 30 um PpNw_diode_w10 (1 finger) PpNw_diode_w10_m (1 finger/ tapered) PpNw_diode_w10_f2 (2 finger) PpNw_diode_w10_m_f2 (2 finger/tapered) It2 1.1 A 1.17 A 1.65 A 1.56 A Single/two fingers PpNw_diode_w10 (P+/N-Well) NpPw_diode_w10 (N+/P-well) It2 1.1 A A P+/N-Well vs. N+/P-Well

57 Effect of STI region on It2 Diode without STI under gate Diode with STI under gate CMOS Process 0.25 um 0.18 um 0.13 um Junction depth 0.22 um 0.2 um 0.18 um STI depth 0.3 um 0.28 um 0.26 um It2 (without STI) 35 ma/um 30 ma/um 26 ma/um It2 (with STI) 46 ma/um 43 ma/um 39 ma/um STI can minimize the flow of surface current and increase the robustness of the diode

58 RF ESD Design for a 5-GHz LNA Core circuit is a 5-GHz LNA in 90-nm CMOS technology. It fails at 50 V HBM without the ESD protection. The optimization of diode involves the voltage drop and critical temperature in such a device. The optimized size of diodes at I/O pads is 65 um 2. The supply clamp is a ggnmos with a width of 400 um. A series resistor may need to be added to minimize the likelihood of core circuit damage. The diode, with a maximum capacitance of 100 ff, is capable to handle 4 kv HBM. A 20% noise degradation is found. I/O D1 D2 V DD Core Circuit V SS Current I/O Supply Clamp

59 RF ESD Design for a 5-GHz LNA Box A is the ESD protection based on inductor, which acts as a low pass filter for the ESD signal The selection of inductor is not straightforward. It involves the correct inductance (1-5 nh, to couple with the capacitance), size, and resistance. An inductor with low on-resistance is preferred as the voltage drop on the inductor can damage the gate oxide of M1. For example, a 3 nh inductor (400x400 um 2 ) gives rise to a 3.8 V voltage drop. The voltage at the gate of M1 can be limited by placing a few diodes, as shown in Box B. The only purpose of these diodes is to clamp the voltage at the gate and thus the size of these diodes can be small. An ESD protection of 5.5 kv HBM can be achieved.

60 ESD Test structure of H35-50V 50 V 0 V Need a supply clamp with trigger and holding voltages > 50 V and small snapback TLP curves of MOSFET measured as a function of gate voltage

61 3) Increasing the collector resistance of the n/p/n BJT. This can be done by reducing the area of n-well, increasing the distance between p-sub/n-well and n-well/p+ junctions, and/or replacing the n-well with a lower doping region (i.e., n- region) if available. How to increase SCR s holding voltage (for supply clamp of HV circuit)? P+ N-well P-sub The holding voltage can be increased by: N+ 1) Reducing the injection efficiency of the n/p/n BJT. This can be done by reducing the emitter area and thereby reducing the injection of free-carriers into the base 2) Reducing the current gain of the n/p/n BJT. This can be achieved by increasing the distance between n+/p-sub and p-sub/n-well junctions

62 SCR Device for High Holding Voltage Application (i.e. Supply Clamp of HV Circuit) The holding voltage is 10 V. This SCR has a large distance between n+/p-sub and p-sub/n-well junctions The holding voltage is increased with the reduction of emitter area (36%, 30%, 25%, and 21% of original emitter area).

63 SCR Device for High Holding Voltage Application (i.e. Supply Clamp of HV Circuit) Cathode Anode P-ext N-Tub P-well Emitter Drain Gate Source N-well N-Tub P-ext P+ N+ Reverse P-ext N-ext P+ D7 N+ D2 P+ P+ D8 N+ D6 P-well D3 D1 L D5 D9 D4 N-well Reverse Forward N-Epitaxial Layer N+ P+ Reverse N-ext P-ext Name L D1 D4 HBM (kv) P-Cell > 8 P-Cell > 8 N-Tub P-Cell P-Cell P-Substrate P-Cell I TLP (ma/μm) V TLP (V) P-Cell 1 P-Cell 2 P-Cell 3 P-Cell 4 P-Cell Using a stack of four P-Cell 5, the holding voltage is more than 50 V and there is no snapback

64 Diode for High Holding Voltage Application (i.e. Supply Clamp of HV Circuit) Device Name D1 D2 D3 D4 D5 D6 PNPN_VH3_ The holding and trigger voltages of this diode (under reverse breakdown) is 35 V. But the diode is less robust (It2 smaller than that of SCR)

65 Outline Overview (Charge Generation, Damaging Mechanisms, ESD Models, and Protection Schemes) ESD Optimization and Design for RF Functionality Integrity (Minimize Parasitic Capacitance) ESD Modeling (MOSFET and SCR)

66 Case study V DD Consider the typical ESD protection scheme shown on the left. For computeraided design, models capable for describing the diode and MOSFET under the ESD stress are needed. I/O D1 D2 Core Circuit Current I/O Supply Clamp Here we focus on the development of a MOSFET model for ESD simulation. Vdd V SS Control Node C R Vss

67 I-V Characteristics from Measurements and Simulation Based on Conventional MOS Model Simulation 100 Measurement Device Size = 160μm/1.2μm 80 Drain Current (ma) Drain Voltage (V)

68 An NMOS Transistor with Parasitic Bipolar Action V G V S V D N+ N+ I B Impact Ionization Electrons Injected When Junction Is Forward Biased I C Depletion Boundary I SUB V B

69 Equivalent Circuit of the NMOS Devices Including Parasitic Bipolar Mechanism G S I D I DT D I E I C I h,gen I sub I B Sub R sub

70 SPICE Model Equation Set The snapback model is summarized by the following equations: 1. Generation Hole Current, I h,gen I = ( M 1) ( I + I h, gen D C 2. Multiplication Factor, M, M = 1 P exp 1 [ P /( V D V )] 1 2 Dsat 3. Substrate Resistance, R sub, R sub = R top + R bott 4. Collector Current, I C, ) V I = I C OC exp V 5. Base Current, I B, BE T V exp V BC T I oc V exp V BE T For V BC < 0 I B V BE = I exp 1 OB VT

71 Conventional Substrate Current Model ln 1 1 M 1 = P ln P V V D Dsat Interception = ln P 1 M = 1 P exp 1 [ P /( V D V )] 1 2 Dsat ln(1-1/m) Slope = -P 2 Before parasitic bipolar turns on, the substrate current can be obtained from: I D M = I I D sub /(V D -V Dsat ) (Volts -1 ) P 1 and P 2 extracted are bias independent

72 Improved Substrate Current Model The substrate current Isub of an n-channel MOSFET is originated from the holes generated in the high-field region near the drain junction and can be given in the following general expression: I sub = I D L L l d α dx n = I D A i L e L l d B i / E( x) dx Here ID is the drain current, L is the effective channel length, ld is the length of the high-field region (i.e., velocity-saturation region) near the drain junction, αn is the impact ionization rate, Ai and Bi are the ionization constants, and E(x) is the electric field in the high-field region. Clearly, in modeling Isub, ld and E(x) are two critical parameters. Source Gate Drain E(x) E m X j n + n + y x Pinch-off E s P-Substrate L-l d x m L

73 Improved Substrate Current Model High-Field Region Length (μm) Existing model [4] Present model Existing model [5] Atlas data L = 1.0,0.75, 0.5, 0.4 and 0.2 μm L decreases Maximum Electric Field (KV/cm) Existing model [3] (for L=0.75μm) Existing model [7] L=0.2μm Present model Atlas data L=0.75μm L=0.5μm L=0.5μm L=0.75μm L=0.2μm V ds -V dsat V ds (V)

74 Comparison of Different Substrate Current Models Substrate Current (μa) 70 W/L=160/1.2μm Vds=5.0 V Vbs=0 V Present model Experiment Existing model [14] Existing model [15] Existing model [16] Existing model [17] V gs (V)

75 Calculation of the Substrate Resistance R sub z x L 1. The Top Section: W = channel width, L = channel length, T = height y N+ N+ Y T L The total substrate resistance is determined by R sub = R top + R bott Substrate Contact R top = ρ[y /(WL )] Y = X j + X d /2 where ρ is the substrate resistivity, L is the effective length of the block, X j is the depth of source or drain area, and X d is the depleton width at the drain junction. 2. The Bottom Section: Approximated by 45 o spreading angle calculation, for W L R 1 L + 2T W + 2T = ln ln bott 2ρ( W L) L + 2Y W + 2 Y For W = L R bott = (T - Y )/ρ[(w + 2T)(W + 2Y )] This approach neglects the conductivity modulation due to the injection of holes

76 More Accurate Substrate Resistance Modeling Source Gate Drain y=2.45um and V gs =1.0V Hole concentration(cm -3 ) V ds =1.0V V ds =3.0V V ds =6.6V Resistivity in substrate is modulated by the holes injected in the region x-direction(μm)

77 More Accurate Substrate Resistance Modeling R 1 = q n μ n q p μ p X W ( L l d ) L S +0.8*L Inversion layer Averaged y position R 2 = k X dm X1 q 1 p( x) μ p dx A Source X sd Subregion 1 Subregion 2 X 1 X dm Drain X j X dd R 3 k = = k H Xdm q 1 p μ p dx A L L L D L S 0 L S y Subregion 3 m L H L D R sub = R R2 R3 x

78 Advanced Substrate Resistance Modeling Substrate Resist( KΩ) V gs = 3V V gs = 4V V gs = 1V V gs = 2V Present Model Spreading R[3] Atlas Simulation Drain Voltage ( V )

79 Parasitic Bipolar Transistor Modeling E-3 I C (A) 1E-4 1E-5 1E-6 1E-7 Measured I S -n F -fit I S =2.50E-13 n F = V BE (V) I I B C I S = β F I = N S qb ( e qv [( e BE / n kt qv BE F / n kt F 1) + I SE ( e 1) ( e qv qv BC BE / n kt E / n kt E 1) 1)] In the snapback region: β F ( M 1) = k 1 k 2 M = 1. 18

80 Macromodel implemented in Cadence SPICE C=3pF R=1.5K L=5uF v1=150, v2=0 tr=7nsec Block of Generation Hole Current Source BP D DB S DM G C=100pF C=2p B C E gnd! R=2K Parasitic BJT Block R=100K gnd Equivalent Circuit of HBM with Parasitic Elements (C, L) Equivalent Circuit of Improved SPICE MOS Model Simple Transient Clamp

81 Simulated and Measured I-V Curves of MOSFET Drain Current (ma) Device=160μm/1.2μm Present Model Simple Model TLP Measurement Vgs=4V Vgs=3V 40 Vgs=2V 20 ~600μA Vgs=1V Vgs=0V Drain Voltage (V)

82 Comparison of model calculations and measurements Vg=1.05V Isub (A) Vg=3.0V Vg=0.75V Id (A) Trise=8.0ns Vg=2.0 V Trise=1.5ns Vd (V) Substrate current as function of Vds and Vgs (Lines; simulation, Symbols: measurement) Vd (V) Snapback curves of a NMOS with different rise times of the voltage pulses (lines: simulation, symbols: measurement)

83 Comparison of Measured and Simulated Transient Response of Supply Clamp Drain Current (A) Present Model HBM Tester Measurements HBM Charging Voltages increasing from 400 to 1000V Transient Time (ns) Drain-Source Voltage (V) Charging voltages from 400 to 1000V HBM Tester Measurements Present Model Transient Time (ns) The ability to predict the peak drain current and holding drainsource voltage is critical for the design of a robust ESD protection structure

84 Source of drain voltage oscillation 18 P Drain Voltage (V) Drain Voltage (V) Time (ns) P6106 Drain Voltage (V) 20 P Time (ns) Time (ns)

85 Drain-Source Voltage (V) 18 Charging voltages are and 800 and 1000 V Present Model 3 Simple Model A Simple Model B Transient Time (ns) Simple Model A: lumped R sub = 2000 Ω and constant P 1 = 8.4 and P 2 = for M (M is a function of V D but not a function of V G ) Simple Model B: lumped R sub = 2000 Ω and constant M = 1.05

86 Macro Model Using BSIM3 and VBIC This approach includes three main components: NMOS modeled by BSIM3 Parasitical NPN modeled by VBIC Substrate resistance The substrate current in MOSFET and avalanche current in BJT are built in BSIM3 and VBIC, respectively: S Rs Cbe Cgs E Cgb G Isub C Iave Cgd Rd D Id=Ids+Ic Cbc Isub = α1+ α0 Leff β 0 Vds Vdeff ( Vds Vdeff ) e Idsa Bi Rsub I ave = I c AVC1 ( ) ( ) ( MC AVC 2 PC Vbci PC Vbci e 1) B Igen = Isub + Iave

87 Model Parameter Extraction First extract the BSIM3 and VBIC model parameters using standard methodology, with emphasis on the substrate current. Then extract Rsub from the triggering behavior of the ggnmos measured using TLP Adjust the gate/source and gate/drain overlap capacitances of NMOS, together with the gate resistance (several kω), to fit the snapback curves measured using TLP Snapback is measured and simulated using voltage pulses as the input

88 Comparison of model calculations and measurements Vg=1.05V Isub (A) Vg=3.0V Vg=0.75V Id (A) Trise=8.0ns Vg=2.0 V Trise=1.5ns Vd (V) Substrate current as function of Vds and Vgs (Lines; simulation, Symbols: measurement) Vd (V) Snapback curves of a NMOS with different rise times of the voltage pulses (lines: simulation, symbols: measurement)

89 Discussions V t1 and I t1 (trigger voltage and trigger current) are mostly determined by NMOS and R sub. BJT parameters have very little impact on them. V h (holding voltage) is almost only depends on the BJT parameters Both BJT and NMOS have impact on the holding current I h. R sub are influenced by both BJT and NMOS. The device s pre-snapback characteristic is almost solely determined by NMOS parameters, and BJT parameters begin to dominate the device behavior after the triggering.

90 Remarks on MOS Devices for ESD Protection In addition to the supply clamp, MOSFET can also be used as the ESD protection device at the I/O pads (replacing the diodes). For this application, the gate will need to be connected to the source and to the ground (i.e., ggmos). The ggmos has snapback and thus is more robust than the diode. The ggmos is a one-directional ESD device. This means that only the drain terminal can be subjected to the ESD stress. If the source is zapped with ESD, then oxide breakdown will occur and ggmos will be damaged. The trigger voltage of MOS device can be increased with the incorporation of LDD structure, because LDD reduces the electric field near the drain region. This minimizes the impact ionization and consequently decreases the substrate current. Thus it will take a higher ESD voltage to trigger the parasitic BJT in the MOSFET. Decreasing the substrate resistance can also increase the trigger voltage. The holding voltage and on-state resistance depend on the characteristics of the parasitic BJT. The holding voltage increases with increasing base thickness (or channel length) and with decreasing base doping (or channel region doping). SOI MOSFET for ESD application is more difficult to design, as the body is floating and the trigger mechanism is more complex. In addition, self-heating is more prominent in SOI, thus making SOI MOSFET more likely to be destroyed by the ESD stress.

91 Modeling of Silicon Controlled Rectifier (SCR) N-Well Anode Drain Gate Cathode P-Well Substrate Anode N+ P+ N+ N+ P+ P+ R Nwell_1 R Nwell_2 R Nwell_2 PNP_216 N-Well P-Well NPN_365 NPN_165 R pwell PNP_217 PNP_216 NMOS N-Epytaxial Layer NPN_165 R Nwell_1 PNP_217 R sub Rsub P- substrate Cathode R pwwell SCR device structure SCR equivalent circuit consisting of one MOSFET and three BJT s. The MOSFET and BJT are modeled using BSIM and VBIC Individual test MOSFET and BJT need to be fabricated so that the parameters associated with BSIM and VBIC can be extracted using the standard extraction procedure

92 Modeling of Silicon Controlled Rectifier (SCR) Simulated and measured MOSFET I-V characteristics Simulated and measured BJT I-V characteristics

93 Modeling of Silicon Controlled Ib=f(Vg, Vd) Rectifier (SCR) ib.m_650m ib.m_750m ib.m_950m ib.m_1.7 ib.m_2.5 ib.m_3.3 ib.s_650m ib.s_750m ib.s_950m ib.s_1.7 ib.s_2.5 ib.s_ Substrate Current Ib (A) E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 1E Vd (v) Amps Voltage TLP Measurement Simulation Simulated and measured MOSFET substrate current characteristics Simulated and measured SCR I-V characteristics