Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-μm 24 V CDMOS Process

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, 2015 ISSN(Print) ISSN(Online) Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-μm 24 V CDMOS Process Yang Wang, Xiangliang Jin, Acheng Zhou, and Liu Yang Abstract A set of novel silicon controlled rectifier (SCR) devices characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (γ) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2- dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard 0.5-μm 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What s more, their holding current is kept over 800 ma, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk. Index Terms ESD devices, holding voltage elevating, SCR structure, ring-shaped cathode Manuscript received Jan. 16, 2015; accepted Sep. 6, School of Physics and Optoelectronics, Xiangtan University, Xiangtan, , China 2 Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on A Chip, Xiangtan, , China jinxl@xtu.edu.cn I. INTRODUCTION With the trend of device dimension scaling and complexity increasing in integrated circuit, seeking for electrostatic protection device with small footprint and high current efficiency becomes a new challenge. Silicon controlled rectifier (SCR) device has excellent current discharge efficiency. But this efficiency is limited by its excessive trigger voltage (Vt1) and low holding voltage (Vh) [1]. Those demerits make it impossible to protect the core circuit efficiently and lead to latch-up issue. Researchers have put forward many methods to reduce Vt1 and improve Vh both at the process-level and in SCR structure itself. LVTSCR, GGSCR as well as Sub- Triggering SCR method can effectively reduce Vt1 lower than the breakdown voltage of the protected core circuit [2, 3], so that the SCR can switch on timely and discharge electrostatic current before internal circuit s failure. Meanwhile, the methods such as SCR cascaded diodes, source-side engineering, P+ slots insertion, and ring-resistance-triggered 6-stacked SCR-LDMOS are used to raise Vh [4-7]. However, devices with improved Vh which is really higher than operation voltage (Vop) are rarely seen in high voltage process. Liu proposed a SCR with segment cathode/anode and boost Vh up to 30 V [8], but it is difficult to grasp the relationship between segment topology and Vh due to process s variety. Junhyeong Ryu s Stacked SCR claimed to improve the Vh above Vop, but such solution requires an additional N-buried layer which is absent in the standard CDMOS process [9]. Ko proposed gate bounded diode triggered high holding voltage SCR ESD clamp for 15V IC application. But the shallow N-type well in such device is difficult to achieve unless the process

2 602 YANG WANG et al : CATHODE SIDE ENGINEERING TO RAISE HOLDING VOLTAGE OF SCR IN A 0.5-ΜM 24 V CDMOS conditions could be modified according to special demand [10]. In this paper, RASCR and RCSCR are proposed to elevate Vh without any extra mask layer and layout design rule violation. A 2-dimensional (2D) TCAD platform was used to simulate electrostatic discharge (ESD) current density distribution during the device s working process. All devices were fabricated in a standard 0.5-μm CDMOS process and measured by transmission line pulse (TLP) testing system. II. DEVICE STRUCTURE AND EQUIVALENT CIRCUIT ANALYSIS The cross sectional and layout top view of Simple SCR (S_SCR), the proposed SCR devices with ringshaped anode (RASCR) and ring-shaped cathode (RCSCR) are shown in Fig. 1. The novel SCR structures whose anode and cathode are surrounded by a ringshaped N+ or P+ diffusion region are designed to raise Vh. The parasitic BJT and resistors are depicted in the cross sectional view. (a) (b) (a) (b) (c) Fig. 2. Equivalent circuit and ESD current discharge path of (a) S_SCR, (b) RCSCR, (c) RASCR. Fig. 2 shows the equivalent circuit for those three devices respectively. They are composed of a PNP transistor, an NPN transistor and several parasitic resistances. Compared with S_SCR in Fig. 2(a), both RCSCR in Fig. 2(b) and RASCR in Fig. 2(c) possess an additional current-discharge path due to the introduction of the ring-shaped diffusion region. The inner sides of the added rings are located between the anode and cathode, and they are denoted as P+G2 and N+G2 in Fig. 1(b) and (c). Thus, parasitic resistor Rs3 or Rs4 are introduced in their equivalent circuit. For RCSCR, the parasitic PW resistance Rs3 is from cathode P+G2 to the base of NPN transistor. While for RASCR, the parasitic NW Rs4 resistance is from anode N+G2 to the base of PNP transistor. When a positive ESD pulse is stressed on the anode, additional current discharge path 2 will shunt a part of ESD current. It is obvious that the more current is shunted by path 2, a higher Vh is needed to provide sufficient current for SCR to maintain the positive feedback state. That is to say, Vh is proportional to the amount of discharging current in path 2. III. VH RAISING MECHANISM FOR RASCR AND RCSCR 1. Analysis of Emitter Injection Efficiency Factor (c) Fig. 1. Cross sectional and layout top view of (a) S_SCR, (b) RCSCR, (c) RASCR. The working mechanisms of SCR depend mainly on the pair of parasitic back-to-back BJTs, which constitute positive feedback to discharge the ESD current. Since N+ ring and P+ ring are arranged around the P+ emitter of PNP transistor in RASCR and N+ emitter of NPN transistor in RCSCR respectively, the holes or electrons

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, injecting from emitter are absorbed partly due to the heavy doped ring-type bases. Therefore, the emitter inject efficiency of one transistor in the parasitic back-toback BJTs is suppressed. The relation between emitter injection efficiency factor γ and device s physical parameters is shown in Formula (1). 1 / g = 1 + ( N B / N E ) ( DE / DB ) ( xb / xe ) (1) where NB/NE is the base/emitter doping concentration, DE/DB is the minority carrier diffusion coefficient of emitter/base, xb/xe is the width of the base/emitter region. The size of anode in Fig. 1(c) and cathode in Fig. 1(b) directly determines the effective base area of parasitic PNP (P+-NW-PW) and NPN (NW-PW-N+). Take RCSCR for example, the effective base width (that is xb) is increased because of P+ ring insertion. On the other hand, the insertion of heavily doped P+ ring in PW is equivalent to elevating the base doping concentration NB. Hence, γ factor decreases with the increasing of xb and DB. The current amplification coefficient α for BJTs is demonstrated in Formula (2) α = γ β α* M Fig. 3. Total current density (A/cm2) of S_SCR at different working state (a) Before avalanche breakdown, (b) Triggering point, (c) In the snapback, (d) High current region. (2) where β is the transport coefficient, α* is the collector multiplication factor, M is avalanche multiplication factor. Thus, α is decreased as γ depressing, and larger Vh is required to supply more positive feedback current after the BJT s triggering. Hence, it is proved that RASCR and RCSCR are candidate devices in improving Vh of SCR. Fig. 4. Total current density (A/cm2) of RCSCR at different working state (a) Before avalanche breakdown, (b) Triggering point, (c) In the snapback, (d) High current region. 2. TCAD Simulation for SCR Devices To further look into the working mechanism of the proposed devices, a 2D device simulation tool Atlas was used to verify the above mentioned analysis. The current density distribution during the ESD current discharging procedure of S_SCR, RCSCR and RASCR devices are shown in Figs. 3-5, respectively. Four separate insets in each figure represent one state at the SCR s ESD snapback I-V curve in a proper sequence: (a) Before avalanche breakdown, (b) Triggering point, (c) Snapback happen, (d) Large current discharging region. Fig. 5. Total current density (A/cm2) of RASCR at different working state (a) Before avalanche breakdown, (b) Triggering point, (c) In the snapback, (d) High current region.

4 604 YANG WANG et al : CATHODE SIDE ENGINEERING TO RAISE HOLDING VOLTAGE OF SCR IN A 0.5-ΜM 24 V CDMOS In the S_SCR structure, the leakage current flows from anode P+ bulk to cathode N+ bulk before avalanche breakdown, and is shown in Fig. 3(a). Then avalanche breakdown happens on the edge of PW-NW junction, and the device is triggered on (Fig. 3(b)). Almost all ESD current pours out from anode P+/N+ to cathode N+, which exhibits in the Fig. 3(c) and (d). Thus, it is the unique ESD current discharging path in the body of S_SCR. While the leakage current stream before triggering in RCSCR, is from anode P+ to cathode P+_G2, which is the nearest P+ bulk to the reverse biased NW-PW junction (Fig. 4(a)). Avalanche breakdown still occurs on such reverse biased junction (Fig. 4(b)). What should be noted is that, the current path, which determines Vh to some extent, is clearly divided into two streams after entering the snapback region in Fig. 4(c). It is clearly that, the current which original sinks to cathode N+ in S_SCR, is partly shunted by the inner P+ bulk of P+ diffusion ring at cathode side. Path1 and path2 both dominate the current discharging routing. Thus, higher Vh is demanded to provide enough feedback current to maintain the positive feedback mechanism in SCR structure. RASCR is analyzed in the same way, if an ESD pulse is stressed on the anode, nearly no current appears in the outer N+ bulk of anode N+ diffusion ring at triggering point (Fig. 5(a) and (b)). When it comes to the high current region after holding point, current distributed at anode P+ region decreases gradually, which is shown in Fig. 5(c) and (d). Hence, the entire device is equivalent to an NPN (N+_G1/G2-PW-N+) BJT, which is different from RCSCR. The P+ diffusion region only provides small base current for NPN transistor. Thus, we can infer that Vh of RASCR is indeed Vce of common BJT, which is slightly higher than Vh of S_SCR, but will not improve Vh a lot. The reason why the parasitic SCR structure does not work is that, the doping density of NW is higher than that of PW, thus, Rs4 in RASCR is much smaller than Rs3 in RCSCR. Hence, path2 in RASCR bypasses too much current to sustain the positive feedback mechanism in SCR structure. IV. EXPERIMENT RESULTS BASED ON THE TLP TEST SYSTEM In order to verify previous simulation and analysis, two groups of S_SCR, RCSCR and RASCR were fabricated in a 0.5 μm 24 V CDMOS process and tested in TLP system. The device dimensions denoted in Fig. 1 are listed in Table 1. D1 is not recorded in this table, it is 3 μm in all devices. The detailed TLP testing results are also summarized in Table 1. The ring width D2 remains 1.5 μm to keep the length of all SCR s anode and cathode is the same. TLP measurement results of Group1 with D3 = 0 μm and Group2 with D3 = 2 μm are shown in Fig. 6 and Fig. 7, respectively. Device with different D3 is used to prove the universality of conclusions. The relationship of Vh is: Vh_ RCSCR > Vh_ RASCR > Vh_ S_SCR, which is in accordance with the simulation results in section III. It is worth mentioning that Vh_ RCSCR is raised to 31 V~33 V, which is higher than Vop of 24 V, and its holding current is over 800 ma further. Such features make it suitable to be used as power clamp, and keep the protected chip away from latch-up risk firmly. Though the current discharge efficiency of RCSCR decreased obviously, it is still higher than that of common LDMOS, for discharge efficiency of 1-fingered 50 μm 24V nldmos fabricated in the same process is 0.52 ma/μm 2. Another feature detected in Table 1 is that the higher the holding voltage is, the smaller the current discharge efficiency is. As a result, it is necessary to trade off Fig. 6. Measured TLP I-V curves of D3 = 0 μm S_SCR_1, RCSCR_1 and RASCR_1.

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, Table 1. TLP data for S_SCR and the proposed SCR with device width of 50 μm DUT D2 (μm) D3 (μm) Vt1 (V) Vh (V) Ih (ma) It2 (A) It2/Area (ma/μm 2 ) FOM_2 (ma/μm 2 ) S_SCR_ S_SCR_ RCSCR_ RCSCR_ RASCR_ RASCR_ Table 2. Comparison of various high-vh devices in high voltage process DUT Technology FOM_1 (ma/μm) FOM_2 (ma/μm 2 ) RCSCR_1 0.5-μm 24 V CDMOS process Source-side engineering proposed by Chen in [5] 0.5-μm 16 V BCD process 2 / P+ slots insertion proposed by Yang in [6] 0.5-μm HV CDMOS process 7 / Ring-resistance-triggered 6-stacked devive proposed by Ma in [7] Gate bounded diode triggered high Vh SCR proposed by Ko in [10] 0.35-μm 30 V/5 V BCD process 5 / 0.35-μm 15 V process / Fig. 8. Photograph of the fabricated device RCSCR_1. evaluation FOM_2 is introduced to take area into consideration. FOM _ 2 = It2 Vh Area Vt1 (4) Fig. 7. Measured TLP I-V curves of D3 = 2 μm S_SCR_2, RCSCR_2 and RASCR_2. between current discharging efficiency and holding voltage in considering the application circumstance. A figure of merit (FOM) is defined to evaluate the performance for various ESD devices in reference [11]: It2 Vh FOM _1 = N W Vt1 where It2 is the failure current, Vh is the holding voltage, N is the number of the stacked devices in reference [11], W is the total width of the protection device, and Vt1 is the trigger voltage. In our Vh improving scheme, N = 1. However, the above formula doesn t consider the impact of device area on ESD performance. Thus, the following (3) where Area is the device area. It is inferred from the above formula that, FOM can be improved by decreasing Area and Vt1, as well as by increasing It2 and Vh. FOM_2 listed in Table 1 indicate that, the RCSCR devices have the best ESD performance due to its cathode side layout improvement. Furthermore, the comparison of various high-vh devices in high-voltage process is a summarized in Table 2. The RCSCR is the most optimal device. And the photograph of manufactured device RCSCR_1 is shown in Fig. 8. V. CONCLUSIONS SCR with ring-shaped anode or cathode is proposed in this paper. And the cause for holding voltage elevating in those devices is discussed. It comes to conclusions as

6 606 YANG WANG et al : CATHODE SIDE ENGINEERING TO RAISE HOLDING VOLTAGE OF SCR IN A 0.5-ΜM 24 V CDMOS follows: (1) The ring surrounding anode/cathode helps SCR to introduce a new ESD current discharging path, thereby a bigger holding voltage is obtained to maintain the positive feedback; (2) Additional ring improves the effective width of base in BJT (meaning x B ) and enlarges the diffusion coefficient of base (meaning D B ), the holding voltage of SCR is raised by deducing from the presentation of γ; (3) As shown in the current density distribution, the current shunting by path2 of RCSCR is much larger than that of RASCR, hence, it infers that Vh_ RCSCR > Vh_ RASCR, and it is proved by TLP measurement results. ACKNOWLEDGMENTS This work is supported by the National Natural Science Foundation of China (Grant No and ) and by Hunan Provincial Natural Science Fund for Distinguished Young Scholars (2015JJ1014). REFERENCES [1] Chen, W. Y. : Overview of On-Chip Electrostatic Discharge protection design with SCR-Based devices in CMOS Integrated Circuits, IEEE Transactions on Device and Materials Reliability, 2005, 5, (2), pp [2] Jang, S. L., and Li, S. H. : MOSFET triggering silicon controlled rectifiers for electrostatic discharge protection circuits, Solid State Electronics, 2001, 45, pp [3] Ker, M. D., and Hsu, K. C. : Substrate-Triggered SCR device for On-Chip ESD protection in fully silicided Sub-0.25-μm CMOS process, IEEE Transactions on Electron Devices, 2003, 50 (2), pp [4] Zhou, A. C., Wang, Y., and Jin, X. L. : Impact of Layout Skill to Improve ESD Holding Voltage of SCR Embeded Diode Structure, Proc. Int. Conf. on EIEE, Changsha, China, June 2012, Vol. 1, pp [5] Chen, W. Y., Ker, M. D., and Jou, Y. N. : Source- Side engineering to increase holding voltage of LDMOS in a 0.5μm 16V BCD technology to avoid latch-up failure, Proc. Int. Conf. on IPFA, China, June 2009, Vol. 1, pp [6] Yang, L., Wang, Y., Zhou, A., and Jin, X. L. : Design, fabrication and test of novel LDMOS- SCR for improving holding voltage, Solid-State Electronics, 2015, 103 (2015), pp [7] Ma, F., Zhang, B., Han, Y., Zheng, J., Song, B., Dong, S., Liang, H. : High Holding Voltage SCR- LDMOS Stacking Structure With Ring-Resistance- Triggered Technique, IEEE Electron Device Letters, 2013, 34(9), pp [8] Liu, Z. W., Liu, J. J., and Vinson, J. E : Silicon- Controlled Rectifier (SCR) device for high-voltage electrostatic discharge (ESD) applications, US Patent Al, August. 27, 2009 [9] Ryu, J. Y., Kang, T. K.,and Shiheung, M. K.: Stacked SCR with high holding voltage, US Patent B2, August. 10, 2010 [10] Ko, J. H., Kim, H. G., Jeon, J. S. : Gate bounded diode triggered high holding voltage SCR clamp for on-chip ESD protection in HV ICs, IEEE 35th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2013, pp. 1-8 [11] Dong, S. R., Jin, H., Miao, M., Wu, J., Liou, J. J. : Novel capacitance coupling complementary dualdirection SCR for high-voltage ESD, IEEE Electron Device Lett, 2012, 33, (5), pp Yang Wang received her M.S. degree in micro-electronics and solid-state electronics with emphasis in digital filter design from Xiangtan University in 2007, and Ph.D. degree in School of Physics and Optoelectronics at the same university in Now, she is associate professor in Xiangtan University. Her current research interest is on-chip ESD protection design for HV ICs. Xiangliang Jin received the M.S. degree in micro technology with emphasis in electric circuits from Hunan University in He received the Ph.D. degree in microelectronics and solid-state circuits with emphasis in CMOS image

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.6, DECEMBER, 2015 sensor design from institute of microelectronics of Chinese academy of sciences in March After graduation, he sets up Superpix Micro technology Ltd. as one co-founder. From March 2010, he is a full professor in Xiangtan University. His interests include MEMS and readout circuit design, CMOS image sensor design, and mixed-mode application-specific integrated circuits with emphasis on high-performance imaging. Acheng Zhou received the B.S. degree and M.S. degree in School of Physics and Optoelectronics at Xiangtan University, Xiangtan, China, in 2011 and 2014, respectively. Now, she is an analog IC design enginner with Mornsun, China. Her research interests include smart power IC design and on-chip ESD protection design. 607 Liu Yang received the B.S. degree in Microelectronics from Xiangtan University in 2014, where she is currently working toward the M.S. degree in School of Physics and Optoelectronics at Xiangtan University. Her major is with on-chip ESD protection design.