AUSTIN SEMICONDUCTOR, INC. 4 MEG x 1 DRAM RAS *A10. Vcc 2-23

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1 RAM AUSTIN SEMICONUCTOR INC. 4 MEG x 1 RAM FAST PAGE MOE AAABLE AS MITARY SPECIFICATONS SM M-ST-883 PIN ASSIGNMENT (Top iew) 18-Pin IP 20-Pin ZIP FEATURES Industry standard x1 pinout timing functions and packages High-performance CMOS silicon-gate process Single +5 ±10% power supply Low-power 2.5mW standby; 300mW active typical All inputs outputs and clocks are fully TTL and CMOS compatible 1024-cycle refresh distributed across 16ms Refresh modes: /R?A/S-ONLY /C/A/S-BEFORE-/R/?A/S (CBR) and HIEN FAST PAGE MOE access cycle CBR with?w/e a HIGH (JEEC test mode capable via WCBR) OPTIONS MARKING Timing 70ns access ns access ns access ns access -12 *A10 A0 A1 A2 A3 cc ss A9 A8 A7 A6 A5 A4 A9 NC A0 A2 cc A5 A Pin SOJ 20-Pin LCC 20-Pin Gull Wing NC *A ss NC A ss A10* NC A1 A3 A4 A6 A8 Packages Ceramic IP (300 mil) CN No. 101 Ceramic IP (400 mil) C No. 102 Ceramic LCC ECN No. 202 Ceramic SOJ ECJ No. 504 Ceramic ZIP CZ No. 400 Ceramic Gull Wing ECG No. 600 A0 A1 A2 A3 cc A8 A7 A6 A5 A4 GENERAL ESCRIPTION The MT4C1004J is a randomly accessed solid-state memory containing bits organized in a x1 configuration. uring REA or WRITE cycles each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits and /C/A/S the latter 11 bits. A REA or WRITE cycle is selected with the?w/e input. A logic HIGH on?w/e dictates REA mode while a logic LOW on?w/e dictates WRITE mode. uring a WRITE cycle data-in () is latched by the *Address not used for /R/A/S-ONLY REFRESH falling edge of?w/e or /C/A/S whichever occurs last. If?W/E goes LOW prior to /C/?A/S going LOW the output pin remains open (High-Z) until the next /C/A/S cycle. If?W/E goes LOW after data reaches the output pin is activated and retains the selected cell data as long as /C/A/S remains LOW (regardless of?w/e or /R/A/S). This LATE-?W/E pulse results in a REA-WRITE cycle. FAST PAGE MOE operations allow faster data operations (REA WRITE or REA-MOIFY- WRITE) within a row-address (A0 -A10) defined page RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

2 AUSTIN SEMICONUCTOR INC. boundary. The FAST PAGE MOE cycle is always initiated with a row address strobed-in by /R/A/S followed by a column address strobed-in by /C/A/S. /C/A/S may be toggled-in by holding /R/A/S LOW and strobing-in different column addresses thus executing faster memory cycles. Returning /R/A/S HIGH terminates the FAST PAGE MOE operation. Returning /R/A/S and /C/A/S HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also the chip is preconditioned for the next cycle during the /R/A/ S HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any /R?A/S cycle (REA WRITE /R?A/S-ONLY /C/A/S-BEFORE-/R/A/S or HIEN RE- FRESH) so that all 1024 combinations of /R?A/S addresses (A0 -A9) are executed at least every 16ms regardless of sequence. The /C?A/S- BEFORE-/R?A/S cycle will invoke the refresh counter for automatic /R/?A/S addressing. FUNCTIONAL BLOCK IAGRAM FAST PAGE MOE ATA IN BUFFER NO. 2 CLOCK GENERATOR *EARLY-WRITE ETECTION CIRCUIT ATA OUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A ESS BUFFER(11) REFRESH CONTRLER REFRESH COUNTER 10 ESS BUFFERS (11) ECOER 1024 ECOER 4096 SENSE AMPLIFIERS I/O GATING 4096 MEMORY ARRAY NO. 1 CLOCK GENERATOR cc ss *NOTE: LOW prior to LOW EW detection circuit output is a HIGH (EARLY-WRITE) LOW prior to LOW EW detection circuit output is a LOW (LATE-WRITE) RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

3 AUSTIN SEMICONUCTOR INC. TRUTH TABLE ESSES ATA FUNCTION?R/A/S?C/A/S?W/E t R t C (ata In) (ata Out) Standby H H>X X X X on t Care High-Z REA L L H C on t Care ata Out EARLY-WRITE L L L C ata In High-Z REA-WRITE L L H>L C ata In ata Out FAST-PAGE-MOE 1st Cycle L H>L H C on t Care ata Out REA 2nd Cycle L H>L H n/a C on t Care ata Out FAST-PAGE-MOE 1st Cycle L H>L L C ata In High-Z EARLY-WRITE 2nd Cycle L H>L L n/a C ata In High-Z FAST-PAGE-MOE 1st Cycle L H>L H>L C ata In ata Out REA-WRITE 2nd Cycle L H>L H>L n/a C ata In ata Out /R/A/S-ONLY REFRESH L H X n/a on t Care High-Z HIEN REA L>H>L L H C on t Care ata Out REFRESH WRITE L>H>L L L C ata In High-Z /C/A/S-BEFORE-/R/A/S REFRESH H>L L H X X on t Care High-Z RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

4 AUSTIN SEMICONUCTOR INC. ABSUTE MAXIMUM RATINGS* oltage on any pin Relative to SS to +7.0 Power issipation... 1W Short Circuit Output Current... 50mA Lead Temperature (Soldering 5 Seconds) C Storage Temperature C to +150 C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AN RECOMMENE C OPERATING CONITIONS (Notes: 1 6 7) (-55 C T A 125 C; CC = 5 ± 10%) PARAMETER/CONITION SYMB MIN MAX UNITS NOTES Supply oltage CC Input High (Logic 1) oltage All Inputs IH 2.4 CC+.5 Input Low (Logic 0) oltage All Inputs INPUT LEAKAGE CURRENT Any Input 0 IN 5.5 CC=5.5 II -5 5 µa (All other pins not under test = 0) OUTPUT LEAKAGE CURRENT ( is isabled 0 OUT 5.5) CC=5.5 IOZ -5 5 µa OUTPUT LEELS OH 2.4 Output High oltage (IOUT = -5mA) Output Low oltage (IOUT = 4.2mA) 0.4 MAX PARAMETER/CONITION SYMB UNITS NOTES STANBY CURRENT (TTL) ICC ma (/R/A/S = /C/A/S = IH) STANBY CURRENT (CMOS) ICC ma (/R/A/S = /C/A/S = CC -0.2; all other inputs = CC -0.2) OPERATING CURRENT: Random REA/WRITE Average Power-Supply Current ICC ma 3 4 (/R/A/S /C/A/S Address Cycling: t RC = t RC (MIN)) OPERATING CURRENT: FAST PAGE MOE Average Power-Supply Current ICC ma 3 4 (/R/A/S = /C/A/S Address Cycling: t PC = t PC (MIN)) REFRESH CURRENT: /R/A/S-ONLY Average Power-Supply Current ICC ma 3 (/R/A/S Cycling /C/A/S = IH: t RC = t RC (MIN)) REFRESH CURRENT: /C/A/S-BEFORE-/R/A/S Average Power-Supply Current ICC ma 3 5 (/R/A/S /C/A/S Address Cycling: t RC = t RC (MIN)) RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

5 AUSTIN SEMICONUCTOR INC. CAPACITANCE PARAMETER SYMB MIN MAX UNITS NOTES Input Capacitance: A0-A10 CI1 7 pf 2 Input Capacitance: /R/A/S /C/A/S?W/E CI2 7 pf 2 Output Capacitance: CO 8 pf 2 ELECTRICAL CHARACTERISTICS AN RECOMMENE AC OPERATING CONITIONS (Notes: ) (-55 C T C 125; CC = 5 ± 10%) AC CHARACTERISTICS PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES Random REA or WRITE cycle time t RC ns REA-WRITE cycle time t RWC ns FAST-PAGE-MOE REA t PC ns or WRITE cycle time FAST-PAGE-MOE REA-WRITE t PRWC ns cycle time Access time from /R/A/S t RAC ns 14 Access time from /C/A/S ns 15 Access time from column address ns Access time from /C/A/S precharge t CPA ns /R/A/S pulse width t ns /R/A/S pulse width (FAST PAGE MOE) t P ns /R/A/S hold time t RSH ns /R/A/S precharge time ns /C/A/S pulse width t ns /C/A/S hold time t CSH ns /C/A/S precharge time t CPN ns 16 /C/A/S precharge time (FAST PAGE MOE) t CP ns /R/A/S to /C/A/S delay time t RC ns 17 /C/A/S to /R/A/S precharge time t CRP ns Row address setup time t ASR ns Row address hold time t RAH ns /R/A/S to column t RA ns 18 address delay time Column address setup time ns Column address hold time ns Column address hold time t AR ns (referenced to /R/A/S) Column address to t RAL ns /R/A/S lead time Read command setup time t RCS ns Read command hold time t RCH ns 19 (referenced to /C/A/S) Read command hold time t RRH ns 19 (referenced to /R/A/S) /C/A/S to output in Low-Z ns Output buffer turn-off delay ns 20?W/E command setup time t WCS ns 21 RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

6 AUSTIN SEMICONUCTOR INC. ELECTRICAL CHARACTERISTICS AN RECOMMENE AC OPERATING CONITIONS (Notes: ) (-55 C T C 125; CC = 5 ± 10%) AC CHARACTERISTICS PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES Write command hold time t WCH ns Write command hold time t WCR ns (referenced to /R/A/S) Write command pulse width t WP ns Write command to /R/A/S lead time t RWL ns Write command to /C/A/S lead time ns ata-in setup time t S ns 22 ata-in hold time t H ns 22 ata-in hold time t HR ns (referenced to /R/A/S) /R/A/S to?w/e delay time t RW ns 21 Column address t AW ns 21 to?w/e delay time /C/A/S to?w/e delay time t CW ns 21 Transition time (rise or fall) t T ns Refresh period (1024 cycles) t REF ms /R/A/S to /C/A/S precharge time C ns /C/A/S setup time t CSR ns 5 (/C/A/S-BEFORE-/R/A/S REFRESH) /C/A/S hold time t CHR ns 5 (/C/A/S-BEFORE-/R/A/S REFRESH)?/W/E hold time t WRH ns (/C/A/S-BEFORE-/R/A/S REFRESH)?/W/E setup time t WRP ns (/C/A/S-BEFORE-/R/A/S REFRESH)?/W/E hold time t WTH ns (WCBR test cycle)?/w/e setup time t WTS ns (WCBR test cycle) RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

7 AUSTIN SEMICONUCTOR INC. NOTES 1. All voltages referenced to SS. 2. This parameter is sampled not 100% tested. Capacitance is measured with cc = 5 f = 1 MHz at less than 50mrms T A = 25 C ±3 C bias = 2.4 applied to each input and output individually with remaining inputs and outputs open. 3. ICC is dependent on cycle rates. 4. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the output open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55 C T A 125 C) is assured. 7. An initial pause of 100µs is required after power-up followed by eight /R?A/S refresh cycles (/R/A/S-ONLY or CBR with?/w/e HIGH) before proper device operation is assured. The eight /R/A/S cycle wake-up should be repeated any time the 16ms refresh requirement is exceeded. 8. AC characteristics assume t T = 5ns. 9. IH (MIN) and (MAX) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH). 10. In addition to meeting the transition rate specification all input signals must transit between IH and (or between and IH) in a monotonic manner. 11. If /C/A/S = IH data output is High-Z. 12. If /C/A/S = data output may contain data from the last valid REA cycle. 13. Measured with a load equivalent to 2 TTL gates and 100pF. 14. Assumes that t RC < t RC (MAX). If t RC is greater than the maximum recommended value shown in this table t RAC will increase by the amount that t RC exceeds the value shown. 15. Assumes that t RC t RC (MAX). 16. If /C/A/S is LOW at the falling edge of /R/A/S will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer /C/A/S must be pulsed HIGH for t CPN. 17. Operation within the t RC (MAX) limit ensures that t RAC (MAX) can be met. t RC (MAX) is specified as a reference point only; if t RC is greater than the specified t RC (MAX) limit then access time is controlled exclusively by. 18. Operation within the t RA (MAX) limit ensures that t RC (MAX) can be met. t RA (MAX) is specified as a reference point only; if t RA is greater than the specified t RA (MAX) limit then access time is controlled exclusively by. 19. Either t RCH or t RRH must be satisfied for a REA cycle. 20. (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to OH or. 21. t WCS t RW t AW and t CW are restrictive operating parameters in LATE WRITE REA-WRITE and REA-MOIFY-WRITE cycles only. If t WCS t WCS (MIN) the cycle is an EARLY-WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t RW t RW (MIN) t AW t AW (MIN) and t CW t CW (MIN) the cycle is a REA-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions are met the cycle is a LATE-WRITE and the state of is indeterminate (at access time and until /C/A/S goes back to IH). 22. These parameters are referenced to /C/A/S leading edge in EARLY-WRITE cycles and?w/e leading edge in LATE-WRITE or REA-WRITE cycles. 23. A HIEN REFRESH may also be performed after a WRITE cycle. In this case?w/e = LOW. 24. t WTS and t WTH are set up and hold specifications for the?w/e pin being held LOW to enable the JEEC test mode (with CBR timing constraints). These two parameters are the inverts of t WRP and t WRH in the CBR REFRESH cycle. 25. JEEC test mode only. RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

8 AUSTIN SEMICONUCTOR INC. REA CYCLE t RC t IH t CSH t RSH t RRH t CRP t RC t IH IH IH t ASR t AR t RA t RAL t RAH tcah t RCS t RCH t RAC OH ALI ATA EARLY-WRITE CYCLE t RC t trp IH t CSH t CRP t RC t RSH t IH IH t AR t RA t RAL t ASR t RAH IH IH t WCS t S ALI ATA t RWL t WCR t WCH t WP t HR t H OH ON T CARE UNEFINE RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

9 AUSTIN SEMICONUCTOR INC. REA-WRITE CYCLE (LATE-WRITE and REA-MOIFY-WRITE CYCLES) t RWC t trp IH t CSH t RSH t CRP t RC t IH t AR IH IH IH OH t RA t RAL t ASR t RAH t RW t RCS t AW t CW t RAC t S t CLZ t RWL t WP t H ALI ATA ALI ATA FAST-PAGE-MOE REA CYCLE t P IH t CSH t PC t RSH t CRP t RC t t CP t t CP t t CPN IH t AR IH IH t ASR t RA t RAH t RCS t RCS t RRH t RCS t RCH t RCH t RCH t RAL t RAC t CPA t CPA OH ATA ATA ALI ATA ON T CARE ALI ALI UNEFINE RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

10 AUSTIN SEMICONUCTOR INC. FAST-PAGE-MOE EARLY-WRITE CYCLE t P IH t CSH t PC t RSH t CRP t RC t t CP t t CP t t CPN IH IH IH t ASR t RA t RAH t AR t WCS t WCH t WP t WCS t WCH t WP t WCS t RAL t WCH t WP IH t WCR t HR t S t H t S t H t S t H ALI ATA ALI ATA ALI ATA t RWL IH FAST-PAGE-MOE REA-WRITE CYCLE (LATE-WRITE and REA-MOIFY-WRITE CYCLES) t P IH t CRP t CSH t RC t * tpc t CP t PRWC t t CP t RSH t tcpn IH IH t AR t RA t ASR t RAH tcah tasc tcah tasc t RAL t RW t RWL t RCS IH IH t AW t WP t AW t WP t AW t WP t CW t CW t S t H t S t H ALI ATA ALI ATA t CPA t CW t S t H ALI ATA t CPA t RAC OH * t PC = LATE-WRITE Cycle t PRWC = FAST REA-MOIFY-WRITE Cycle ALI ATA ALI ATA ALI ATA ON T CARE UNEFINE RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

11 /// // // /// // // // // // AUSTIN SEMICONUCTOR INC. //R/ //A/ //S-ONLY REFRESH CYCLE ( = A0-A9; A10 and?w/e = ON T CARE) t RC t IH t CRP C IH IH t ASR t RAH OH //C/ //A/ //S-BEFORE-/ //R/ //A/ //S REFRESH CYCLE (A0-A10 = ON T CARE) t t IH C t CPN t CSR t CHR C t CSR tchr IH IH t WRP t WRH t WRP t WRH HIEN REFRESH CYCLE 23 (?W/E = HIGH) (REA) t (REFRESH) t IH t CRP t RC t RSH t CHR IH IH t ASR t AR t RA t RAH tral t RAC OH ALI ATA ON T CARE UNEFINE RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

12 AUSTIN SEMICONUCTOR INC. 4 MEG POR-UP AN REFRESH CONSTRAINTS The EIA/JEEC 4 Meg RAM introduces two potential incompatibilities compared to the previous generation 1 Meg RAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg. REFRESH The most commonly used refresh mode of the 1 Meg is the CBR (?C?A/S-BEFORE-?R?A/S) REFRESH cycle. The CBR for the 1 Meg specifies the?w/e pin as a don t care. The 4 Meg on the other hand specifies the CBR REFRESH mode with the?w/e pin held at a voltage HIGH level. A CBR cycle with?w/e LOW will put the 4 Meg into the JEEC specified test mode (WCBR). POR-UP The 4 Meg JEEC test mode constraint may introduce another problem. The 1 Meg POR-UP cycle requires a 100µs delay followed by any eight?r?a/s cycles. The 4 Meg POR-UP is more restrictive in that eight?r?a/s-only or CBR REFRESH (?W/E held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEEC specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEEC test mode is with either a?r?a/s-only or a CBR REFRESH cycle (?W/E held HIGH). SUMMARY 1. The 1 Meg CBR REFRESH allows the?w/e pin to be don t care while the 4 Meg CBR requires?w/e to be HIGH. 2. The eight?r?a/s wake-up cycles on the 1 Meg may be any valid?r?a/s cycle while the 4 Meg may only use?r?a/s- ONLY or CBR REFRESH cycles (?W/E held HIGH). t t IH C t CPN t CSR t CHR C t CSR tchr 4 MEG RAM 1 MEG RAM IH OH WCBR TEST MOE: CBR REFRESH: CBR REFRESH: IH IH IH t WRP t WRH t WTS t WTH t WTS t WTH t WRP t WRH ON T CARE COMPARISON OF 4 MEG TEST MOE AN WCBR TO 1 MEG CBR RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

13 AUSTIN SEMICONUCTOR INC. ELECTRICAL TEST REUIREMENTS SUBGROUPS M-ST-883 TEST REUIREMENTS (per Method 5005 Table I) INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2 8A 10 (Method 5004) FINAL ELECTRICAL TEST PARAMETERS 1* 2 3 7* (Method 5004) GROUP A TEST REUIREMENTS ** (Method 5005) GROUP C AN EN-POINT ELECTRICAL PARAMETERS (Method 5005) * PA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes which may affect input or output capacitance. RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.

14 AUSTIN SEMICONUCTOR INC. RE. 11/ Austin Semiconductor Inc. reserves the right to change products or specifications without notice.