Low Power, High Speed Hybrid Clock Divider Circuit

Transcription

1 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] Lw Pwer, High Speed Hybrid k Divider Ciruit Jhn Reuben, Mhammed Zakriya. V Sehl feleetrnies Engineering, VIT University, Vellre, lndia jhnreuben@vit. ae.in, rndzaekriya@rediff.ern Dr.Harish M Kittur Sehl feleetrnies Engineering, VIT University, Vellre, lndia kittur@vit. ae. in Abstrat- The k Divider iruit has fund immense appliatin in Multiple k Dmain (MCD) systems like ASICs, SC and GALS. In MCD systems, we generate many Ik signals f varius frequenies frm a high frequeny Ik by frequeny divisin. Pwer is an imprtant parameter t be minimized sine the ndes in a Ik divider iruit will tggle at Ik frequeny. In this paper, we present a lw pwer hybrid Ik divider iruit wh ih an take an input frequeny up t 6 GHz and perfrm frequeny divisin. The divider is hybrid beause it uses tw different tlip flps - a Mdified Extended True Single-Phase k tlip flp (METSPC-FF) and a self blking FF (SBFF).The METSPC-FF is fast enugh t divide a GHz frequeny, but nsumes mre pwer when mpared t SBFF, while the SBFF is relatively slw but nsumes less pwer mpared t METSPC. We analyze the perfrmane f these 2 FFs arss PVT variatins and implement them in a Ik divider iruit. Our Ik divider iruit nsumes /lw pwer fr 'divide by' 8 peratin n a 6 GHz Ik. Simulatin f these tlip flps in TSMC 90 nm tehnlgy using CADENCE SPECTRE simulatr shws that they are very energy effiient and hene an be used fr ther high speed appliatins withut mprmising n the pwer. Keywrds: k Divider (CD); TSPC flip flp; Self blking Flip flp; prpagatin delay; pwer dissipatin; Hybrid k Divider(HCD); METSPC; ETSPC,PVT In this paper, we present a lw pwer hybrid lk divider iruit whih an take an input frequeny up t 6 GHz and perfrm frequeny divisin. The divider is hybrid beause it uses tw different tlip flps - a mdified ETSPC tlip flp (METSPC-FF) and self blking FF (SBFF) [4]. The METSPC-FF is fast enugh t divide a GHz frequeny, but nsumes mre pwer when mpared t SBFF belw 1.5 GHz, while the SBFF is relatively slw but nsumes less pwer mpared t METSPC. The paper is rganized as fliws: Setin 11 desribes the design f METSPC-FF and its simulatin results in TSMC 90 nm. Setin III desribes the SBFF as presented in [4] and its simulatin results in TSMC 90 nm (In [4], the SBFF is simulated in SMIC 65 nm tehnlgy).the hybrid lk divider iruit is presented in setin IV with the simulatin results. We nlude with pssible future wrk in setin V. 11.MODIFIED ETSPC FLIP FLOP (METSPC-FF) A. Basie ETSPC Flip flp A dynami ETSPC flip flp is presented in [3], whih desn't have staked MOS struture that slws the swithing speed. I.INTRODUCTION The k Divider iruit has fund immense appliatin in multiple lk dmain(mcd) systems like ASICs, SC(System n Chip) and GALS(Glbally Asynhrnus, Lally Synhrnus).SC, whih is an IC designed by stithing tgether multiple stand-alne VLSI designs( alled IPs) t prvide full funtinality fr an appliatin[l] has different IP blks perating at different lk frequeny. k generatin and lk distributin fr these MCD systems are the stliest in terms f pwer nsumptin [2].The lk generatin system generates different frequenies fr the lk dmains frm the basi rystal sillatr (tens f MHz) using PLLs(as frequeny multipliers) fllwed by k Dividers. Hene minimizing the pwer nsumptin f the lk divider iruit is a ruial step in the design f k generatr iruit fr MCD systems. S1 S2 Q W/L=1.2 Fig. 1. ETSPC [3] The ETSPC shwn in Fig. 1 is a negative edge triggered flip flp. When the lk is high, NI and N2 will be n, P3 will be ff. The nde SI and S2 is preharged t lw thrugh NI and N2 irrespetive f D state /13/$ IEEE 935

2 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-20I3] The evaluatin phase starts at the negative edge f the lk. Case 1: If D is lw, PI will turn n t make nde SI high whih in turn will turn ff P2 t make nde S2 stay lw. Thus nde S2 will turn ff N3 t make nde S3 (q) high and hene Q will beme lw. Case 2: If D is high, PI will turn ff t make nde SI stay lw whih in turn will turn n P2 t make nde S2 high. Thus nde S2 will turn n N3 t make nde S3 (Q ) lw and hene Q will beme high. Table 1. State f ndes at Preharge Phase Q'-l Case k Dt A B Q, Q, 0 Ip p Ip p Case 2p: When D is high, NI will be turned n, thus nde A will disharge thrugh NI and it will turn ff N2, therefre nde B will stay high thrugh P2. B. Prpsed Mdified ETSPC Flip flp The basis ETSPC [3] has delay f ps and nsumes /lw pwer resuiting in a PDP f 5.12 fj at 6 GHz (Nminal press rner). We prpse a Mdified ETSPC FF (Fig. 2) whih has a better PDP as will be disussed belw. Sine bth P3 and N3 will stay turned ff in preharge phase, Q, and Q, will hld the previus state ['-I and Qt-l respetively even thugh the present state f D (Dt) hanges as shwn in Table 1. Evaluatin Phase: When lk ges high, transistr PI, P2 will be turned ff, N3 will be turned n and the nde A and B will hld the preharge state as in Table.2 Table 2. State f ndes at Evaluatin Phase Case k Dt A B Q, Qt A W/L=1.2 B Ie 2e J J 0 I Fig. 2. METSPC -FF The prpsed METSPC-FF is a psitive edge triggered FF. It nsists f preharge and evaluatin phase as desribed. The lk signal (CLK) is generated n hip frm the PLL and fed t the flip flps. Preharge Phase: When lk is lw, transistr PI, P2 will be turned n and N3 will be turned ff. Case 1p: When D is lw, NI will be turned ff, thus nde A will be high thrugh PI and it will turn n N2. Sine the width f P2 is larger than N2 (resistane f P2 will be lesser than N2), nde B will stay high thrugh P2 irrespetive f N2 being n r ff. Case 1e: If D, is lw at rising edge f the lk, A will stay high but B will disharge t GND thrugh N2 sine P2 is ff in evaluatin phase. Thus nde B will turn n P3. The nde ij, will stay high as the width f P3 is larger than N3 (resistane f P3 will be lesser than N3). Therefre Q, will beme lw. Case 2e: If D, is high at rising edge f the lk, A will stay lw and B will als stay high sine N2 is ff. Thus nde B will turn ff P3. The nde Q, wi 11 be disharged t GND thrugh N3. Therefre Q, will beme high. The simulatin results shwed that METSPC flip flp has delay f ps and nsumes uw pwer resulting in a PDP f 1.77 fj at 6 GHz (Nminal press rner) whih is better than ETSPC tlip flp. Hene it is mre suitable fr high frequeny (GHz) peratin. The ut-ff frequeny f MOSFET in TSMC 90 nm is arund 120 GHz[9]. 936

3 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] (j) e23 > Q; 22 : e *' "..., npl,"... Pwer Dissipatin Frequeny (GHz) - "\. \ \ : <J> 40 i5 30 Q; :;: 20 Fig. 3. CIk t Q prpagatin delay f METSPC-FF Vs. frequeny Fig.3 shws the variatin f prpagatin delay and pwer dissipatin W.r.t frequeny whih are as expeted. T make sure that ur FF design is insensitive t press variatins, we did extensive simulatin f ur design arss all press rners fr varius frequeny. We have pltted the average prpagatin delay f ur FF arss all rners in Fig.4. The prpagatin delay f ur FF averaged ver all rners turns ut t be ps, 10 (NN-Nminal, FF-Fast NMOS,Fast PMOS, FS-Fast NMOS, Siw PMOS,SF-Slw nmos, Fast PMOS and SS-Slw NMOS and Siw PMOS). Sirnilarly, we have pltted the average pwer dissipatin f ur FF arss all rners in Fig.5.The average pwer dissipatin f ur FF averaged ver all rners turns ut t be f.1w. The average PDP averaged ver all rners is fj. III. SELF BLOCKING FLIP FLOP (SBFF) A. Basi Self blking Flip flp A single phase lked flip-flp, SBFF is prpsed in [4], where the authrs laim that their FF has better pwerdelay prdut than even the mst reent Sense Amplifier FF. T verify the laims f SBFF, we simulated it in TSMC 90 nm and ptimized the W /L ratis fr prper funtinality. 35 'ß:30 >- 2S : 20 ls e [!! 5! FS ; Press Crners Fig.4. Average prpagatin delay f METSPC-FF arss all rners ! FF FS NN F ",F Q; Q) [!! Q) L- Press Crners Fig.5. Average pwer dissipatin f METSPC-FF arss all rners ss Fig. 6 SBFF [4] The SBFF nsist f a dynami XOR gate in the first stage and a differential strage lath in send stage. The slave lath is ntrlled by the X and lk signal frm the XOR gate. When lk is lw, the nde X is preharged and N7 is turn ff, thus the slave lath is paque t hanges in D. At the psitive edge f the lk, signal X is evaluated t D EE> Q. Casel: When the present state D and previus state Q are same (Dt EE> Qt-I = 0), nde X disharges thrugh NI. Whih in turn will hld N6 ff; this will prevent data frm entering int strage lath as the previus data is unneessary t be hanged. Case2: When the present state D and previus state Q are different (Dt EE> Qt-l = 1), nde X will hld the VDD state. Thus bth N6 and N7 will be turned n. When the present state is high (Dt=I), N8 will be turned n, whih will pull Q t high (Qt= l) thrugh P5. Sine 937

4 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] Qt is high, N10 is turned n making Qt zer. If present state is lw (Dt= O), N9 will be turned n (sine Dt= l), whih will pull Qt t high (Qt= O) thrugh P4. Sine Qt is high, NIl is turned average pwer dissipatin f SBFF averaged ver all rners turns ut t be /.I. W. The average PDP averaged ver all rners is fj. n making Qt zer. Thus SBFF will hld the value Qt and Q t thrugh the differential lath setup in the evaluatin stage. One the Q and D beme same, signal X will disharge thrugh NI t GND. Hene hanges in D after the psitive edge f the lk will nt affet Q. After extensive simulatin f SBFF with ptimized W /L values shwn in Fig.6, we realized that this SBFF has lwer PDP than METSPC at frequenies belw 1.5 GHz. But SBFF fails t funtin as a flip flp abve l.5 GHz due t setup time nstraints. Hene, we nluded that SBFF is a better ptin fr sub 1.5 GHz peratin. 9 FF... u NN SF Press Crners : Fig.9 Average pwer dissipatin f SBFF arss all rners 100 ifi S 80 > r r. e 20 a.. "' / -- - J Prpagatin Delay... Pwer Dissipatin ---./ " a.. B. Cmparisn fthe tw Flip Flps Cmpared t the average PDP f METSPC whih is l.794 fj, the average PDP f SBFF is 68% lesser, exept that it an funtin nly at frequenies less than l.5 GHz. The PDP f METSPC-FF is higher beause the pwer nsumptin is high due t shrt iruit urrent flwing in the diret path between V DD and GND during the preharge phase Frequeny (MHz) Fig.7. k t Q prpagatin delay f SBFF Vs. frequeny Fig.7 shws the variatin f prpagatin delay and pwer dissipatin W.f.t frequeny f SBFF whih are as expeted. Sine the authrs in [4] didn't hek their FF fr press insensitivity, we verified the funtinality f the SBFF arss all press rners fr frequenies belw l.5 GHz. We have pltted the average prpagatin delay f SB FF arss all rners in Fig.8.The average prpagatin delay f SBFF averaged ver all rners turns ut t be ps. IV. HYBRID CLOCK DIVIDER (HCD) T divide high frequeny signal we are prpsing a hybrid CD struture as shwn in Fig. 10. We have used METSPC-FF in fust stage sine it has gt lesser prpagatin delay than SBFF at higher frequenies. The send stage f the CD uses SBFF beause it has gt lwer PDP than METSPC fr frequenies lesser than 1.5 GHz. The fust stage f the CD is used t nvert the high input lk frequeny t a sub-l.5 GHz frequeny. Then the send stage an implement the required 'divide-by-n' peratin using SBFF. 180 $160 S iu'140 a; 0120 '" : > 80 2 a.. 60 Q) 0> ! FS "bi Press Crners SF SS Fig. 8. Average prpagatin delay f SBFF arss all rners Similarly, we have pltted the average pwer dissipatin f ur SBFF arss all rners in Fig.9.The F CD CD F2 = F1 F1 = Fix using using I--- METSPC-FF SBFF Fig. 10. Hybrid k Divider Struture Fr illustratin nsider the HCD shwn in Fig. 12 whih des "divide by 8" peratin n a 6 GHz lk. We use tw METSPC-FFs t btain 1.5 GHz lk ("/4") in fust stage and ne SBFF in the send stage t btain 750 MHz lk ("/8"). Ix 938

5 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] ':[]DDDQDDDn 'l!d \ f\ LH ' \f\ ilu: \ [GHz \ 0 'j:d,,\750_mh: _ Z : :,: : : : n5 I mV time (n5) :, l n Fig. 11 Simulatin result f Hybrid CD fr 6GHz TSMC 90 nm tehnlgy using CADENCE SPECTRE simulatr First State Send Stage r"-" -" -" -" -" -" -" -" -" -" -' r" -" -" -" -" -'" D Q D Q D Q METPC-FF METPC-FF SBFF Q Q Q CLK f/2 Fig. 12. Hybrid k Divider Ciruit fr 'divide by 8' Perfrmane fcd under PVT variatin Sine we verified the funtinality f METSPC (upt 6 GHz) and SBFF (upt 1.5 GHz) fr press variatins (at all 4 rners), we nlude that the CD implemented using these tw flip flps will be insensitive t press variatins. T evaluate ur CD iruit under PVT variatin, we ntinue t evaluate ur CD arss the ther 2 parameters viz., vltage, V DD and temperature. The nminal supply vltage fr ur flip flp and CD was 1.1 V. T make sure that ur CD is insensitive t variatin in V DD, we varied V DD fr ± 0.2 V deviatin. Our CD was insensitive t V DD variatin f ± 0.2 V and behavir f prpagatin delay and pwer dissipatin fr VDD variatin at 6 GHz is pltted in Fig T'"" Vi 200.\--...::!!::::!:::: "...!_ =-== Prpagatin Delay (ps) 50.. Pwer(uW) O +--r--r---r---;r_.. -r--r.r_.. ""T"_y +O VDD(V) Fig.13. Plt f prpagatin delay and pwer dissipatin ver range Of VDD The nminal temperature at whih we simulated ur flip flps was 27 e. T make sure that ur CD is insensitive t variatin in temperature, we varied temperature frm 0 t 70 e. Our CD was insensitive t temperature variatin. The behavir f prpagatin delay and pwer dissipatin fr temperature variatin at 6 GHz is pltted in Fig T'""----"""T 160 Vi t::s;;:;;:::e::=-=...,... II::::I!:: ::-===-.:::: i :: f I e,. 50 f1... Prpagatin Delay (ps) Pwer(uW) Temperature (degree C) Fig.14. Plt f prpagatin delay and pwer dissipatin ver range Of VDD. 939

6 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] Fig.15. Layut f divide by 2 using METSPC -FF : > GHz 'v 3GHz _ _- ---j ps I SrrN I time (ns) Fig.16. Pst-Layut simulatin f divide by 2 using METSPC -FF fr 6 GHz Simulatin f this hybrid CD in TSMC 90 nm tehnlgy using CADENCE SPECTRE simulatr is shwn in Fig.ll. Fr a divide by 8 peratin n 6 GHz lk, ur hybrid CD nsumes average pwer f f.lw nsidering all PVT variatin. The average prpagatin delay thrugh the entire divider is 19l.34 ps arss all PVT variatin. Table 3 shws the mparisn f ur lk divider with the reent lk dividers in literature. The layut f a divide-by-2 iruit using METSPC-FF and the pst layut simulatin wavefrms fr a divide-by-2 peratin n a 6 GHz lk are shwn in Fig.15 and Fig.16 respetively. T a bl e 3 P er D rmane mpansn 0 f vanus I e kd" lvi d ers Ref. Teh VDD Operating Pwer (f.lm) (V) Frequeny (GHz) (mw/ghz) [7] 0.09 l.l [8] 0.18 l This wrk 0.09 l.l V.CONCLUSION The prpsed METSPC-FF is designed t redue pwer nsumptin and prpagatin delay at high frequeny peratin. The self blking FF presented in [4] is indeed verified t be energy effiient sine it has lwest pwer delay prdut till 1.5 GHz. Bth the flip flps and the resulting CD iruit are simulated arss PVT variatins t ensure the reliability f the design. These tw flip flps an be judiiusly used t design a high speed, lw pwer lk divider iruit. We have verified this by being able t "divide by 8" a 6 GHz lk, the entire peratin nsuming nly f.lw. Exept fr the prpagatin delay, the CD iruit des nt alter the lk wavefrm and maintains the 50% duty yle f the input lk. Hene they an be used diretly by the IP blks in a S. We have als dne the pst-layut simulatin f CD using METSPC-FF and verified that they math lsely with the transistr level simulatin results. 940

7 2013 Internatinal Cnferene n Ciruits, Pwer and Cmputing Tehnlgies [ICCPCT-2013] REFERENCES [1] R. Rajsuman, "System-n-a-hip: Design and Test", Arteh Huse In. Publishers, 2000,pp.3-7. [2] R. Y. Chen, N. Vijaykrishnan, and M. 1. Irwin, "k pwer issues in system-n-a-hip designs," in Pr. IEEE Wrkshp n VLSI, 1999, pp [3] Xia Peng Yu, Manh Anh D, Wei Meng Lim, Kiat Seng Ye, and Jian-Gu Ma, "Design and Optimizatin f the Extended True Single-Phase k-based Presaler" IEEE Transatins On Mirwave Thery And Tehniques, Vl. 54, N. 11, Pp , Nvember [4] X. Li, S. Jia, X. Liang and Y. Wang, "Self-blking flipflp design", Eletrnis Letters, Vl. 48, N. 2, 19th January [5] 1. N. Sares, Jr. and W. A. M. Van Nije, "A 1.6-GHz dual mdulus presaler using the extended true-single-phaselk CMOS iruit tehnique (E-TSPC)," IEEE J. Slid State Ciruits, vl. 34, n. 1, pp , Jan [6] Wu-Hsin Chen and Byungh Jung, "High-Speed Lw Pwer True Single-Phase k Dual-Mdulus Presalers ",IEEE Transatins On Ciruits And Systems-li: Express Briefs, Vl. 58, N. 3, pp , Marh [7] Stephan Henzler and Siegmar Keppe, "Design and Appliatin f Pwer Optimized High-Speed CMOS Frequeny Dividers," IEEE Transatins On Very Large Seale Integratin (VLSI) Systems, vl. 16, n. 11, pp , Nvember [8] Chih-Wei Chang and Yi-Jan Emery Chen," A CMOS True Single-Phase-k Divider With Differential Outputs," IEEE Mirwave And Wireless Cmpnents Letters, vl. 19, n. 12, pp , Deember [9] Kuang-Yu Cheng et al, "Develpment f 90nm InGaAs HEMTs and Benhmarking Lgi Perfrmane with Si CMOS," Cmpund Semindutr Integrated Ciruit Sympsium (CSICS), 2010 IEEE, vl., n., pp.i-4, 3-6 Ot Jhn Reuben hlds a B.E.,(Hnrs') degree in Eletrial and Eletrnis Engineering frm BITS,Pilani and M.Teh in Cmmuniatin Engineering frm VIT University, Vellre. He is urrently Assistant Prfessr with VIT University, Vellre where he is pursuing his PhD. Mhammed Zakriya. V was brn in Vellre, India. He reeived B.E., degree in Eletrnis and Cmmuniatin Engineering frm Anna University, Chennai. He is pursuing M.S (By Researh) in the Shl f Eletrnis Engineering,VIT University, Vellre. Dr. Harish M Kittur (M'10) was brn in Gadag, India. He reeived - B. S. Degree in Physis, Mathematis and Eletrnis frm the Karnataka University, India, in M.S. in Physis frm the Indian Institute f Tehnlgy, Mumbai, in M. Teh. in Slid State Tehnlgy in the year 1999 frm the Indian Institute f Tehnlgy, Madras, and Ph. D. in Physis frm the RWTH Aahen, Germany in the year He is urrently Prfessr with VIT University, Vellre, India and heads the VLSI Divisin. He has published 8 papers in Internatinal Jurnals and 8 papers in Internatinal Cnferenes. His researh interests are Lw Pwer VLSI Design, Memry Design and Naneletrnis. He is a life member f IETE and member f IEEE. 941