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1 Reprinted frm the 1987 IEEE PV Specialists Cnference Prceedings pp This material is psted here with permissin f the IEEE. Such permissin f the IEEE des nt in any way imply IEEE endrsement f any NREL prducts r services. Internal r persnal use f this material is permitted. Hwever permissin t reprint/republish this material fr advertising r prmtinal purpses r fr creating new cllective wrks fr resale r redistributin must be btained frm the IEEE by writing t pubs-permissins@ieee.rg. By chsing t view this dcument yu agree t all prvisins f the cpyright laws prtecting it. C f!pj..!.!._.2k_h.!!.-fef.!l!'l.tg' _Q...!.!!E:._1!.l!..-..Y_K'!_!Q_VJ..!'!'Q.tL.!S_.2SOL_ CELE. C. R. Osterwald Slar Energy Research Institute Glden Clrad 841 T. Glatfelter and J. Burdick Energy Cnversin Devices Inc. Try Michigan 4884 ABSTRACT It is well-knwn that the maximum pwer utput f phtvltaic devices changes with temperature. Therefre the temperature cefficients f the basic device perfrmance parameters (pen-circuit vltage shrt-circuit current fill actr and efficiency) are imprtant factrs wh1ch must be taken int accunt in the design f a phtvltaic pwer system where temperature changes ccur thrughut the day and year. This paper reprts results f experimental temperature cefficient measurements btained n a wide variety f different phtvltaic devices many f which have nt had temperature cefficient data published previus ly. INTRODUCTION It is well-knwn that phtvltaic device perfrmance and therefre slar cell maximum pwer utput changes with temperature. Hence it is imprtant t take int accunt the temperature cefficients f the basic device I-V parameters (pen-circuit vltage shrt-circuit current fill factr and efficiency r maximum pwer pint) when designing phtvltaic pwer systems fr actual utdr applicatins where temperature changes ccur thrughut the day and year. In the past hwever very little temperature cefficient data fr devices ther than crystalline silicn r GaAs has been published. The bjective f this wrk is t present a cmparisn f temperature cefficient data fr a variety f different slar cell types several f which have nt been previusly published. The data is experimentally btained and is tabulated in bth actual parameter units (mv rna mw) per degree Celcius as well as parts-per-millin per degree Celcius t enable cmparisn f the different phtvltaic devices. MEASUREMENT METHOD The temperature cefficients fr each device were determined frm the slpe f each I-V parameter versus temperature. All temperature cefficient data measured in this wrk was btained using a high-reslutin I-V measurement system which has been described elsewhere [1). The illuminated I-V measurements were perfrmed under a calibrated Spectrlab X-25 slar simulatr and the temperature f the devices was fixed t within +O.lC with a feedback-cntrlled thermelectric plate. The plate temperature was set using a platinum-rtd surface temperature prbe which had a reslutin f O.lC. Since mst f the devices did nt have bnded cntacts fur-terminal Kelvin prbe cnnectins were made t each gevice. Jhe I-V curve was then measured at 5 C (O2 C) intervals ver a temperature range frm 15 C t 6 C withut disturbing the cntacts (the prbe cnnectins). This prcedure ensured that any changes in the cell I-V parameters (especially the fill factr) were due slely t the temperature change. Fr each temperature scan a linear least-squares fit f the Jsc Vc FF and Pmax data was then perfrmed t btain the slpe and crrelatin cefficient. Typically the crrelatin cefficients were within.5 f unity; fr example the crrelatin cefficients f the linear fits fr the Vc and Isc measurements were generally within.3 f unity while the fill factr crrelatin cefficients were in the range f.994 t.996. Fr cmparisn purpses the data and the slpes were then nrmalized t the 25 C value f the linear fit. DISCUSSION AND RESULTS Tables 1 and 2 shw a summary f the results fr the varius phtvltaic devices measured and they include measurements reprted in references 2 and 3. In Table 1 the temperature cefficient f each measurement is listed withut nrmalizatin and in Table 2 the nrmalized temperature cefficients are cmpared alng with previusly published data. Figures 1-8 shw the results f the device I-V parameters versus temperature (nrmalized t the linear fit at 25 C) fr respectively: crystalline Si (Fig. 1) (Fig. 2) CulnSe /Cd(n)S (Fig. 3) GaAs duble heterstructure (ig. 4) a-si ally single-cell (Fig. 5) a-si:ge ally single-cell (Fig. 6) a-si ally same-gap tw-cell tandem (Fig. 7) and a-si:ge ally dual-gap tw-cell tandem (Fig. 8). All f the different devices shw a decrease in Vc and an increase in Jsc with increasing temperature as expected. Hwever the mst ntable feature f these measurements is the results fr the amrphus silicn (a-si) ally slar cells. All f these devices exhibit a E.:!.L! behavir f the FF and Pmax versus temperature. In additin the results shw the !87/-188 $ IEEE

2 fill factr with a nn-linear psitive temperature cefficient (FF increasing wlth-temperature ver the range 15 C t 6 C) fr the a-si ally slar cells in cntrast with a [ FF temperature cefficient fr all f the crystalline devices. This psitive FF temperature cefficient in turn results in!...x i.!..l nega.ei.!._f<!...>!...;-! ejli.cie.!l.!:! f -1 t -2 ppm/ C fr the a-si ally devices cmpared t the larger (mre negative) Pmax temperature cefficients fr the ther types f slar cells mst f which range frm -2 t -6 ppm/c. These trends as well as the nn-linear FF and Pmax temperature cefficients f the a-si ally devices can be bserved frm the tables and figures. In terms f actual utdr applicatins therefre these I-V versus temperature results mean that the a-si ally slar cells will shw less decrease in Pmax with increasing temperature than will the ther types f (crystalline) phtvltaic devices tested. Finally frm the behavir exhibited by the varius types f slar cells that were measured in this study nte that the devices with larger band gaps generally have lwer Pmax temperature cefficients than d the narrw band gap slar cells. Table 1. Temperature cefficient measurement results f the I-V parameters Ve Jsc FF and Pmax fr varius types f phtvltaic devices. Device dvc djsc dff dpmax (mv'oc) (rna/em 2 DC) (jc) (mw/cm 2 DC) (xl- 3 ) (xl- 4 ) (xl- 2 ) RF Sput tered DC Sputtered si MINP [2] Si passivated emitter [3] CulnSe 2 /Cd(n)S GaAs duble heters tructure eV AIGaAs a-si:h:f ally (*) (*) a-si:ge:h:f ally (*) (*) a-si/a-si ally (*) (*) a-si/a-si:ge ally (*) (*) (*) nn-linear 189

3 Table 2. Nrmalized temperature cefficients (ppm/c) f the I-V parameters Vc Jsc FF and Pmax fr varius types f phtvltaic devices. Device dvc djsc dff Vc Jsc FF Pmax dpmax si space cells [2] -451 t t t t -47 GaAs space cells [2] -216 t t 71-1 t t -195 si MINP [2] si passivated emitter [3] -32 RF Spu t tered DC Sputtered CulnSe 2 /Cd(n)S GaAs duble heters truc ture eV AlGaAs a-si :H:F ally -31 t t t 131 (*) -197 t - 98 (*) a-si:ge:h:f ally -389 t t t 176 (*l -197 t -12 (*) a-si/a-si ally -327 t t t 158 (*l -143 t -122 (*l a-si/a-si:ge ally -368 t t t 118 (*) -194 t -166 (*l (*) nn-linear 19

4 Figure 1. Nrmalized Vc (X) temperature fr a phtvltaic device. Jsc (+) FF () high efficiency and Pmax crystalline ( <» vs silicn >. z La 1. <1 La a O.S<I.sa.8.88.aa.8<1 N N Figure 2. Nrmalized Vc (X) Jsc temperature fr an (+) FF () and phtvltaic device. Pmax ( <> ) vs :! : a!! 1..s!:!.8.a!!.8.7!:! Figure 3. Nrmalized Vc temperature fr (X) Jsc (+) a CulnSe 2 /Cd(n)S FF () and Pmax phtvltaic device. ( <> ) vs 191

5 " I :1..4 i O.B2.8 N N g Figure 4. Nrmalized temperature device. Vee fer (X) Jsc a GaAs (+) duble FF () and Pmax () vs heterstructure phtvltaic " > 1.8 LD4 i S N N T"mp.... tur" [d8 C) Figure 5. Nrmalized Ve (X) temperature fr an device. Jsc (+) FF a-si :H:F ally () and Pmax () vs ITO/pin/S5 phtvltaic 1 " 1. 8 L a D.SIl N N Temperllture [deo C) Figure 6. Nrmalized temperature device. Vee fer (xl an Jsc ( +) a-si:ge:h:f FF () and Pmax () vs ally ITO/pin/S8 phtvltaic 192

6 " L4 : 1. 2 t 1. ".9S.96 ;.94.B2.8 " " Temp"rature [<I... CJ Figure 7. Nrmalized Vee (X) temperature fr phtvltaic device. Jse an (+) FF a-si/a-si () and ally Pmax () vs :I I 1..8e c.sa ".84 z.e2 O.e " " " Tl!.p.. ""tur" [dg C) Figure 8. Nrmalized Ve ex) temperature fr an phtvltaic device. Isc (+) FF a-si/a-si:ge () and ally Pmax () vs ACKNOWLEDGEMENTS This wrk was supprted by the U.S. Department f Energy thrugh cntract DE-AC2-83CGI93. We wish t thank Tim Cutts f SERI fr prviding the ITO/lP devices. The GaAs duble heterstructure CulnSe!Cd(n) 5 and AIGaAs devices were supplied 2 t SERr thrugh subcntracts frm MIT Lincln Labratries Being Aerspace Cmpany and Spire Crpratin respectively and we aknwledge their cntributins. The Energy Cnversin Devices' advanced phtvltaic device research and develpment grup fabricated the a-si ally slar cells used in these measurements REFERENCES K. A. Emery and C. R. Osterwald IIS l ar Cell Efficiency Measurements" Slar Ce 11s Vl. 17 (1986) p M. A. Green "Silicn Slar Sensitivity" (1982) p. 97. K. A. Emery and A. W. Blakers Cells with Reduced Temperature Electrnics Letters Vl. 18 M. A. Green A. W. Blakers C. R. Osterwald "Characterizatin f High-efficiency Silicn Slar Cells" Jurnal f Applied Physics Vl. 58 (1985) p